diff options
Diffstat (limited to 'common/dpdk/recipes-extended/dpdk/dpdk/dpdk-dev-v4-11-20-crypto-ccp-support-3des-cipher-algo.patch')
-rw-r--r-- | common/dpdk/recipes-extended/dpdk/dpdk/dpdk-dev-v4-11-20-crypto-ccp-support-3des-cipher-algo.patch | 244 |
1 files changed, 0 insertions, 244 deletions
diff --git a/common/dpdk/recipes-extended/dpdk/dpdk/dpdk-dev-v4-11-20-crypto-ccp-support-3des-cipher-algo.patch b/common/dpdk/recipes-extended/dpdk/dpdk/dpdk-dev-v4-11-20-crypto-ccp-support-3des-cipher-algo.patch deleted file mode 100644 index b51879be..00000000 --- a/common/dpdk/recipes-extended/dpdk/dpdk/dpdk-dev-v4-11-20-crypto-ccp-support-3des-cipher-algo.patch +++ /dev/null @@ -1,244 +0,0 @@ -From patchwork Fri Mar 9 08:35:11 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [dpdk-dev,v4,11/20] crypto/ccp: support 3des cipher algo -From: Ravi Kumar <ravi1.kumar@amd.com> -X-Patchwork-Id: 35810 -X-Patchwork-Delegate: pablo.de.lara.guarch@intel.com -Message-Id: <1520584520-130522-11-git-send-email-Ravi1.kumar@amd.com> -List-Id: dev.dpdk.org -To: dev@dpdk.org -Cc: pablo.de.lara.guarch@intel.com -Date: Fri, 9 Mar 2018 03:35:11 -0500 - -Signed-off-by: Ravi Kumar <Ravi1.kumar@amd.com> ---- - drivers/crypto/ccp/ccp_crypto.c | 132 ++++++++++++++++++++++++++++++++++++++- - drivers/crypto/ccp/ccp_crypto.h | 3 + - drivers/crypto/ccp/ccp_pmd_ops.c | 20 ++++++ - 3 files changed, 154 insertions(+), 1 deletion(-) - -diff --git a/drivers/crypto/ccp/ccp_crypto.c b/drivers/crypto/ccp/ccp_crypto.c -index b097355..0660761 100644 ---- a/drivers/crypto/ccp/ccp_crypto.c -+++ b/drivers/crypto/ccp/ccp_crypto.c -@@ -80,7 +80,7 @@ ccp_configure_session_cipher(struct ccp_session *sess, - const struct rte_crypto_sym_xform *xform) - { - const struct rte_crypto_cipher_xform *cipher_xform = NULL; -- size_t i; -+ size_t i, j, x; - - cipher_xform = &xform->cipher; - -@@ -115,6 +115,11 @@ ccp_configure_session_cipher(struct ccp_session *sess, - sess->cipher.um.aes_mode = CCP_AES_MODE_CBC; - sess->cipher.engine = CCP_ENGINE_AES; - break; -+ case RTE_CRYPTO_CIPHER_3DES_CBC: -+ sess->cipher.algo = CCP_CIPHER_ALGO_3DES_CBC; -+ sess->cipher.um.des_mode = CCP_DES_MODE_CBC; -+ sess->cipher.engine = CCP_ENGINE_3DES; -+ break; - default: - CCP_LOG_ERR("Unsupported cipher algo"); - return -1; -@@ -137,6 +142,20 @@ ccp_configure_session_cipher(struct ccp_session *sess, - sess->cipher.key_ccp[sess->cipher.key_length - i - 1] = - sess->cipher.key[i]; - break; -+ case CCP_ENGINE_3DES: -+ if (sess->cipher.key_length == 16) -+ sess->cipher.ut.des_type = CCP_DES_TYPE_128; -+ else if (sess->cipher.key_length == 24) -+ sess->cipher.ut.des_type = CCP_DES_TYPE_192; -+ else { -+ CCP_LOG_ERR("Invalid cipher key length"); -+ return -1; -+ } -+ for (j = 0, x = 0; j < sess->cipher.key_length/8; j++, x += 8) -+ for (i = 0; i < 8; i++) -+ sess->cipher.key_ccp[(8 + x) - i - 1] = -+ sess->cipher.key[i + x]; -+ break; - default: - CCP_LOG_ERR("Invalid CCP Engine"); - return -ENOTSUP; -@@ -280,6 +299,10 @@ ccp_cipher_slot(struct ccp_session *session) - count = 2; - /**< op + passthrough for iv */ - break; -+ case CCP_CIPHER_ALGO_3DES_CBC: -+ count = 2; -+ /**< op + passthrough for iv */ -+ break; - default: - CCP_LOG_ERR("Unsupported cipher algo %d", - session->cipher.algo); -@@ -478,6 +501,109 @@ ccp_perform_aes(struct rte_crypto_op *op, - return 0; - } - -+static int -+ccp_perform_3des(struct rte_crypto_op *op, -+ struct ccp_queue *cmd_q, -+ struct ccp_batch_info *b_info) -+{ -+ struct ccp_session *session; -+ union ccp_function function; -+ unsigned char *lsb_buf; -+ struct ccp_passthru pst; -+ struct ccp_desc *desc; -+ uint32_t tail; -+ uint8_t *iv; -+ phys_addr_t src_addr, dest_addr, key_addr; -+ -+ session = (struct ccp_session *)get_session_private_data( -+ op->sym->session, -+ ccp_cryptodev_driver_id); -+ -+ iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset); -+ switch (session->cipher.um.des_mode) { -+ case CCP_DES_MODE_CBC: -+ lsb_buf = &(b_info->lsb_buf[b_info->lsb_buf_idx*CCP_SB_BYTES]); -+ b_info->lsb_buf_idx++; -+ -+ rte_memcpy(lsb_buf + (CCP_SB_BYTES - session->iv.length), -+ iv, session->iv.length); -+ -+ pst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *) lsb_buf); -+ pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES); -+ pst.len = CCP_SB_BYTES; -+ pst.dir = 1; -+ pst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP; -+ pst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT; -+ ccp_perform_passthru(&pst, cmd_q); -+ break; -+ case CCP_DES_MODE_CFB: -+ case CCP_DES_MODE_ECB: -+ CCP_LOG_ERR("Unsupported DES cipher mode"); -+ return -ENOTSUP; -+ } -+ -+ src_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src, -+ op->sym->cipher.data.offset); -+ if (unlikely(op->sym->m_dst != NULL)) -+ dest_addr = -+ rte_pktmbuf_mtophys_offset(op->sym->m_dst, -+ op->sym->cipher.data.offset); -+ else -+ dest_addr = src_addr; -+ -+ key_addr = rte_mem_virt2phy(session->cipher.key_ccp); -+ -+ desc = &cmd_q->qbase_desc[cmd_q->qidx]; -+ -+ memset(desc, 0, Q_DESC_SIZE); -+ -+ /* prepare desc for des command */ -+ CCP_CMD_ENGINE(desc) = CCP_ENGINE_3DES; -+ -+ CCP_CMD_SOC(desc) = 0; -+ CCP_CMD_IOC(desc) = 0; -+ CCP_CMD_INIT(desc) = 1; -+ CCP_CMD_EOM(desc) = 1; -+ CCP_CMD_PROT(desc) = 0; -+ -+ function.raw = 0; -+ CCP_DES_ENCRYPT(&function) = session->cipher.dir; -+ CCP_DES_MODE(&function) = session->cipher.um.des_mode; -+ CCP_DES_TYPE(&function) = session->cipher.ut.des_type; -+ CCP_CMD_FUNCTION(desc) = function.raw; -+ -+ CCP_CMD_LEN(desc) = op->sym->cipher.data.length; -+ -+ CCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr); -+ CCP_CMD_SRC_HI(desc) = high32_value(src_addr); -+ CCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM; -+ -+ CCP_CMD_DST_LO(desc) = ((uint32_t)dest_addr); -+ CCP_CMD_DST_HI(desc) = high32_value(dest_addr); -+ CCP_CMD_DST_MEM(desc) = CCP_MEMTYPE_SYSTEM; -+ -+ CCP_CMD_KEY_LO(desc) = ((uint32_t)key_addr); -+ CCP_CMD_KEY_HI(desc) = high32_value(key_addr); -+ CCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM; -+ -+ if (session->cipher.um.des_mode) -+ CCP_CMD_LSB_ID(desc) = cmd_q->sb_iv; -+ -+ cmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE; -+ -+ rte_wmb(); -+ -+ /* Write the new tail address back to the queue register */ -+ tail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE); -+ CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail); -+ /* Turn the queue back on using our cached control register */ -+ CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, -+ cmd_q->qcontrol | CMD_Q_RUN); -+ -+ op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED; -+ return 0; -+} -+ - static inline int - ccp_crypto_cipher(struct rte_crypto_op *op, - struct ccp_queue *cmd_q, -@@ -503,6 +629,10 @@ ccp_crypto_cipher(struct rte_crypto_op *op, - result = ccp_perform_aes(op, cmd_q, b_info); - b_info->desccnt += 1; - break; -+ case CCP_CIPHER_ALGO_3DES_CBC: -+ result = ccp_perform_3des(op, cmd_q, b_info); -+ b_info->desccnt += 2; -+ break; - default: - CCP_LOG_ERR("Unsupported cipher algo %d", - session->cipher.algo); -diff --git a/drivers/crypto/ccp/ccp_crypto.h b/drivers/crypto/ccp/ccp_crypto.h -index 614cd47..d528ec9 100644 ---- a/drivers/crypto/ccp/ccp_crypto.h -+++ b/drivers/crypto/ccp/ccp_crypto.h -@@ -57,6 +57,9 @@ - #define CCP_AES_ENCRYPT(p) ((p)->aes.encrypt) - #define CCP_AES_MODE(p) ((p)->aes.mode) - #define CCP_AES_TYPE(p) ((p)->aes.type) -+#define CCP_DES_ENCRYPT(p) ((p)->des.encrypt) -+#define CCP_DES_MODE(p) ((p)->des.mode) -+#define CCP_DES_TYPE(p) ((p)->des.type) - #define CCP_PT_BYTESWAP(p) ((p)->pt.byteswap) - #define CCP_PT_BITWISE(p) ((p)->pt.bitwise) - -diff --git a/drivers/crypto/ccp/ccp_pmd_ops.c b/drivers/crypto/ccp/ccp_pmd_ops.c -index 5f56242..3a16be8 100644 ---- a/drivers/crypto/ccp/ccp_pmd_ops.c -+++ b/drivers/crypto/ccp/ccp_pmd_ops.c -@@ -99,6 +99,26 @@ static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { - }, } - }, } - }, -+ { /* 3DES CBC */ -+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, -+ {.sym = { -+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, -+ {.cipher = { -+ .algo = RTE_CRYPTO_CIPHER_3DES_CBC, -+ .block_size = 8, -+ .key_size = { -+ .min = 16, -+ .max = 24, -+ .increment = 8 -+ }, -+ .iv_size = { -+ .min = 8, -+ .max = 8, -+ .increment = 0 -+ } -+ }, } -+ }, } -+ }, - RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() - }; - |