diff options
263 files changed, 1294 insertions, 18926 deletions
diff --git a/common/conf/layer.conf b/common/conf/layer.conf index 8d6e5eff..8ce97511 100644 --- a/common/conf/layer.conf +++ b/common/conf/layer.conf @@ -10,5 +10,6 @@ BBFILES += "${@' '.join('${LAYERDIR}/%s/recipes*/*/*.bbappend' % layer \ BBFILE_COLLECTIONS += "amd" BBFILE_PRIORITY_amd = "13" BBFILE_PATTERN_amd = "^${LAYERDIR}/" +LAYERSERIES_COMPAT_amd = "sumo" LICENSE_PATH += "${LAYERDIR}/licenses" diff --git a/common/conf/machine/include/amd-common-configurations.inc b/common/conf/machine/include/amd-common-configurations.inc index 45810f96..f4d6fa66 100644 --- a/common/conf/machine/include/amd-common-configurations.inc +++ b/common/conf/machine/include/amd-common-configurations.inc @@ -1,14 +1,11 @@ +require conf/machine/include/amd-features.inc + POKY_DEFAULT_DISTRO_FEATURES_remove = "wayland" PREFERRED_PROVIDER_jpeg ?= "jpeg" PREFERRED_PROVIDER_jpeg-native ?= "jpeg-native" -PREFERRED_PROVIDER_llvm ?= "llvm3.9" PREFERRED_VERSION_linux-yocto ?= "4.4%" -PREFERRED_VERSION_mesa ?= "12.0.3+git%" -PREFERRED_VERSION_gstreamer1.0-omx ?= "git+git%" PREFERRED_VERSION_libav ?= "9.18" -PREFERRED_VERSION_grub ?= "2.00+AUTOINC+%" -PREFERRED_VERSION_grub-efi ?= "2.00+AUTOINC+%" MULTILIBS ?= "" require conf/multilib.conf @@ -47,14 +44,9 @@ APPEND += "${APPEND_ADDITIONAL}" EXTRA_OECONF_append_pn-matchbox-panel-2 = " --with-battery=acpi" -# Once we switch to using the xserver-nodm-init version -# from poky, following lines should be dropped -# Currently there's a debian packaging issue with it -VIRTUAL-RUNTIME_xserver_common_pn-packagegroup-core-x11 = "xserver-common" -PREFERRED_VERSION_xserver-nodm-init ?= "2.0" - -SPLASH ?= "psplash" - IMAGE_FSTYPES += "hddimg iso" IMAGE_OVERHEAD_FACTOR = "1.1" + +MACHINE_FEATURES_append_amdgpu = " x11" +MACHINE_FEATURES_append_radeon = " x11" diff --git a/common/conf/machine/include/amd-common.inc b/common/conf/machine/include/amd-common.inc deleted file mode 100644 index 16518cee..00000000 --- a/common/conf/machine/include/amd-common.inc +++ /dev/null @@ -1,14 +0,0 @@ -IMAGE_INSTALL_append += " \ - bc \ -" - -GST_PACKAGES = " \ - ${@bb.utils.contains('DISTRO_FEATURES', 'x11',' \ - gstreamer1.0-meta-x11-base \ - gstreamer1.0-meta-audio \ - gstreamer1.0-meta-debug \ - gstreamer1.0-meta-video \ - gstreamer1.0-omx \ - gstreamer1.0-vaapi', '', d)}" - -IMAGE_INSTALL_append_mel += " ${@bb.utils.contains("DISTRO", "mel", "${GST_PACKAGES}", "", d)}" diff --git a/common/conf/machine/include/amd-features.inc b/common/conf/machine/include/amd-features.inc new file mode 100644 index 00000000..b6717127 --- /dev/null +++ b/common/conf/machine/include/amd-features.inc @@ -0,0 +1,80 @@ +# This file defines AMD Features that can be added as EXTRA_IMAGE_FEATURES to +# different machines based on what is supported on a machine. This gives a broad +# flexibility and control over packages being installed on a machine for any image +# without needing to create bbappends for all the images that are to be supported. +# +# > Each feature can contain packages and packagegroups as its components. +# > Feature components can be dependent on DISTRO, IMAGE_FEATURE, or any variable +# in general. e.g.: Components of "amd-feature-graphics" may be dependent on +# "x11-base" as an IMAGE_FEATURE. Some packages may only be included for a +# specific DISTRO. Some packages may only be installed if user allows them in +# local.conf etc. +# > Each machine must add the required features to EXTRA_IMAGE_FEATURES in its +# own machine config file. +# > All required features must be added to a machine regardless of the image +# being built, but make sure that feature components are included based on +# dependency conditions. e.g. say "amd-feature-graphics" was added to a machine +# that supported graphics, but components of this feature must not be installed +# on an image that is only console based such as "core-image-base", therefore +# such components must depend on an IMAGE_FEATURE that is based on graphics +# such as "x11-base". +# > Each machine can also override feature components in its own machine config +# when adding the feature to EXTRA_IMAGE_FEATURES. e.g.: A feature may be added +# to a specific machine with minimal (or extended) packages based on requirement. +# +# Features are classified as: +# +# * amd-common-pkgs : Common packages to be added to all machines +# * amd-feature-multimedia : Multimedia packages (it does not depend on graphics because a machine may not have a GUI but could play videos and sounds from console) +# * amd-feature-graphics : Graphics packages +# * amd-feature-networking : Networking packages +# * amd-feature-debug-profile : Debugging and Profiling tools +# * <add more features here> : <feature summary> + +# Add common feartures to be supported for all machines here +EXTRA_IMAGE_FEATURES += "amd-common-pkgs amd-feature-multimedia" + +GSTREAMER_PKGS ?= " \ + ${@bb.utils.contains("IMAGE_FEATURES", "x11-base", "gstreamer1.0-meta-x11-base", "", d)} \ + ${@bb.utils.contains("IMAGE_FEATURES", "tools-audio", "gstreamer1.0-meta-audio", "", d)} \ + gstreamer1.0-meta-debug \ + gstreamer1.0-meta-video \ + gstreamer1.0-omx \ + gstreamer1.0-vaapi \ +" +VULKAN_PKGS ?= "" +CODEXL_PKGS ?= "" +DPDK_PKGS ?= "" + +# Additional packages can be added to the following feature specific +# variables from each machine's config file +AMD_FEATURE_MULTIMEDIA_PKGS ?= "" +AMD_FEATURE_GRAPHICS_PKGS ?= "" +AMD_FEATURE_NETWORKING_PKGS ?= "" +AMD_FEATURE_DEBUG_PROFILE_PKGS ?= "" + +FEATURE_PACKAGES_amd-common-pkgs = "\ + bc \ +" + +FEATURE_PACKAGES_amd-feature-multimedia = "\ + ${@bb.utils.contains("DISTRO", "mel", "${GSTREAMER_PKGS}", "", d)} \ + ${AMD_FEATURE_MULTIMEDIA_PKGS} \ +" + +FEATURE_PACKAGES_amd-feature-graphics = "\ + ${@bb.utils.contains("IMAGE_FEATURES", "x11-base", bb.utils.contains("INCLUDE_VULKAN", "yes", "${VULKAN_PKGS}", "", d), "", d)} \ + ${AMD_FEATURE_GRAPHICS_PKGS} \ +" +FEATURE_PACKAGES_amd-feature-graphics_append_amdgpu = " ${@bb.utils.contains("IMAGE_FEATURES", "x11-base", "mesa-demos", "", d)}" +FEATURE_PACKAGES_amd-feature-graphics_append_radeon = " ${@bb.utils.contains("IMAGE_FEATURES", "x11-base", "mesa-demos", "", d)}" + +FEATURE_PACKAGES_amd-feature-networking = "\ + ${@bb.utils.contains("DISTRO", "mel", "${DPDK_PKGS} strongswan", "", d)} \ + ${AMD_FEATURE_NETWORKING_PKGS} \ +" + +FEATURE_PACKAGES_amd-feature-debug-profile = "\ + ${@bb.utils.contains("INCLUDE_CODEXL", "yes", "${CODEXL_PKGS}", "", d)} \ + ${AMD_FEATURE_DEBUG_PROFILE_PKGS} \ +" diff --git a/common/dpdk/recipes-core/images/console-image.bbappend b/common/dpdk/recipes-core/images/console-image.bbappend deleted file mode 100644 index f5527e32..00000000 --- a/common/dpdk/recipes-core/images/console-image.bbappend +++ /dev/null @@ -1,3 +0,0 @@ -IMAGE_INSTALL_append_snowyowl = " dpdk \ - dpdk-examples \ - dpdk-test" diff --git a/common/mel-support/recipes-core/meta/archive-release.bbappend b/common/mel-support/recipes-core/meta/archive-release.bbappend index 0b80e4b3..8839981b 100644 --- a/common/mel-support/recipes-core/meta/archive-release.bbappend +++ b/common/mel-support/recipes-core/meta/archive-release.bbappend @@ -1,2 +1,2 @@ -IMAGE_EXTENSION_live_amd := "${@oe_filter_out('iso', '${IMAGE_EXTENSION_live}', d)}" +IMAGE_EXTENSION_live_amd := "${@oe.utils.str_filter_out('iso', '${IMAGE_EXTENSION_live}', d)}" ARCHIVE_RELEASE_IMAGE_FSTYPES_EXCLUDE_amd = "iso" diff --git a/common/mel/recipes-core/images/console-image.bbappend b/common/mel/recipes-core/images/console-image.bbappend deleted file mode 100644 index c656893c..00000000 --- a/common/mel/recipes-core/images/console-image.bbappend +++ /dev/null @@ -1,3 +0,0 @@ -require conf/machine/include/amd-common.inc - -IMAGE_INSTALL_append_snowyowl = " strongswan" diff --git a/common/mel/recipes-core/images/core-image-minimal-install-initramfs.bbappend b/common/mel/recipes-core/images/core-image-minimal-install-initramfs.bbappend deleted file mode 100644 index f8f21eea..00000000 --- a/common/mel/recipes-core/images/core-image-minimal-install-initramfs.bbappend +++ /dev/null @@ -1,3 +0,0 @@ -# This is required so extrausers functionality can be used -# with dependant images. -PACKAGE_INSTALL += "shadow" diff --git a/common/recipes-bsp/grub/files/0001-Disable-mfpmath-sse-as-well-when-SSE-is-disabled.patch b/common/recipes-bsp/grub/files/0001-Disable-mfpmath-sse-as-well-when-SSE-is-disabled.patch deleted file mode 100644 index ce3238f3..00000000 --- a/common/recipes-bsp/grub/files/0001-Disable-mfpmath-sse-as-well-when-SSE-is-disabled.patch +++ /dev/null @@ -1,46 +0,0 @@ -From fb7b827a56b1f92f882d0f5ef130acc968b23293 Mon Sep 17 00:00:00 2001 -From: Khem Raj <raj.khem@gmail.com> -Date: Wed, 13 Jan 2016 19:17:31 +0000 -Subject: [PATCH] Disable -mfpmath=sse as well when SSE is disabled - -Fixes - -configure:20574: i586-poky-linux-gcc -m32 -march=core2 -msse3 --mtune=generic -mfpmath=sse ---sysroot=/usr/local/dev/yocto/grubtest2/build/tmp/sysroots/emenlow -o -conftest -O2 -pipe -g -feliminate-unused-debug-types -Wall -W -Wshadow --Wpointer-arith -Wmissing-prototypes -Wundef -Wstrict-prototypes -g --falign-jumps=1 -falign-loops=1 -falign-functions=1 -mno-mmx -mno-sse --mno-sse2 -mno-3dnow -fno-dwarf2-cfi-asm -m32 -fno-stack-protector --mno-stack-arg-probe -Werror -nostdlib -Wl,--defsym,___main=0x8100 --Wall -W -I$(top_srcdir)/include -I$(top_builddir)/include --DGRUB_MACHINE_PCBIOS=1 -DGRUB_MACHINE=I386_PC -Wl,-O1 --Wl,--hash-style=gnu -Wl,--as-needed conftest.c >&5 -conftest.c:1:0: error: SSE instruction set disabled, using 387 -arithmetics [-Werror] -cc1: all warnings being treated as errors - -Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com> -Signed-off-by: Khem Raj <raj.khem@gmail.com> ---- -Upstream-Status: Pending - - configure.ac | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/configure.ac b/configure.ac -index 26d2f33..9ce56de 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -783,7 +783,7 @@ fi - if ( test "x$target_cpu" = xi386 || test "x$target_cpu" = xx86_64 ) && test "x$platform" != xemu; then - # Some toolchains enable these features by default, but they need - # registers that aren't set up properly in GRUB. -- TARGET_CFLAGS="$TARGET_CFLAGS -mno-mmx -mno-sse -mno-sse2 -mno-sse3 -mno-3dnow" -+ TARGET_CFLAGS="$TARGET_CFLAGS -mno-mmx -mno-sse -mno-sse2 -mno-sse3 -mno-3dnow -mfpmath=387" - fi - - # GRUB doesn't use float or doubles at all. Yet some toolchains may decide --- -2.7.0 - diff --git a/common/recipes-bsp/grub/files/0001-grub.d-10_linux.in-add-oe-s-kernel-name.patch b/common/recipes-bsp/grub/files/0001-grub.d-10_linux.in-add-oe-s-kernel-name.patch deleted file mode 100644 index d5bfaa17..00000000 --- a/common/recipes-bsp/grub/files/0001-grub.d-10_linux.in-add-oe-s-kernel-name.patch +++ /dev/null @@ -1,56 +0,0 @@ -From b512c77222a8b133d7dd71a0dcef081a921d97d4 Mon Sep 17 00:00:00 2001 -From: Khem Raj <raj.khem@gmail.com> -Date: Wed, 13 Jan 2016 19:28:00 +0000 -Subject: [PATCH] grub.d/10_linux.in: add oe's kernel name - -Our kernel's name is bzImage, we need add it to grub.d/10_linux.in so -that the grub-mkconfig and grub-install can work correctly. - -We only need add the bzImage to util/grub.d/10_linux.in, but also add it -to util/grub.d/20_linux_xen.in to keep compatibility. - -Signed-off-by: Robert Yang <liezhi.yang@windriver.com> -Signed-off-by: Khem Raj <raj.khem@gmail.com> ---- -Upstream-Status: Inappropriate [OE specific] - - util/grub.d/10_linux.in | 6 +++--- - util/grub.d/20_linux_xen.in | 2 +- - 2 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/util/grub.d/10_linux.in b/util/grub.d/10_linux.in -index 859b608..946be5d 100644 ---- a/util/grub.d/10_linux.in -+++ b/util/grub.d/10_linux.in -@@ -148,12 +148,12 @@ machine=`uname -m` - case "x$machine" in - xi?86 | xx86_64) - list= -- for i in /boot/vmlinuz-* /vmlinuz-* /boot/kernel-* ; do -+ for i in /boot/bzImage-* /bzImage-* /boot/vmlinuz-* /vmlinuz-* /boot/kernel-* ; do - if grub_file_is_not_garbage "$i" ; then list="$list $i" ; fi - done ;; -- *) -+ *) - list= -- for i in /boot/vmlinuz-* /boot/vmlinux-* /vmlinuz-* /vmlinux-* /boot/kernel-* ; do -+ for i in /boot/bzImage-* /boot/vmlinuz-* /boot/vmlinux-* /bzImage-* /vmlinuz-* /vmlinux-* /boot/kernel-* ; do - if grub_file_is_not_garbage "$i" ; then list="$list $i" ; fi - done ;; - esac -diff --git a/util/grub.d/20_linux_xen.in b/util/grub.d/20_linux_xen.in -index f532fb9..1994244 100644 ---- a/util/grub.d/20_linux_xen.in -+++ b/util/grub.d/20_linux_xen.in -@@ -138,7 +138,7 @@ EOF - } - - linux_list= --for i in /boot/vmlinu[xz]-* /vmlinu[xz]-* /boot/kernel-*; do -+for i in /boot/bzImage[xz]-* /bzImage[xz]-* /boot/vmlinu[xz]-* /vmlinu[xz]-* /boot/kernel-*; do - if grub_file_is_not_garbage "$i"; then - basename=$(basename $i) - version=$(echo $basename | sed -e "s,^[^0-9]*-,,g") --- -2.7.0 - diff --git a/common/recipes-bsp/grub/files/autogen.sh-exclude-pc.patch b/common/recipes-bsp/grub/files/autogen.sh-exclude-pc.patch deleted file mode 100644 index fc5aa4e3..00000000 --- a/common/recipes-bsp/grub/files/autogen.sh-exclude-pc.patch +++ /dev/null @@ -1,34 +0,0 @@ -From ff8f68cc48fd3c30d55e1d570d51f2e0952c968e Mon Sep 17 00:00:00 2001 -From: Robert Yang <liezhi.yang@windriver.com> -Date: Sat, 25 Jan 2014 23:49:44 -0500 -Subject: [PATCH] autogen.sh: exclude .pc from po/POTFILES.in - -Exclude the .pc from po/POTFILES.in since quilt uses "patch --backup", -which will create the backup file under .pc, this may cause unexpected -errors, for example, on CentOS 5.x, if the backup file is null -(newfile), it's mode will be 000, then we will get errors when xgettext -try to read it. - -Upstream-Status: Inappropriate [OE specific] - -Signed-off-by: Robert Yang <liezhi.yang@windriver.com> ---- - autogen.sh | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/autogen.sh b/autogen.sh -index 7424428..843619e 100755 ---- a/autogen.sh -+++ b/autogen.sh -@@ -5,7 +5,7 @@ set -e - export LC_COLLATE=C - unset LC_ALL - --find . -iname '*.[ch]' ! -ipath './grub-core/lib/libgcrypt-grub/*' ! -ipath './build-aux/*' ! -ipath './grub-core/lib/libgcrypt/src/misc.c' ! -ipath './grub-core/lib/libgcrypt/src/global.c' ! -ipath './grub-core/lib/libgcrypt/src/secmem.c' ! -ipath './util/grub-gen-widthspec.c' ! -ipath './util/grub-gen-asciih.c' |sort > po/POTFILES.in -+find . -iname '*.[ch]' ! -ipath './grub-core/lib/libgcrypt-grub/*' ! -ipath './build-aux/*' ! -ipath './grub-core/lib/libgcrypt/src/misc.c' ! -ipath './grub-core/lib/libgcrypt/src/global.c' ! -ipath './grub-core/lib/libgcrypt/src/secmem.c' ! -ipath './util/grub-gen-widthspec.c' ! -ipath './util/grub-gen-asciih.c' ! -path './.pc/*' | sort > po/POTFILES.in - find util -iname '*.in' ! -name Makefile.in |sort > po/POTFILES-shell.in - - echo "Importing unicode..." --- -1.7.10.4 - diff --git a/common/recipes-bsp/grub/files/cfg b/common/recipes-bsp/grub/files/cfg deleted file mode 100644 index 8ca53d24..00000000 --- a/common/recipes-bsp/grub/files/cfg +++ /dev/null @@ -1,2 +0,0 @@ -search.file ($cmdpath)/EFI/BOOT/grub.cfg root -set prefix=($root)/EFI/BOOT diff --git a/common/recipes-bsp/grub/grub-efi_git.bb b/common/recipes-bsp/grub/grub-efi_git.bb deleted file mode 100644 index 000912d2..00000000 --- a/common/recipes-bsp/grub/grub-efi_git.bb +++ /dev/null @@ -1,78 +0,0 @@ -require recipes-bsp/grub/grub2.inc - -DEFAULT_PREFERENCE = "-1" - -DEPENDS_class-target = "grub-efi-native" -RDEPENDS_${PN}_class-target = "diffutils freetype efibootmgr" -PR = "r3" - -FILESEXTRAPATHS =. "${FILE_DIRNAME}/grub-git:" - -PV = "2.00+${SRCPV}" -SRCREV = "7a5b301e3adb8e054288518a325135a1883c1c6c" -SRC_URI = "git://git.savannah.gnu.org/grub.git \ - file://cfg \ - file://0001-Disable-mfpmath-sse-as-well-when-SSE-is-disabled.patch \ - file://autogen.sh-exclude-pc.patch \ - file://0001-grub.d-10_linux.in-add-oe-s-kernel-name.patch \ - " - -S = "${WORKDIR}/git" - -# Determine the target arch for the grub modules -python __anonymous () { - import re - target = d.getVar('TARGET_ARCH', True) - if target == "x86_64": - grubtarget = 'x86_64' - grubimage = "bootx64.efi" - elif re.match('i.86', target): - grubtarget = 'i386' - grubimage = "bootia32.efi" - else: - raise bb.parse.SkipPackage("grub-efi is incompatible with target %s" % target) - d.setVar("GRUB_TARGET", grubtarget) - d.setVar("GRUB_IMAGE", grubimage) -} - -inherit deploy - -CACHED_CONFIGUREVARS += "ac_cv_path_HELP2MAN=" -EXTRA_OECONF = "--with-platform=efi --disable-grub-mkfont \ - --enable-efiemu=no --program-prefix='' \ - --enable-liblzma=no --enable-device-mapper=no --enable-libzfs=no" - -EXTRA_OECONF += "${@bb.utils.contains('DISTRO_FEATURES', 'largefile', '--enable-largefile', '--disable-largefile', d)}" - -# ldm.c:114:7: error: trampoline generated for nested function 'hook' [-Werror=trampolines] -# and many other places in the grub code when compiled with some native gcc compilers (specifically, gentoo) -CFLAGS_append_class-native = " -Wno-error=trampolines" - -do_install_class-native() { - install -d ${D}${bindir} - install -m 755 grub-mkimage ${D}${bindir} -} - -GRUB_BUILDIN ?= "boot linux ext2 fat serial part_msdos part_gpt normal efi_gop iso9660 search" - -do_deploy() { - # Search for the grub.cfg on the local boot media by using the - # built in cfg file provided via this recipe - grub-mkimage -c ../cfg -p /EFI/BOOT -d ./grub-core/ \ - -O ${GRUB_TARGET}-efi -o ./${GRUB_IMAGE} \ - ${GRUB_BUILDIN} - install -m 644 ${B}/${GRUB_IMAGE} ${DEPLOYDIR} -} - -do_deploy_class-native() { - : -} - -addtask deploy after do_install before do_build - -FILES_${PN} += "${libdir}/grub/${GRUB_TARGET}-efi \ - ${datadir}/grub \ - " - -BBCLASSEXTEND = "native" - diff --git a/common/recipes-core/images/core-image-base.bbappend b/common/recipes-core/images/core-image-base.bbappend deleted file mode 100644 index cb597e98..00000000 --- a/common/recipes-core/images/core-image-base.bbappend +++ /dev/null @@ -1 +0,0 @@ -require conf/machine/include/amd-common.inc diff --git a/common/recipes-core/images/core-image-minimal-initramfs.bbappend b/common/recipes-core/images/core-image-minimal-initramfs.bbappend deleted file mode 100644 index f8f21eea..00000000 --- a/common/recipes-core/images/core-image-minimal-initramfs.bbappend +++ /dev/null @@ -1,3 +0,0 @@ -# This is required so extrausers functionality can be used -# with dependant images. -PACKAGE_INSTALL += "shadow" diff --git a/common/recipes-core/initrdscripts/files/0001-init-install.sh-Don-t-set-quiet-kernel-option-in-ins.patch b/common/recipes-core/initrdscripts/files/0001-init-install.sh-Don-t-set-quiet-kernel-option-in-ins.patch index 7738fc76..c42438d4 100644 --- a/common/recipes-core/initrdscripts/files/0001-init-install.sh-Don-t-set-quiet-kernel-option-in-ins.patch +++ b/common/recipes-core/initrdscripts/files/0001-init-install.sh-Don-t-set-quiet-kernel-option-in-ins.patch @@ -1,38 +1,38 @@ -From d95ce99d4d7e968ca003b17379db482ade25f66e Mon Sep 17 00:00:00 2001 -From: Drew Moseley <drew_moseley@mentor.com> -Date: Sat, 5 Jul 2014 18:56:10 -0400 -Subject: [PATCH 1/4] init-install.sh: Don't set "quiet" kernel option in - installed grub +From 2fe5dc144c38ca4e8621d81e990453565bb1b01e Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Mon, 19 Mar 2018 16:49:51 +0500 +Subject: [PATCH] init-install.sh: Don't set "quiet" kernel option Signed-off-by: Drew Moseley <drew_moseley@mentor.com> ---- - meta/recipes-core/initrdscripts/files/init-install.sh | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) +Signed-off-by: Awais Belal <awais_belal@mentor.com> Upstream-Status: Inappropriate [configuration] +--- + init-install.sh | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/meta/recipes-core/initrdscripts/files/init-install.sh b/meta/recipes-core/initrdscripts/files/init-install.sh -index 7fccdde..b36e5c0 100644 +diff --git a/init-install.sh b/init-install.sh +index 713a830..36fcdba 100644 --- init-install.sh +++ init-install.sh -@@ -229,7 +229,7 @@ if [ -f /etc/grub.d/00_header -a $grub_version -ne 0 ] ; then +@@ -293,7 +293,7 @@ if [ -f /etc/grub.d/00_header -a $grub_version -ne 0 ] ; then cat >$GRUBCFG <<_EOF menuentry "Linux" { search --no-floppy --fs-uuid $boot_uuid --set root -- linux /vmlinuz root=PARTUUID=$root_part_uuid $rootwait rw $5 $3 $4 quiet -+ linux /vmlinuz root=PARTUUID=$root_part_uuid $rootwait rw $5 $3 $4 +- linux /$kernel root=PARTUUID=$root_part_uuid $rootwait rw $5 $3 $4 quiet ++ linux /$kernel root=PARTUUID=$root_part_uuid $rootwait rw $5 $3 $4 } _EOF chmod 0444 $GRUBCFG -@@ -243,7 +243,7 @@ if [ $grub_version -eq 0 ] ; then +@@ -307,7 +307,7 @@ if [ $grub_version -eq 0 ] ; then echo "timeout 30" >> /boot/grub/menu.lst echo "title Live Boot/Install-Image" >> /boot/grub/menu.lst echo "root (hd0,0)" >> /boot/grub/menu.lst -- echo "kernel /vmlinuz root=$rootfs rw $3 $4 quiet" >> /boot/grub/menu.lst -+ echo "kernel /vmlinuz root=$rootfs rw $3 $4" >> /boot/grub/menu.lst +- echo "kernel /$kernel root=$rootfs rw $3 $4 quiet" >> /boot/grub/menu.lst ++ echo "kernel /$kernel root=$rootfs rw $3 $4" >> /boot/grub/menu.lst fi - cp /run/media/$1/vmlinuz /boot/ + # Copy kernel artifacts. To add more artifacts just add to types -- -1.9.1 +2.11.1 diff --git a/common/recipes-core/initrdscripts/files/0003-init-install-efi.sh-Don-t-set-quiet-kernel-option-in.patch b/common/recipes-core/initrdscripts/files/0003-init-install-efi.sh-Don-t-set-quiet-kernel-option-in.patch index dd0d6808..76771c09 100644 --- a/common/recipes-core/initrdscripts/files/0003-init-install-efi.sh-Don-t-set-quiet-kernel-option-in.patch +++ b/common/recipes-core/initrdscripts/files/0003-init-install-efi.sh-Don-t-set-quiet-kernel-option-in.patch @@ -1,38 +1,38 @@ -From af95e0e208a6a407c3cfb0e7f4d3a6e7882b666a Mon Sep 17 00:00:00 2001 -From: Drew Moseley <drew_moseley@mentor.com> -Date: Sat, 5 Jul 2014 18:56:31 -0400 -Subject: [PATCH 3/4] init-install-efi.sh: Don't set "quiet" kernel option in - installed grub +From 30186b183e0022abb97485f5804be0e1e02ccb1f Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Mon, 19 Mar 2018 16:56:53 +0500 +Subject: [PATCH] init-install-efi.sh: Don't set "quiet" kernel option Signed-off-by: Drew Moseley <drew_moseley@mentor.com> ---- - meta/recipes-core/initrdscripts/files/init-install-efi.sh | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) +Signed-off-by: Awais Belal <awais_belal@mentor.com> Upstream-Status: Inappropriate [configuration] +--- + init-install-efi.sh | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/meta/recipes-core/initrdscripts/files/init-install-efi.sh b/meta/recipes-core/initrdscripts/files/init-install-efi.sh -index 14939ac..e79e445 100644 +diff --git a/init-install-efi.sh b/init-install-efi.sh +index f946d97..c8af835 100644 --- init-install-efi.sh +++ init-install-efi.sh -@@ -198,7 +198,7 @@ if [ -f /run/media/$1/EFI/BOOT/grub.cfg ]; then - # Delete any root= strings - sed -i "s/ root=[^ ]*/ /" $GRUBCFG - # Add the root= and other standard boot options -- sed -i "s@linux /vmlinuz *@linux /vmlinuz root=PARTUUID=$root_part_uuid rw $rootwait quiet @" $GRUBCFG -+ sed -i "s@linux /vmlinuz *@linux /vmlinuz root=PARTUUID=$root_part_uuid rw $rootwait @" $GRUBCFG +@@ -246,7 +246,7 @@ if [ -f /run/media/$1/EFI/BOOT/grub.cfg ]; then + sed -i "s/ LABEL=[^ ]*/ /" $GRUBCFG + # Replace root= and add additional standard boot options + # We use root as a sentinel value, as vmlinuz is no longer guaranteed +- sed -i "s/ root=[^ ]*/ root=PARTUUID=$root_part_uuid rw $rootwait quiet /g" $GRUBCFG ++ sed -i "s/ root=[^ ]*/ root=PARTUUID=$root_part_uuid rw $rootwait /g" $GRUBCFG fi if [ -d /run/media/$1/loader ]; then -@@ -214,7 +214,7 @@ if [ -d /run/media/$1/loader ]; then +@@ -263,7 +263,7 @@ if [ -d /run/media/$1/loader ]; then # delete any root= strings - sed -i "s/ root=[^ ]*/ /" $GUMMIBOOT_CFGS + sed -i "s/ root=[^ ]*/ /" $SYSTEMDBOOT_CFGS # add the root= and other standard boot options -- sed -i "s@options *@options root=PARTUUID=$rootuuid rw $rootwait quiet @" $GUMMIBOOT_CFGS -+ sed -i "s@options *@options root=PARTUUID=$rootuuid rw $rootwait @" $GUMMIBOOT_CFGS +- sed -i "s@options *@options root=PARTUUID=$rootuuid rw $rootwait quiet @" $SYSTEMDBOOT_CFGS ++ sed -i "s@options *@options root=PARTUUID=$rootuuid rw $rootwait @" $SYSTEMDBOOT_CFGS fi umount /tgt_root -- -1.9.1 +2.11.1 diff --git a/common/recipes-core/llvm/files/0001-CrossCompile.cmake-adjust-build-for-OE.patch b/common/recipes-core/llvm/files/0001-CrossCompile.cmake-adjust-build-for-OE.patch deleted file mode 100644 index bf03ec2f..00000000 --- a/common/recipes-core/llvm/files/0001-CrossCompile.cmake-adjust-build-for-OE.patch +++ /dev/null @@ -1,44 +0,0 @@ -From eb27ad28d5171770d27415ace95f4c91f15828bf Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Wed, 21 Dec 2016 14:32:50 +0500 -Subject: [PATCH] CrossCompile.cmake: adjust build for OE - -CMake picks up its values from these environment variables -in case of native builds and in OE we set these to target -tools which will be incorrect in this case. -We specifically need to strip the BUILD_CC variable -before setting CC through it because OE tends to -add a space which isn't liked too much by cmake. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - cmake/modules/CrossCompile.cmake | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/cmake/modules/CrossCompile.cmake b/cmake/modules/CrossCompile.cmake -index 9c598a6..cf76fd6 100644 ---- a/cmake/modules/CrossCompile.cmake -+++ b/cmake/modules/CrossCompile.cmake -@@ -4,6 +4,19 @@ function(llvm_create_cross_target_internal target_name toolchain buildtype) - set(LLVM_${target_name}_BUILD "${CMAKE_BINARY_DIR}/${target_name}") - set(LLVM_${target_name}_BUILD ${LLVM_${target_name}_BUILD} PARENT_SCOPE) - message(STATUS "Setting native build dir to " ${LLVM_${target_name}_BUILD}) -+ string(STRIP $ENV{BUILD_CC} build_cc) -+ set(ENV{AR} $ENV{BUILD_AR}) -+ set(ENV{ASM} ${build_cc}) -+ set(ENV{ASMFLAGS} $ENV{BUILD_CFLAGS}) -+ set(ENV{CC} ${build_cc}) -+ set(ENV{CFLAGS} $ENV{BUILD_CFLAGS}) -+ set(ENV{CXX} $ENV{BUILD_CXX}) -+ set(ENV{CXXFLAGS} $ENV{BUILD_CXXFLAGS}) -+ set(ENV{CPP} $ENV{BUILD_CPP}) -+ set(ENV{CPPFLAGS} $ENV{BUILD_CPPFLAGS}) -+ set(ENV{NM} $ENV{BUILD_NM}) -+ set(ENV{RANLIB} $ENV{BUILD_RANLIB}) -+ set(ENV{LDFLAGS} $ENV{BUILD_LDFLAGS}) - endif(NOT DEFINED LLVM_${target_name}_BUILD) - - if (EXISTS ${LLVM_MAIN_SRC_DIR}/cmake/platforms/${toolchain}.cmake) --- -1.9.1 - diff --git a/common/recipes-core/llvm/files/0001-llvm-config-allow-overriding-libdir-through-cmdline.patch b/common/recipes-core/llvm/files/0001-llvm-config-allow-overriding-libdir-through-cmdline.patch new file mode 100644 index 00000000..26bf42e5 --- /dev/null +++ b/common/recipes-core/llvm/files/0001-llvm-config-allow-overriding-libdir-through-cmdline.patch @@ -0,0 +1,101 @@ +From 87b01c9e5cecd30f9cde1f717e1ae7094e1f62c1 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Wed, 13 Dec 2017 14:15:24 +0500 +Subject: [PATCH] llvm-config: allow overriding libdir through cmdline + +This is handy in cases such as the OE environment +where llvm-config is used through the llvm-native +package so the libdir it reports can be different +what is required for the target sysroot and so if +the baselib is different for target and host the +llvm-config --libs command will fail complaining +about not finding required libraries. This scenario +can be reproduced through an LLVM enabled mesa build +where host and target have different baselib. So +after the patch the mesa build should pass the whole +target libdir to the llvm-config command to use. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + tools/llvm-config/llvm-config.cpp | 32 ++++++++++++++++++++++++++++---- + 1 file changed, 28 insertions(+), 4 deletions(-) + +diff --git a/tools/llvm-config/llvm-config.cpp b/tools/llvm-config/llvm-config.cpp +index 08b096afb05..8233d16dda0 100644 +--- a/tools/llvm-config/llvm-config.cpp ++++ b/tools/llvm-config/llvm-config.cpp +@@ -301,6 +301,18 @@ int main(int argc, char **argv) { + DevelopmentTreeLayout = CMakeStyle; // Initialized to avoid warnings. + } + ++ // Check if we were given a special libdir to use ++ // if so disregard all other libdir settings ++ std::string TargetLibDir; ++ for (int i = 1; i != argc; ++i) { ++ if (strcmp(argv[i],"--tgtlibdir") == 0) { ++ if (argc > i+1) { ++ TargetLibDir.assign(argv[i+1]); ++ break; ++ } ++ } ++ } ++ + // Compute various directory locations based on the derived location + // information. + std::string ActivePrefix, ActiveBinDir, ActiveIncludeDir, ActiveLibDir, +@@ -315,13 +327,19 @@ int main(int argc, char **argv) { + switch (DevelopmentTreeLayout) { + case CMakeStyle: + ActiveBinDir = ActiveObjRoot + "/bin"; +- ActiveLibDir = ActiveObjRoot + "/lib" + LLVM_LIBDIR_SUFFIX; ++ if (!TargetLibDir.empty()) ++ ActiveLibDir = TargetLibDir; ++ else ++ ActiveLibDir = ActiveObjRoot + "/lib" + LLVM_LIBDIR_SUFFIX; + ActiveCMakeDir = ActiveLibDir + "/cmake/llvm"; + break; + case CMakeBuildModeStyle: + ActivePrefix = ActiveObjRoot; + ActiveBinDir = ActiveObjRoot + "/bin/" + build_mode; +- ActiveLibDir = ++ if (!TargetLibDir.empty()) ++ ActiveLibDir = TargetLibDir; ++ else ++ ActiveLibDir = + ActiveObjRoot + "/lib" + LLVM_LIBDIR_SUFFIX + "/" + build_mode; + ActiveCMakeDir = ActiveLibDir + "/cmake/llvm"; + break; +@@ -336,7 +354,10 @@ int main(int argc, char **argv) { + SmallString<256> path(StringRef(LLVM_TOOLS_INSTALL_DIR)); + sys::fs::make_absolute(ActivePrefix, path); + ActiveBinDir = path.str(); +- ActiveLibDir = ActivePrefix + "/lib" + LLVM_LIBDIR_SUFFIX; ++ if (!TargetLibDir.empty()) ++ ActiveLibDir = TargetLibDir; ++ else ++ ActiveLibDir = ActivePrefix + "/lib" + LLVM_LIBDIR_SUFFIX; + ActiveCMakeDir = ActiveLibDir + "/cmake/llvm"; + ActiveIncludeOption = "-I" + ActiveIncludeDir; + } +@@ -468,7 +489,7 @@ int main(int argc, char **argv) { + }; + + raw_ostream &OS = outs(); +- for (int i = 1; i != argc; ++i) { ++ for (int i = 1; i < argc; ++i) { + StringRef Arg = argv[i]; + + if (Arg.startswith("-")) { +@@ -567,6 +588,9 @@ int main(int argc, char **argv) { + LinkMode = LinkModeShared; + } else if (Arg == "--link-static") { + LinkMode = LinkModeStatic; ++ } else if (Arg == "--tgtlibdir") { ++ ++i; ++ continue; + } else { + usage(); + } +-- +2.11.1 + diff --git a/common/recipes-core/llvm/files/0002-CrossCompile.cmake-use-target-BuildVariables-include.patch b/common/recipes-core/llvm/files/0002-CrossCompile.cmake-use-target-BuildVariables-include.patch deleted file mode 100644 index 5ed00757..00000000 --- a/common/recipes-core/llvm/files/0002-CrossCompile.cmake-use-target-BuildVariables-include.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 489b229104c76651ff36fc5639384cf9dc6b8d7d Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Fri, 23 Dec 2016 03:19:18 +0500 -Subject: [PATCH] CrossCompile.cmake: use target BuildVariables include for - host - -This is primarily OE specific where we'd like to report -the target build variables when checked through host -llvm-config because that is used for configuring -projects depending on LLVM. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - cmake/modules/CrossCompile.cmake | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/cmake/modules/CrossCompile.cmake b/cmake/modules/CrossCompile.cmake -index 9c598a6..173aefd 100644 ---- a/cmake/modules/CrossCompile.cmake -+++ b/cmake/modules/CrossCompile.cmake -@@ -22,7 +22,8 @@ function(llvm_create_cross_target_internal target_name toolchain buildtype) - -DLLVM_TARGET_IS_CROSSCOMPILE_HOST=TRUE - WORKING_DIRECTORY ${LLVM_${target_name}_BUILD} - DEPENDS ${LLVM_${target_name}_BUILD} -- COMMENT "Configuring ${target_name} LLVM...") -+ COMMENT "Configuring ${target_name} LLVM..." -+ COMMAND "${CMAKE_COMMAND}" "-E" "copy" "${CMAKE_SOURCE_DIR}/../build/tools/llvm-config/BuildVariables.inc" "${CMAKE_SOURCE_DIR}/../build/NATIVE/tools/llvm-config/BuildVariables.inc") - - add_custom_target(CONFIGURE_LLVM_${target_name} - DEPENDS ${LLVM_${target_name}_BUILD}/CMakeCache.txt) --- -1.9.1 - diff --git a/common/recipes-core/llvm/files/0003-Cleanup-LLVM_OPTIMIZED_TABLEGEN.patch b/common/recipes-core/llvm/files/0003-Cleanup-LLVM_OPTIMIZED_TABLEGEN.patch deleted file mode 100644 index 9ba332d1..00000000 --- a/common/recipes-core/llvm/files/0003-Cleanup-LLVM_OPTIMIZED_TABLEGEN.patch +++ /dev/null @@ -1,97 +0,0 @@ -From dbbdf44025768383566a947cb5ea811929db0e6c Mon Sep 17 00:00:00 2001 -From: Chris Bieneman <beanz@apple.com> -Date: Tue, 6 Sep 2016 20:27:07 +0000 -Subject: [PATCH] [CMake] Cleanup LLVM_OPTIMIZED_TABLEGEN - -This cleanup removes the need for the native support library to have its own target. That target was only needed because makefile builds were tripping over each other if two tablegen targets were building at the same time. This causes problems because the parallel make invocations through CMake can't communicate with each other. This is fixed by invoking make directly instead of through CMake which is how we handle this in External Project invocations. - -The other part of the cleanup is to mark the custom commands as USES_TERMINAL. This is a bit of a hack, but we need to ensure that Ninja generators don't invoke multiple tablegen targets in the same build dir in parallel, because that too would be bad. - -Marking as USES_TERMINAL does have some downside for Ninja because it results in decreased parallelism, but correct builds are worth the minor loss and LLVM_OPTIMZIED_TABLEGEN is such a huge win, it is worth it. - -git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280748 91177308-0d34-0410-b5e6-96231b3b80d8 ---- - cmake/modules/LLVMExternalProjectUtils.cmake | 8 ++++++-- - cmake/modules/TableGen.cmake | 27 +++++++++++++++------------ - 2 files changed, 21 insertions(+), 14 deletions(-) - -diff --git a/cmake/modules/LLVMExternalProjectUtils.cmake b/cmake/modules/LLVMExternalProjectUtils.cmake -index efe47e7..f7020fb 100644 ---- a/cmake/modules/LLVMExternalProjectUtils.cmake -+++ b/cmake/modules/LLVMExternalProjectUtils.cmake -@@ -3,12 +3,16 @@ include(ExternalProject) - # llvm_ExternalProject_BuildCmd(out_var target) - # Utility function for constructing command lines for external project targets - function(llvm_ExternalProject_BuildCmd out_var target bin_dir) -+ cmake_parse_arguments(ARG "" "CONFIGURATION" "" ${ARGN}) -+ if(NOT ARG_CONFIGURATION) -+ set(ARG_CONFIGURATION "$<CONFIGURATION>") -+ endif() - if (CMAKE_GENERATOR MATCHES "Make") - # Use special command for Makefiles to support parallelism. -- set(${out_var} "$(MAKE)" "-C" "${BINARY_DIR}" "${target}" PARENT_SCOPE) -+ set(${out_var} "$(MAKE)" "-C" "${bin_dir}" "${target}" PARENT_SCOPE) - else() - set(${out_var} ${CMAKE_COMMAND} --build ${bin_dir} --target ${target} -- --config $<CONFIGURATION> PARENT_SCOPE) -+ --config ${ARG_CONFIGURATION} PARENT_SCOPE) - endif() - endfunction() - -diff --git a/cmake/modules/TableGen.cmake b/cmake/modules/TableGen.cmake -index b84fa93..c9cfb37 100644 ---- a/cmake/modules/TableGen.cmake -+++ b/cmake/modules/TableGen.cmake -@@ -2,6 +2,8 @@ - # Extra parameters for `tblgen' may come after `ofn' parameter. - # Adds the name of the generated file to TABLEGEN_OUTPUT. - -+include(LLVMExternalProjectUtils) -+ - function(tablegen project ofn) - # Validate calling context. - foreach(v -@@ -71,18 +73,15 @@ function(add_public_tablegen_target target) - endfunction() - - if(LLVM_USE_HOST_TOOLS) -- add_custom_command(OUTPUT LIB_LLVMSUPPORT -- COMMAND ${CMAKE_COMMAND} --build . --target LLVMSupport --config Release -- DEPENDS CONFIGURE_LLVM_NATIVE -- WORKING_DIRECTORY ${LLVM_NATIVE_BUILD} -- COMMENT "Building libLLVMSupport for native TableGen...") -- add_custom_target(NATIVE_LIB_LLVMSUPPORT DEPENDS LIB_LLVMSUPPORT) -- -+ llvm_ExternalProject_BuildCmd(tblgen_build_cmd LLVMSupport -+ ${LLVM_NATIVE_BUILD} -+ CONFIGURATION Release) - add_custom_command(OUTPUT LIB_LLVMTABLEGEN -- COMMAND ${CMAKE_COMMAND} --build . --target LLVMTableGen --config Release -+ COMMAND ${tblgen_build_cmd} - DEPENDS CONFIGURE_LLVM_NATIVE - WORKING_DIRECTORY ${LLVM_NATIVE_BUILD} -- COMMENT "Building libLLVMTableGen for native TableGen...") -+ COMMENT "Building libLLVMTableGen for native TableGen..." -+ USES_TERMINAL) - add_custom_target(NATIVE_LIB_LLVMTABLEGEN DEPENDS LIB_LLVMTABLEGEN) - endif(LLVM_USE_HOST_TOOLS) - -@@ -123,11 +122,15 @@ macro(add_tablegen target project) - endif() - set(${project}_TABLEGEN_EXE ${${project}_TABLEGEN_EXE} PARENT_SCOPE) - -+ llvm_ExternalProject_BuildCmd(tblgen_build_cmd ${target} -+ ${LLVM_NATIVE_BUILD} -+ CONFIGURATION Release) - add_custom_command(OUTPUT ${${project}_TABLEGEN_EXE} -- COMMAND ${CMAKE_COMMAND} --build . --target ${target} --config Release -- DEPENDS ${target} NATIVE_LIB_LLVMSUPPORT NATIVE_LIB_LLVMTABLEGEN -+ COMMAND ${tblgen_build_cmd} -+ DEPENDS ${target} NATIVE_LIB_LLVMTABLEGEN - WORKING_DIRECTORY ${LLVM_NATIVE_BUILD} -- COMMENT "Building native TableGen...") -+ COMMENT "Building native TableGen..." -+ USES_TERMINAL) - add_custom_target(${project}-tablegen-host DEPENDS ${${project}_TABLEGEN_EXE}) - set(${project}_TABLEGEN_TARGET ${project}-tablegen-host PARENT_SCOPE) - endif() diff --git a/common/recipes-core/llvm/files/0004-Dont-build-llvm-config-and-tblgen-concurrently.patch b/common/recipes-core/llvm/files/0004-Dont-build-llvm-config-and-tblgen-concurrently.patch deleted file mode 100644 index 683d814c..00000000 --- a/common/recipes-core/llvm/files/0004-Dont-build-llvm-config-and-tblgen-concurrently.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 8bddda3652b36619cc8cd916c33d38c9cd41f024 Mon Sep 17 00:00:00 2001 -From: Justin Bogner <mail@justinbogner.com> -Date: Wed, 21 Dec 2016 21:19:00 +0000 -Subject: [PATCH] cmake: Don't build llvm-config and tblgen concurrently in - cross builds - -This sets USES_TERMINAL for the native llvm-config build, so that it -doesn't run at the same time as builds of other native tools (namely, -tablegen). Without this, if you're very unlucky with the timing it's -possible to be relinking libSupport as one of the tools is linking, -causing a spurious failure. - -The tablegen build adopted USES_TERMINAL for this same reason in -r280748. - -git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290271 91177308-0d34-0410-b5e6-96231b3b80d8 ---- - tools/llvm-config/CMakeLists.txt | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/tools/llvm-config/CMakeLists.txt b/tools/llvm-config/CMakeLists.txt -index 744fa4e..1f5db59b 100644 ---- a/tools/llvm-config/CMakeLists.txt -+++ b/tools/llvm-config/CMakeLists.txt -@@ -69,7 +69,8 @@ if(CMAKE_CROSSCOMPILING) - COMMAND ${CMAKE_COMMAND} --build . --target llvm-config --config $<CONFIGURATION> - DEPENDS ${LLVM_NATIVE_BUILD}/CMakeCache.txt - WORKING_DIRECTORY ${LLVM_NATIVE_BUILD} -- COMMENT "Building native llvm-config...") -+ COMMENT "Building native llvm-config..." -+ USES_TERMINAL) - add_custom_target(${project}NativeLLVMConfig DEPENDS ${${project}_LLVM_CONFIG_EXE}) - add_dependencies(${project}NativeLLVMConfig CONFIGURE_LLVM_NATIVE) - diff --git a/common/recipes-core/llvm/llvm3.9_3.9.bb b/common/recipes-core/llvm/llvm3.9_3.9.bb deleted file mode 100644 index 2acfef80..00000000 --- a/common/recipes-core/llvm/llvm3.9_3.9.bb +++ /dev/null @@ -1,153 +0,0 @@ -DESCRIPTION = "The Low Level Virtual Machine" -HOMEPAGE = "http://llvm.org" - -# 3-clause BSD-like -# University of Illinois/NCSA Open Source License -LICENSE = "NCSA" -LIC_FILES_CHKSUM = "file://LICENSE.TXT;md5=b99eb43c934ceebecab85c6b9b1a08be" - -DEPENDS = "libffi libxml2-native llvm-common zlib ninja-native" -RDEPENDS_${PN} += "ncurses-terminfo" - -inherit perlnative pythonnative cmake - -PROVIDES += "llvm" - -LLVM_RELEASE = "${PV}" -LLVM_DIR = "llvm${LLVM_RELEASE}" - -SRCREV = "a093ef43dd592b729da46db4ff3057fef9a46023" -PV = "3.9" -PATCH_VERSION = "1" -SRC_URI = "git://llvm.org/git/llvm.git;branch=release_39;protocol=http \ - file://0001-CrossCompile.cmake-adjust-build-for-OE.patch \ - file://0002-CrossCompile.cmake-use-target-BuildVariables-include.patch \ - file://0003-Cleanup-LLVM_OPTIMIZED_TABLEGEN.patch \ - file://0004-Dont-build-llvm-config-and-tblgen-concurrently.patch" -S = "${WORKDIR}/git" - -LLVM_INSTALL_DIR = "${WORKDIR}/llvm-install" - -EXTRA_OECMAKE += "-DLLVM_ENABLE_ASSERTIONS=OFF \ - -DLLVM_ENABLE_EXPENSIVE_CHECKS=OFF \ - -DLLVM_BINDINGS_LIST="" \ - -DLLVM_LINK_LLVM_DYLIB=ON \ - -DLLVM_ENABLE_FFI=ON \ - -DLLVM_OPTIMIZED_TABLEGEN=ON \ - -DLLVM_TARGETS_TO_BUILD="AMDGPU;X86"" - -do_configure() { - # Fix paths in llvm-config - sed -i "s|sys::path::parent_path(CurrentPath))\.str()|sys::path::parent_path(sys::path::parent_path(CurrentPath))).str()|g" ${S}/tools/llvm-config/llvm-config.cpp - sed -ri "s#/(bin|include|lib)(/?\")#/\1/${LLVM_DIR}\2#g" ${S}/tools/llvm-config/llvm-config.cpp - sed -ri "s#lib/${LLVM_DIR}#${baselib}/${LLVM_DIR}#g" ${S}/tools/llvm-config/llvm-config.cpp - cd ${B} - cmake \ - -G Ninja \ - ${S} \ - -DCMAKE_INSTALL_PREFIX:PATH=/usr \ - -DCMAKE_INSTALL_BINDIR:PATH=bin \ - -DCMAKE_INSTALL_SBINDIR:PATH=sbin \ - -DCMAKE_INSTALL_LIBEXECDIR:PATH=libexec \ - -DCMAKE_INSTALL_SYSCONFDIR:PATH=/etc \ - -DCMAKE_INSTALL_SHAREDSTATEDIR:PATH=../com \ - -DCMAKE_INSTALL_LOCALSTATEDIR:PATH=/var \ - -DCMAKE_INSTALL_LIBDIR:PATH=lib64 \ - -DCMAKE_INSTALL_INCLUDEDIR:PATH=include \ - -DCMAKE_INSTALL_DATAROOTDIR:PATH=share \ - -DCMAKE_INSTALL_SO_NO_EXE=0 \ - -DCMAKE_TOOLCHAIN_FILE=${WORKDIR}/toolchain.cmake \ - -DCMAKE_VERBOSE_MAKEFILE=1 \ - -DCMAKE_NO_SYSTEM_FROM_IMPORTED=1 \ - ${EXTRA_OECMAKE} -} - -do_compile() { - cd ${B} - NINJA_STATUS="[%p] " ninja -v -} - -do_install() { - DESTDIR=${LLVM_INSTALL_DIR} ninja -v install - - install ${B}/NATIVE/bin/llvm-config ${LLVM_INSTALL_DIR}/llvm-config-host - - install -d ${D}${bindir}/${LLVM_DIR} - cp -r ${LLVM_INSTALL_DIR}${bindir}/* ${D}${bindir}/${LLVM_DIR}/ - - install -d ${D}${includedir}/${LLVM_DIR} - cp -r ${LLVM_INSTALL_DIR}${includedir}/* ${D}${includedir}/${LLVM_DIR}/ - - install -d ${D}${libdir}/${LLVM_DIR} - - # The LLVM sources have "/lib" embedded and so we cannot completely rely on the ${libdir} variable - if [ -d ${LLVM_INSTALL_DIR}${libdir}/ ]; then - cp -r ${LLVM_INSTALL_DIR}${libdir}/* ${D}${libdir}/${LLVM_DIR}/ - elif [ -d ${LLVM_INSTALL_DIR}${prefix}/lib ]; then - cp -r ${LLVM_INSTALL_DIR}${prefix}/lib/* ${D}${libdir}/${LLVM_DIR}/ - elif [ -d ${LLVM_INSTALL_DIR}${prefix}/lib64 ]; then - cp -r ${LLVM_INSTALL_DIR}${prefix}/lib64/* ${D}${libdir}/${LLVM_DIR}/ - fi - - # Remove unnecessary cmake files - rm -rf ${D}${libdir}/${LLVM_DIR}/cmake - - ln -s ${LLVM_DIR}/libLLVM-${PV}${SOLIBSDEV} ${D}${libdir}/libLLVM-${PV}${SOLIBSDEV} - - # We'll have to delete the libLLVM.so due to multiple reasons... - rm -rf ${D}${libdir}/${LLVM_DIR}/libLLVM.so -} - -SYSROOT_PREPROCESS_FUNCS += "llvm_sysroot_preprocess" - -llvm_sysroot_preprocess() { - install -d ${SYSROOT_DESTDIR}${bindir_crossscripts} - cp ${LLVM_INSTALL_DIR}/llvm-config-host ${SYSROOT_DESTDIR}${bindir_crossscripts}/llvm-config${PV} -} - -PACKAGES += "${PN}-bugpointpasses ${PN}-llvmhello" -ALLOW_EMPTY_${PN} = "1" -ALLOW_EMPTY_${PN}-staticdev = "1" -FILES_${PN} = "" -FILES_${PN}-staticdev = "" -FILES_${PN}-dbg = " \ - ${bindir}/${LLVM_DIR}/.debug \ - ${libdir}/${LLVM_DIR}/.debug/BugpointPasses.so \ - ${libdir}/${LLVM_DIR}/.debug/LLVMHello.so \ - /usr/src/debug \ -" - -FILES_${PN}-dev = " \ - ${bindir}/${LLVM_DIR} \ - ${includedir}/${LLVM_DIR} \ -" -RRECOMMENDS_${PN}-dev += "${PN}-bugpointpasses ${PN}-llvmhello" - -FILES_${PN}-bugpointpasses = "\ - ${libdir}/${LLVM_DIR}/BugpointPasses.so \ -" -FILES_${PN}-llvmhello = "\ - ${libdir}/${LLVM_DIR}/LLVMHello.so \ -" - -PACKAGES_DYNAMIC = "^libllvm${LLVM_RELEASE}-.*$" -NOAUTOPACKAGEDEBUG = "1" - -INSANE_SKIP_${MLPREFIX}libllvm${LLVM_RELEASE}-llvm-${LLVM_RELEASE}.${PATCH_VERSION} += "dev-so" -INSANE_SKIP_${MLPREFIX}libllvm${LLVM_RELEASE}-llvm-${LLVM_RELEASE} += "dev-so" -INSANE_SKIP_${MLPREFIX}libllvm${LLVM_RELEASE}-llvm += "dev-so" - -python llvm_populate_packages() { - libdir = bb.data.expand('${libdir}', d) - libllvm_libdir = bb.data.expand('${libdir}/${LLVM_DIR}', d) - split_dbg_packages = do_split_packages(d, libllvm_libdir+'/.debug', '^lib(.*)\.so$', 'libllvm${LLVM_RELEASE}-%s-dbg', 'Split debug package for %s', allow_dirs=True) - split_packages = do_split_packages(d, libdir, '^lib(.*)\.so$', 'libllvm${LLVM_RELEASE}-%s', 'Split package for %s', allow_dirs=True, allow_links=True, recursive=True) - split_staticdev_packages = do_split_packages(d, libllvm_libdir, '^lib(.*)\.a$', 'libllvm${LLVM_RELEASE}-%s-staticdev', 'Split staticdev package for %s', allow_dirs=True) - if split_packages: - pn = d.getVar('PN', True) - d.appendVar('RDEPENDS_' + pn, ' '+' '.join(split_packages)) - d.appendVar('RDEPENDS_' + pn + '-dbg', ' '+' '.join(split_dbg_packages)) - d.appendVar('RDEPENDS_' + pn + '-staticdev', ' '+' '.join(split_staticdev_packages)) -} - -PACKAGESPLITFUNCS_prepend = "llvm_populate_packages " diff --git a/common/recipes-core/llvm/llvm_git.bbappend b/common/recipes-core/llvm/llvm_git.bbappend new file mode 100644 index 00000000..373df6cb --- /dev/null +++ b/common/recipes-core/llvm/llvm_git.bbappend @@ -0,0 +1,2 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" +SRC_URI += "file://0001-llvm-config-allow-overriding-libdir-through-cmdline.patch" diff --git a/common/recipes-core/packagegroups/packagegroup-multimedia-risky.bb b/common/recipes-core/packagegroups/packagegroup-multimedia-risky.bb index 2a9ba43b..36bc2075 100644 --- a/common/recipes-core/packagegroups/packagegroup-multimedia-risky.bb +++ b/common/recipes-core/packagegroups/packagegroup-multimedia-risky.bb @@ -1,7 +1,6 @@ DESCRIPTION = "AMD risky multimedia packages" LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://${COREBASE}/LICENSE;md5=4d92cd373abda3937c2bc47fbc49d690 \ - file://${COREBASE}/meta/COPYING.MIT;md5=3da9cfbcb788c80a0384361b4de20420" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" PR = "r0" inherit packagegroup diff --git a/common/recipes-core/systemd/systemd_%.bbappend b/common/recipes-core/systemd/systemd_%.bbappend new file mode 100644 index 00000000..2198b747 --- /dev/null +++ b/common/recipes-core/systemd/systemd_%.bbappend @@ -0,0 +1,5 @@ +pkg_postinst_udev-hwdb_amd () { +} +pkg_postinst_ontarget_udev-hwdb_amd () { + udevadm hwdb --update +} diff --git a/common/recipes-devtools/qemu/files/04b33e21866412689f18b7ad6daf0a54d8f959a7.patch b/common/recipes-devtools/qemu/files/04b33e21866412689f18b7ad6daf0a54d8f959a7.patch deleted file mode 100644 index d947e8cb..00000000 --- a/common/recipes-devtools/qemu/files/04b33e21866412689f18b7ad6daf0a54d8f959a7.patch +++ /dev/null @@ -1,282 +0,0 @@ -From 04b33e21866412689f18b7ad6daf0a54d8f959a7 Mon Sep 17 00:00:00 2001 -From: Khem Raj <raj.khem@gmail.com> -Date: Wed, 28 Jun 2017 13:44:52 -0700 -Subject: [PATCH] Replace 'struct ucontext' with 'ucontext_t' type - -glibc used to have: - - typedef struct ucontext { ... } ucontext_t; - -glibc now has: - - typedef struct ucontext_t { ... } ucontext_t; - -(See https://sourceware.org/bugzilla/show_bug.cgi?id=21457 - for detail and rationale for the glibc change) - -However, QEMU used "struct ucontext" in declarations. This is a -private name and compatibility cannot be guaranteed. Switch to -only using the standardized type name. - -Signed-off-by: Khem Raj <raj.khem@gmail.com> -Message-id: 20170628204452.41230-1-raj.khem@gmail.com -Cc: Kamil Rytarowski <kamil@netbsd.org> -Cc: Riku Voipio <riku.voipio@iki.fi> -Cc: Laurent Vivier <laurent@vivier.eu> -Cc: Paolo Bonzini <pbonzini@redhat.com> -Reviewed-by: Eric Blake <eblake@redhat.com> -[PMM: Rewrote commit message, based mostly on the one from - Nathaniel McCallum] -Signed-off-by: Peter Maydell <peter.maydell@linaro.org> - -Upstream-Status: Backport -RP 2017/9/6 ---- - linux-user/host/aarch64/hostdep.h | 2 +- - linux-user/host/arm/hostdep.h | 2 +- - linux-user/host/i386/hostdep.h | 2 +- - linux-user/host/ppc64/hostdep.h | 2 +- - linux-user/host/s390x/hostdep.h | 2 +- - linux-user/host/x86_64/hostdep.h | 2 +- - linux-user/signal.c | 10 +++++----- - tests/tcg/test-i386.c | 4 ++-- - user-exec.c | 18 +++++++++--------- - 9 files changed, 22 insertions(+), 22 deletions(-) - -diff --git a/linux-user/host/aarch64/hostdep.h b/linux-user/host/aarch64/hostdep.h -index 64f75ce..a8d41a2 100644 ---- a/linux-user/host/aarch64/hostdep.h -+++ b/linux-user/host/aarch64/hostdep.h -@@ -24,7 +24,7 @@ extern char safe_syscall_end[]; - /* Adjust the signal context to rewind out of safe-syscall if we're in it */ - static inline void rewind_if_in_safe_syscall(void *puc) - { -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - __u64 *pcreg = &uc->uc_mcontext.pc; - - if (*pcreg > (uintptr_t)safe_syscall_start -diff --git a/linux-user/host/arm/hostdep.h b/linux-user/host/arm/hostdep.h -index 5c1ae60..9276fe6 100644 ---- a/linux-user/host/arm/hostdep.h -+++ b/linux-user/host/arm/hostdep.h -@@ -24,7 +24,7 @@ extern char safe_syscall_end[]; - /* Adjust the signal context to rewind out of safe-syscall if we're in it */ - static inline void rewind_if_in_safe_syscall(void *puc) - { -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - unsigned long *pcreg = &uc->uc_mcontext.arm_pc; - - if (*pcreg > (uintptr_t)safe_syscall_start -diff --git a/linux-user/host/i386/hostdep.h b/linux-user/host/i386/hostdep.h -index d834bd8..073be74 100644 ---- a/linux-user/host/i386/hostdep.h -+++ b/linux-user/host/i386/hostdep.h -@@ -24,7 +24,7 @@ extern char safe_syscall_end[]; - /* Adjust the signal context to rewind out of safe-syscall if we're in it */ - static inline void rewind_if_in_safe_syscall(void *puc) - { -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - greg_t *pcreg = &uc->uc_mcontext.gregs[REG_EIP]; - - if (*pcreg > (uintptr_t)safe_syscall_start -diff --git a/linux-user/host/ppc64/hostdep.h b/linux-user/host/ppc64/hostdep.h -index 0b0f5f7..98979ad 100644 ---- a/linux-user/host/ppc64/hostdep.h -+++ b/linux-user/host/ppc64/hostdep.h -@@ -24,7 +24,7 @@ extern char safe_syscall_end[]; - /* Adjust the signal context to rewind out of safe-syscall if we're in it */ - static inline void rewind_if_in_safe_syscall(void *puc) - { -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - unsigned long *pcreg = &uc->uc_mcontext.gp_regs[PT_NIP]; - - if (*pcreg > (uintptr_t)safe_syscall_start -diff --git a/linux-user/host/s390x/hostdep.h b/linux-user/host/s390x/hostdep.h -index 6f9da9c..4f0171f 100644 ---- a/linux-user/host/s390x/hostdep.h -+++ b/linux-user/host/s390x/hostdep.h -@@ -24,7 +24,7 @@ extern char safe_syscall_end[]; - /* Adjust the signal context to rewind out of safe-syscall if we're in it */ - static inline void rewind_if_in_safe_syscall(void *puc) - { -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - unsigned long *pcreg = &uc->uc_mcontext.psw.addr; - - if (*pcreg > (uintptr_t)safe_syscall_start -diff --git a/linux-user/host/x86_64/hostdep.h b/linux-user/host/x86_64/hostdep.h -index 3b42596..a4fefb5 100644 ---- a/linux-user/host/x86_64/hostdep.h -+++ b/linux-user/host/x86_64/hostdep.h -@@ -24,7 +24,7 @@ extern char safe_syscall_end[]; - /* Adjust the signal context to rewind out of safe-syscall if we're in it */ - static inline void rewind_if_in_safe_syscall(void *puc) - { -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - greg_t *pcreg = &uc->uc_mcontext.gregs[REG_RIP]; - - if (*pcreg > (uintptr_t)safe_syscall_start -diff --git a/linux-user/signal.c b/linux-user/signal.c -index d68bd26..cc0c3fc 100644 ---- a/linux-user/signal.c -+++ b/linux-user/signal.c -@@ -3346,7 +3346,7 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka, - * - * a0 = signal number - * a1 = pointer to siginfo_t -- * a2 = pointer to struct ucontext -+ * a2 = pointer to ucontext_t - * - * $25 and PC point to the signal handler, $29 points to the - * struct sigframe. -@@ -3764,7 +3764,7 @@ struct target_signal_frame { - - struct rt_signal_frame { - siginfo_t info; -- struct ucontext uc; -+ ucontext_t uc; - uint32_t tramp[2]; - }; - -@@ -3980,7 +3980,7 @@ struct rt_signal_frame { - siginfo_t *pinfo; - void *puc; - siginfo_t info; -- struct ucontext uc; -+ ucontext_t uc; - uint16_t retcode[4]; /* Trampoline code. */ - }; - -@@ -4515,7 +4515,7 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka, - tswap_siginfo(&frame->info, info); - } - -- /*err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));*/ -+ /*err |= __clear_user(&frame->uc, offsetof(ucontext_t, uc_mcontext));*/ - __put_user(0, &frame->uc.tuc_flags); - __put_user(0, &frame->uc.tuc_link); - __put_user(target_sigaltstack_used.ss_sp, -@@ -5007,7 +5007,7 @@ enum { - - struct target_ucontext { - target_ulong tuc_flags; -- target_ulong tuc_link; /* struct ucontext __user * */ -+ target_ulong tuc_link; /* ucontext_t __user * */ - struct target_sigaltstack tuc_stack; - #if !defined(TARGET_PPC64) - int32_t tuc_pad[7]; -diff --git a/tests/tcg/test-i386.c b/tests/tcg/test-i386.c -index 0f7b943..9599204 100644 ---- a/tests/tcg/test-i386.c -+++ b/tests/tcg/test-i386.c -@@ -1720,7 +1720,7 @@ int tab[2]; - - void sig_handler(int sig, siginfo_t *info, void *puc) - { -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - - printf("si_signo=%d si_errno=%d si_code=%d", - info->si_signo, info->si_errno, info->si_code); -@@ -1912,7 +1912,7 @@ void test_exceptions(void) - /* specific precise single step test */ - void sig_trap_handler(int sig, siginfo_t *info, void *puc) - { -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - printf("EIP=" FMTLX "\n", (long)uc->uc_mcontext.gregs[REG_EIP]); - } - -diff --git a/user-exec.c b/user-exec.c -index a8f95fa..2a975ea 100644 ---- a/user-exec.c -+++ b/user-exec.c -@@ -167,7 +167,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, - #elif defined(__OpenBSD__) - struct sigcontext *uc = puc; - #else -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - #endif - unsigned long pc; - int trapno; -@@ -222,7 +222,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, - #elif defined(__OpenBSD__) - struct sigcontext *uc = puc; - #else -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - #endif - - pc = PC_sig(uc); -@@ -289,7 +289,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, - #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) - ucontext_t *uc = puc; - #else -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - #endif - unsigned long pc; - int is_write; -@@ -316,7 +316,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) - { - siginfo_t *info = pinfo; -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - uint32_t *pc = uc->uc_mcontext.sc_pc; - uint32_t insn = *pc; - int is_write = 0; -@@ -414,7 +414,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, - #if defined(__NetBSD__) - ucontext_t *uc = puc; - #else -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - #endif - unsigned long pc; - int is_write; -@@ -441,7 +441,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, - int cpu_signal_handler(int host_signum, void *pinfo, void *puc) - { - siginfo_t *info = pinfo; -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - uint32_t insn = *(uint32_t *)pc; - bool is_write; -@@ -474,7 +474,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, void *puc) - int cpu_signal_handler(int host_signum, void *pinfo, void *puc) - { - siginfo_t *info = pinfo; -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - unsigned long ip; - int is_write = 0; - -@@ -505,7 +505,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) - { - siginfo_t *info = pinfo; -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - unsigned long pc; - uint16_t *pinsn; - int is_write = 0; -@@ -558,7 +558,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) - { - siginfo_t *info = pinfo; -- struct ucontext *uc = puc; -+ ucontext_t *uc = puc; - greg_t pc = uc->uc_mcontext.pc; - int is_write; - --- -1.8.3.1 - diff --git a/common/recipes-devtools/qemu/qemu_2.7.0.bbappend b/common/recipes-devtools/qemu/qemu_2.7.0.bbappend deleted file mode 100644 index 0ae298c6..00000000 --- a/common/recipes-devtools/qemu/qemu_2.7.0.bbappend +++ /dev/null @@ -1,2 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" -SRC_URI += "${@bb.utils.contains_any("DISTRO", "mel mel-lite", "file://04b33e21866412689f18b7ad6daf0a54d8f959a7.patch", "", d)}" diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0001-intel-kbl-Add-Kabylake-PCI-ids.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0001-intel-kbl-Add-Kabylake-PCI-ids.patch deleted file mode 100644 index 9c9e815e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0001-intel-kbl-Add-Kabylake-PCI-ids.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 242f77ce03f4db371d8de3de1bef8622c0fe7488 Mon Sep 17 00:00:00 2001 -From: Rodrigo Vivi <rodrigo.vivi@intel.com> -Date: Fri, 18 Sep 2015 11:26:39 -0700 -Subject: [PATCH 001/117] intel/kbl: Add Kabylake PCI ids - -Also, following kernel definition Kabylake is skylake. - -Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> -Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> ---- - intel/intel_chipset.h | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 56 insertions(+), 1 deletion(-) - -diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h -index 26fbee4..35148e5 100644 ---- a/intel/intel_chipset.h -+++ b/intel/intel_chipset.h -@@ -187,6 +187,29 @@ - #define PCI_CHIP_SKYLAKE_H_GT4 0x193B - #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D - -+#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 -+#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 -+#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 -+#define PCI_CHIP_KABYLAKE_ULT_GT3 0x5926 -+#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 -+#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 -+#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E -+#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E -+#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 -+#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 -+#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 -+#define PCI_CHIP_KABYLAKE_DT_GT4 0x5932 -+#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B -+#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B -+#define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B -+#define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B -+#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A -+#define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A -+#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A -+#define PCI_CHIP_KABYLAKE_SRV_GT4 0x593A -+#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D -+#define PCI_CHIP_KABYLAKE_WKS_GT4 0x593D -+ - #define PCI_CHIP_BROXTON_0 0x0A84 - #define PCI_CHIP_BROXTON_1 0x1A84 - #define PCI_CHIP_BROXTON_2 0x5A84 -@@ -375,6 +398,37 @@ - (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) - -+#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ -+ (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ -+ (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ -+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT1 || \ -+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) -+ -+#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) -+ -+#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3 || \ -+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT3 || \ -+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT3) -+ -+#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT4 || \ -+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT4 || \ -+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT4 || \ -+ (devid) == PCI_CHIP_KABYLAKE_WKS_GT4) -+ -+#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ -+ IS_KBL_GT2(devid) || \ -+ IS_KBL_GT3(devid) || \ -+ IS_KBL_GT4(devid)) -+ - #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ - IS_SKL_GT2(devid) || \ - IS_SKL_GT3(devid) || \ -@@ -385,7 +439,8 @@ - (devid) == PCI_CHIP_BROXTON_2) - - #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ -- IS_BROXTON(devid)) -+ IS_BROXTON(devid) || \ -+ IS_KABYLAKE(devid)) - - #define IS_9XX(dev) (IS_GEN3(dev) || \ - IS_GEN4(dev) || \ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0001-tests-also-install-tests-app.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0001-tests-also-install-tests-app.patch deleted file mode 100644 index 3d0e89dd..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0001-tests-also-install-tests-app.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 3ad69d49671cd8f29824840f9cc175f835e413b3 Mon Sep 17 00:00:00 2001 -From: Arindam Nath <arindam.nath@amd.com> -Date: Sun, 17 Jan 2016 16:52:40 +0530 -Subject: [PATCH 1/1] tests: also install tests app - -Upstream-Status: Inappropriate [configuration] - -Signed-off-by: Yu Ke <ke.yu@intel.com> -Signed-off-by: Arindam Nath <arindam.nath@amd.com> ---- - tests/Makefile.am | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/tests/Makefile.am b/tests/Makefile.am -index 58feb12..3e46e16 100644 ---- a/tests/Makefile.am -+++ b/tests/Makefile.am -@@ -29,13 +29,14 @@ AM_CFLAGS = \ - - LDADD = $(top_builddir)/libdrm.la - --check_PROGRAMS = \ -+bin_PROGRAMS = \ - dristat \ - drmdevice \ - drmstat - - dristat_LDADD = -lm - -+check_PROGRAMS = - if HAVE_NOUVEAU - SUBDIRS += nouveau - endif --- -1.9.1 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0002-Fix-memory-leak-with-drmModeGetConnectorCurrent.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0002-Fix-memory-leak-with-drmModeGetConnectorCurrent.patch deleted file mode 100644 index ff2d910f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0002-Fix-memory-leak-with-drmModeGetConnectorCurrent.patch +++ /dev/null @@ -1,77 +0,0 @@ -From e342c0fc250f3f16b817c43e96ab9b839fcb15c2 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> -Date: Tue, 15 Dec 2015 14:18:32 +0200 -Subject: [PATCH 002/117] Fix memory leak with drmModeGetConnectorCurrent() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -drmModeGetConnectorCurrent() must provide temporary storage for the -kernel to fill in at least one mode (asking for !=0 modes is how -you prevent the heavyweight probe in the kernel). Currently we malloc -that temp storage but we fail to free it before overwriting the -pointer with the address of the actual storage we use to store the -real mode list we get from the kernel in the second ioctl call. - -Let's just keep the temporary storage on the stack and thus we avoid the -leak and also eliminate some pointless mallocs. - -Cc: Chris Wilson <chris@chris-wilson.co.uk> -Fixes: 5ed5fa10600f ("mode: Retrieve only the current information for a Connector") -Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> -Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> ---- - xf86drmMode.c | 11 +++++++---- - 1 file changed, 7 insertions(+), 4 deletions(-) - -diff --git a/xf86drmMode.c b/xf86drmMode.c -index ab6b519..7710061 100644 ---- a/xf86drmMode.c -+++ b/xf86drmMode.c -@@ -475,12 +475,13 @@ _drmModeGetConnector(int fd, uint32_t connector_id, int probe) - { - struct drm_mode_get_connector conn, counts; - drmModeConnectorPtr r = NULL; -+ struct drm_mode_modeinfo stack_mode; - - memclear(conn); - conn.connector_id = connector_id; - if (!probe) { - conn.count_modes = 1; -- conn.modes_ptr = VOID2U64(drmMalloc(sizeof(struct drm_mode_modeinfo))); -+ conn.modes_ptr = VOID2U64(&stack_mode); - } - - if (drmIoctl(fd, DRM_IOCTL_MODE_GETCONNECTOR, &conn)) -@@ -504,7 +505,7 @@ retry: - goto err_allocs; - } else { - conn.count_modes = 1; -- conn.modes_ptr = VOID2U64(drmMalloc(sizeof(struct drm_mode_modeinfo))); -+ conn.modes_ptr = VOID2U64(&stack_mode); - } - - if (conn.count_encoders) { -@@ -525,7 +526,8 @@ retry: - counts.count_encoders < conn.count_encoders) { - drmFree(U642VOID(conn.props_ptr)); - drmFree(U642VOID(conn.prop_values_ptr)); -- drmFree(U642VOID(conn.modes_ptr)); -+ if (U642VOID(conn.modes_ptr) != &stack_mode) -+ drmFree(U642VOID(conn.modes_ptr)); - drmFree(U642VOID(conn.encoders_ptr)); - - goto retry; -@@ -567,7 +569,8 @@ retry: - err_allocs: - drmFree(U642VOID(conn.prop_values_ptr)); - drmFree(U642VOID(conn.props_ptr)); -- drmFree(U642VOID(conn.modes_ptr)); -+ if (U642VOID(conn.modes_ptr) != &stack_mode) -+ drmFree(U642VOID(conn.modes_ptr)); - drmFree(U642VOID(conn.encoders_ptr)); - - return r; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0003-configure.ac-disable-annoying-warning-Wmissing-field.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0003-configure.ac-disable-annoying-warning-Wmissing-field.patch deleted file mode 100644 index 5bc53983..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0003-configure.ac-disable-annoying-warning-Wmissing-field.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 5198f2b2e658651d9cb81d67998ba7b2c39e12d7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> -Date: Tue, 12 Jan 2016 22:09:24 +0100 -Subject: [PATCH 003/117] configure.ac: disable annoying warning - -Wmissing-field-initializers - -It warns for all "{}" initializers. - -Reviewed-by: David Herrmann <dh.herrmann@gmail.com> -Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> ---- - configure.ac | 3 ++- - intel/intel_decode.c | 2 -- - 2 files changed, 2 insertions(+), 3 deletions(-) - -diff --git a/configure.ac b/configure.ac -index c8c4ace..057a846 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -174,7 +174,8 @@ MAYBE_WARN="-Wall -Wextra \ - -Wstrict-aliasing=2 -Winit-self \ - -Wdeclaration-after-statement -Wold-style-definition \ - -Wno-unused-parameter \ ---Wno-attributes -Wno-long-long -Winline -Wshadow" -+-Wno-attributes -Wno-long-long -Winline -Wshadow \ -+-Wno-missing-field-initializers" - - # invalidate cached value if MAYBE_WARN has changed - if test "x$libdrm_cv_warn_maybe" != "x$MAYBE_WARN"; then -diff --git a/intel/intel_decode.c b/intel/intel_decode.c -index e7aef74..287c342 100644 ---- a/intel/intel_decode.c -+++ b/intel/intel_decode.c -@@ -38,8 +38,6 @@ - #include "intel_chipset.h" - #include "intel_bufmgr.h" - --/* The compiler throws ~90 warnings. Do not spam the build, until we fix them. */ --#pragma GCC diagnostic ignored "-Wmissing-field-initializers" - - /* Struct for tracking drm_intel_decode state. */ - struct drm_intel_decode { --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0004-amdgpu-drop-address-patching-logics.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0004-amdgpu-drop-address-patching-logics.patch deleted file mode 100644 index 187930cd..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0004-amdgpu-drop-address-patching-logics.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 50386e09dbdc6fd70d02efd1371d9ad061c8d447 Mon Sep 17 00:00:00 2001 -From: "monk.liu" <monk.liu@amd.com> -Date: Tue, 25 Aug 2015 16:53:07 +0800 -Subject: [PATCH 004/117] amdgpu: drop address patching logics -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -we don't support non-page-aligned cpu pointer anymore - -Signed-off-by: monk.liu <monk.liu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_bo.c | 11 +---------- - 1 file changed, 1 insertion(+), 10 deletions(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 1a5a401..2ae1c18 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -537,17 +537,8 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, - int r; - struct amdgpu_bo *bo; - struct drm_amdgpu_gem_userptr args; -- uintptr_t cpu0; -- uint32_t ps, off; - -- memset(&args, 0, sizeof(args)); -- ps = getpagesize(); -- -- cpu0 = ROUND_DOWN((uintptr_t)cpu, ps); -- off = (uintptr_t)cpu - cpu0; -- size = ROUND_UP(size + off, ps); -- -- args.addr = cpu0; -+ args.addr = (uintptr_t)cpu; - args.flags = AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_REGISTER; - args.size = size; - r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0005-amdgpu-validate-user-memory-for-userptr.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0005-amdgpu-validate-user-memory-for-userptr.patch deleted file mode 100644 index 9379fd99..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0005-amdgpu-validate-user-memory-for-userptr.patch +++ /dev/null @@ -1,31 +0,0 @@ -From f06c9928198d9348fb31325a2a480afbc29c04b8 Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Mon, 30 Nov 2015 14:08:07 +0800 -Subject: [PATCH 005/117] amdgpu: validate user memory for userptr -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_bo.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 2ae1c18..d30fd1e 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -539,7 +539,8 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, - struct drm_amdgpu_gem_userptr args; - - args.addr = (uintptr_t)cpu; -- args.flags = AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_REGISTER; -+ args.flags = AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_REGISTER | -+ AMDGPU_GEM_USERPTR_VALIDATE; - args.size = size; - r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR, - &args, sizeof(args)); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0006-amdgpu-add-semaphore-support.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0006-amdgpu-add-semaphore-support.patch deleted file mode 100644 index e3801da4..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0006-amdgpu-add-semaphore-support.patch +++ /dev/null @@ -1,403 +0,0 @@ -From 6afadeaf13279fcdbc48999f522e1dc90a9dfdaf Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> -Date: Tue, 12 Jan 2016 22:13:07 +0100 -Subject: [PATCH 006/117] amdgpu: add semaphore support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -the semaphore is a binary semaphore. the work flow is: -1. create sem -2. signal sem -3. wait sem, reset sem after signalled -4. destroy sem. - -Signed-off-by: Chunming Zhou <david1.zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu.h | 65 ++++++++++++++++++ - amdgpu/amdgpu_cs.c | 173 +++++++++++++++++++++++++++++++++++++++++++++-- - amdgpu/amdgpu_internal.h | 15 ++++ - 3 files changed, 249 insertions(+), 4 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index e44d802..0851306 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -124,6 +124,11 @@ typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; - */ - typedef struct amdgpu_va *amdgpu_va_handle; - -+/** -+ * Define handle for semaphore -+ */ -+typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; -+ - /*--------------------------------------------------------------------------*/ - /* -------------------------- Structures ---------------------------------- */ - /*--------------------------------------------------------------------------*/ -@@ -1180,4 +1185,64 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, - uint64_t flags, - uint32_t ops); - -+/** -+ * create semaphore -+ * -+ * \param sem - \c [out] semaphore handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); -+ -+/** -+ * signal semaphore -+ * -+ * \param context - \c [in] GPU Context -+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* -+ * \param ip_instance - \c [in] Index of the IP block of the same type -+ * \param ring - \c [in] Specify ring index of the IP -+ * \param sem - \c [in] semaphore handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_semaphore_handle sem); -+ -+/** -+ * wait semaphore -+ * -+ * \param context - \c [in] GPU Context -+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* -+ * \param ip_instance - \c [in] Index of the IP block of the same type -+ * \param ring - \c [in] Specify ring index of the IP -+ * \param sem - \c [in] semaphore handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_semaphore_handle sem); -+ -+/** -+ * destroy semaphore -+ * -+ * \param sem - \c [in] semaphore handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); -+ - #endif /* #ifdef _AMDGPU_H_ */ -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 6747158..1848ade 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -40,6 +40,9 @@ - #include "amdgpu_drm.h" - #include "amdgpu_internal.h" - -+static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem); -+static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem); -+ - /** - * Create command submission context - * -@@ -53,6 +56,7 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, - { - struct amdgpu_context *gpu_context; - union drm_amdgpu_ctx args; -+ int i, j, k; - int r; - - if (NULL == dev) -@@ -66,6 +70,10 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, - - gpu_context->dev = dev; - -+ r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL); -+ if (r) -+ goto error; -+ - /* Create the context */ - memset(&args, 0, sizeof(args)); - args.in.op = AMDGPU_CTX_OP_ALLOC_CTX; -@@ -74,11 +82,16 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, - goto error; - - gpu_context->id = args.out.alloc.ctx_id; -+ for (i = 0; i < AMDGPU_HW_IP_NUM; i++) -+ for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) -+ for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) -+ list_inithead(&gpu_context->sem_list[i][j][k]); - *context = (amdgpu_context_handle)gpu_context; - - return 0; - - error: -+ pthread_mutex_destroy(&gpu_context->sequence_mutex); - free(gpu_context); - return r; - } -@@ -94,18 +107,32 @@ error: - int amdgpu_cs_ctx_free(amdgpu_context_handle context) - { - union drm_amdgpu_ctx args; -+ int i, j, k; - int r; - - if (NULL == context) - return -EINVAL; - -+ pthread_mutex_destroy(&context->sequence_mutex); -+ - /* now deal with kernel side */ - memset(&args, 0, sizeof(args)); - args.in.op = AMDGPU_CTX_OP_FREE_CTX; - args.in.ctx_id = context->id; - r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX, - &args, sizeof(args)); -- -+ for (i = 0; i < AMDGPU_HW_IP_NUM; i++) { -+ for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) { -+ for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) { -+ amdgpu_semaphore_handle sem; -+ LIST_FOR_EACH_ENTRY(sem, &context->sem_list[i][j][k], list) { -+ list_del(&sem->list); -+ amdgpu_cs_reset_sem(sem); -+ amdgpu_cs_unreference_sem(sem); -+ } -+ } -+ } -+ } - free(context); - - return r; -@@ -150,7 +177,10 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - struct drm_amdgpu_cs_chunk *chunks; - struct drm_amdgpu_cs_chunk_data *chunk_data; - struct drm_amdgpu_cs_chunk_dep *dependencies = NULL; -- uint32_t i, size; -+ struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL; -+ struct list_head *sem_list; -+ amdgpu_semaphore_handle sem; -+ uint32_t i, size, sem_count = 0; - bool user_fence; - int r = 0; - -@@ -162,7 +192,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - return -EINVAL; - user_fence = (ibs_request->fence_info.handle != NULL); - -- size = ibs_request->number_of_ibs + (user_fence ? 2 : 1); -+ size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1; - - chunk_array = alloca(sizeof(uint64_t) * size); - chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size); -@@ -196,6 +226,8 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - chunk_data[i].ib_data.flags = ib->flags; - } - -+ pthread_mutex_lock(&context->sequence_mutex); -+ - if (user_fence) { - i = cs.in.num_chunks++; - -@@ -240,15 +272,49 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - chunks[i].chunk_data = (uint64_t)(uintptr_t)dependencies; - } - -+ sem_list = &context->sem_list[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring]; -+ LIST_FOR_EACH_ENTRY(sem, sem_list, list) -+ sem_count++; -+ if (sem_count) { -+ sem_dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_count); -+ if (!sem_dependencies) { -+ r = -ENOMEM; -+ goto error_unlock; -+ } -+ sem_count = 0; -+ LIST_FOR_EACH_ENTRY(sem, sem_list, list) { -+ struct amdgpu_cs_fence *info = &sem->signal_fence; -+ struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++]; -+ dep->ip_type = info->ip_type; -+ dep->ip_instance = info->ip_instance; -+ dep->ring = info->ring; -+ dep->ctx_id = info->context->id; -+ dep->handle = info->fence; -+ -+ list_del(&sem->list); -+ amdgpu_cs_reset_sem(sem); -+ amdgpu_cs_unreference_sem(sem); -+ } -+ i = cs.in.num_chunks++; -+ -+ /* dependencies chunk */ -+ chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i]; -+ chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES; -+ chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count; -+ chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies; -+ } -+ - r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS, - &cs, sizeof(cs)); - if (r) - goto error_unlock; - - ibs_request->seq_no = cs.out.handle; -- -+ context->last_seq[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring] = ibs_request->seq_no; - error_unlock: -+ pthread_mutex_unlock(&context->sequence_mutex); - free(dependencies); -+ free(sem_dependencies); - return r; - } - -@@ -369,3 +435,102 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - return r; - } - -+int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) -+{ -+ struct amdgpu_semaphore *gpu_semaphore; -+ -+ if (NULL == sem) -+ return -EINVAL; -+ -+ gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore)); -+ if (NULL == gpu_semaphore) -+ return -ENOMEM; -+ -+ atomic_set(&gpu_semaphore->refcount, 1); -+ *sem = gpu_semaphore; -+ -+ return 0; -+} -+ -+int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_semaphore_handle sem) -+{ -+ if (NULL == ctx) -+ return -EINVAL; -+ if (ip_type >= AMDGPU_HW_IP_NUM) -+ return -EINVAL; -+ if (ring >= AMDGPU_CS_MAX_RINGS) -+ return -EINVAL; -+ if (NULL == sem) -+ return -EINVAL; -+ /* sem has been signaled */ -+ if (sem->signal_fence.context) -+ return -EINVAL; -+ pthread_mutex_lock(&ctx->sequence_mutex); -+ sem->signal_fence.context = ctx; -+ sem->signal_fence.ip_type = ip_type; -+ sem->signal_fence.ip_instance = ip_instance; -+ sem->signal_fence.ring = ring; -+ sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring]; -+ update_references(NULL, &sem->refcount); -+ pthread_mutex_unlock(&ctx->sequence_mutex); -+ return 0; -+} -+ -+int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_semaphore_handle sem) -+{ -+ if (NULL == ctx) -+ return -EINVAL; -+ if (ip_type >= AMDGPU_HW_IP_NUM) -+ return -EINVAL; -+ if (ring >= AMDGPU_CS_MAX_RINGS) -+ return -EINVAL; -+ if (NULL == sem) -+ return -EINVAL; -+ /* must signal first */ -+ if (NULL == sem->signal_fence.context) -+ return -EINVAL; -+ -+ pthread_mutex_lock(&ctx->sequence_mutex); -+ list_add(&sem->list, &ctx->sem_list[ip_type][ip_instance][ring]); -+ pthread_mutex_unlock(&ctx->sequence_mutex); -+ return 0; -+} -+ -+static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem) -+{ -+ if (NULL == sem) -+ return -EINVAL; -+ if (NULL == sem->signal_fence.context) -+ return -EINVAL; -+ -+ sem->signal_fence.context = NULL;; -+ sem->signal_fence.ip_type = 0; -+ sem->signal_fence.ip_instance = 0; -+ sem->signal_fence.ring = 0; -+ sem->signal_fence.fence = 0; -+ -+ return 0; -+} -+ -+static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem) -+{ -+ if (NULL == sem) -+ return -EINVAL; -+ -+ if (update_references(&sem->refcount, NULL)) -+ free(sem); -+ return 0; -+} -+ -+int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) -+{ -+ return amdgpu_cs_unreference_sem(sem); -+} -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 7dd5c1c..557ba1f 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -111,8 +111,23 @@ struct amdgpu_bo_list { - - struct amdgpu_context { - struct amdgpu_device *dev; -+ /** Mutex for accessing fences and to maintain command submissions -+ in good sequence. */ -+ pthread_mutex_t sequence_mutex; - /* context id*/ - uint32_t id; -+ uint64_t last_seq[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS]; -+ struct list_head sem_list[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS]; -+}; -+ -+/** -+ * Structure describing sw semaphore based on scheduler -+ * -+ */ -+struct amdgpu_semaphore { -+ atomic_t refcount; -+ struct list_head list; -+ struct amdgpu_cs_fence signal_fence; - }; - - /** --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0007-tests-amdgpu-add-semaphore-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0007-tests-amdgpu-add-semaphore-test.patch deleted file mode 100644 index ae7c4bd9..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0007-tests-amdgpu-add-semaphore-test.patch +++ /dev/null @@ -1,183 +0,0 @@ -From d4d4184363a62ece6b8830cacaf390b5638d7f8e Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <david1.zhou@amd.com> -Date: Mon, 10 Aug 2015 17:08:25 +0800 -Subject: [PATCH 007/117] tests/amdgpu: add semaphore test -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Chunming Zhou <david1.zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/basic_tests.c | 133 +++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 133 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index e489e6e..fa0ed12 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -47,6 +47,7 @@ static void amdgpu_command_submission_gfx(void); - static void amdgpu_command_submission_compute(void); - static void amdgpu_command_submission_sdma(void); - static void amdgpu_userptr_test(void); -+static void amdgpu_semaphore_test(void); - - CU_TestInfo basic_tests[] = { - { "Query Info Test", amdgpu_query_info_test }, -@@ -55,6 +56,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, - { "Command submission Test (Compute)", amdgpu_command_submission_compute }, - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, -+ { "SW semaphore Test", amdgpu_semaphore_test }, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) -@@ -77,6 +79,9 @@ CU_TestInfo basic_tests[] = { - #define SDMA_OPCODE_COPY 1 - # define SDMA_COPY_SUB_OPCODE_LINEAR 0 - -+#define GFX_COMPUTE_NOP 0xffff1000 -+#define SDMA_NOP 0x0 -+ - int suite_basic_tests_init(void) - { - int r; -@@ -333,6 +338,134 @@ static void amdgpu_command_submission_gfx(void) - amdgpu_command_submission_gfx_shared_ib(); - } - -+static void amdgpu_semaphore_test(void) -+{ -+ amdgpu_context_handle context_handle[2]; -+ amdgpu_semaphore_handle sem; -+ amdgpu_bo_handle ib_result_handle[2]; -+ void *ib_result_cpu[2]; -+ uint64_t ib_result_mc_address[2]; -+ struct amdgpu_cs_request ibs_request[2] = {0}; -+ struct amdgpu_cs_ib_info ib_info[2] = {0}; -+ struct amdgpu_cs_fence fence_status = {0}; -+ uint32_t *ptr; -+ uint32_t expired; -+ amdgpu_bo_list_handle bo_list[2]; -+ amdgpu_va_handle va_handle[2]; -+ int r, i; -+ -+ r = amdgpu_cs_create_semaphore(&sem); -+ CU_ASSERT_EQUAL(r, 0); -+ for (i = 0; i < 2; i++) { -+ r = amdgpu_cs_ctx_create(device_handle, &context_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, -+ AMDGPU_GEM_DOMAIN_GTT, 0, -+ &ib_result_handle[i], &ib_result_cpu[i], -+ &ib_result_mc_address[i], &va_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_get_bo_list(device_handle, ib_result_handle[i], -+ NULL, &bo_list[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ /* 1. same context different engine */ -+ ptr = ib_result_cpu[0]; -+ ptr[0] = SDMA_NOP; -+ ib_info[0].ib_mc_address = ib_result_mc_address[0]; -+ ib_info[0].size = 1; -+ -+ ibs_request[0].ip_type = AMDGPU_HW_IP_DMA; -+ ibs_request[0].number_of_ibs = 1; -+ ibs_request[0].ibs = &ib_info[0]; -+ ibs_request[0].resources = bo_list[0]; -+ ibs_request[0].fence_info.handle = NULL; -+ r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); -+ CU_ASSERT_EQUAL(r, 0); -+ ptr = ib_result_cpu[1]; -+ ptr[0] = GFX_COMPUTE_NOP; -+ ib_info[1].ib_mc_address = ib_result_mc_address[1]; -+ ib_info[1].size = 1; -+ -+ ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; -+ ibs_request[1].number_of_ibs = 1; -+ ibs_request[1].ibs = &ib_info[1]; -+ ibs_request[1].resources = bo_list[1]; -+ ibs_request[1].fence_info.handle = NULL; -+ -+ r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[1], 1); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ fence_status.context = context_handle[0]; -+ fence_status.ip_type = AMDGPU_HW_IP_GFX; -+ fence_status.fence = ibs_request[1].seq_no; -+ r = amdgpu_cs_query_fence_status(&fence_status, -+ 500000000, 0, &expired); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_EQUAL(expired, true); -+ -+ /* 2. same engine different context */ -+ ptr = ib_result_cpu[0]; -+ ptr[0] = GFX_COMPUTE_NOP; -+ ib_info[0].ib_mc_address = ib_result_mc_address[0]; -+ ib_info[0].size = 1; -+ -+ ibs_request[0].ip_type = AMDGPU_HW_IP_GFX; -+ ibs_request[0].number_of_ibs = 1; -+ ibs_request[0].ibs = &ib_info[0]; -+ ibs_request[0].resources = bo_list[0]; -+ ibs_request[0].fence_info.handle = NULL; -+ r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem); -+ CU_ASSERT_EQUAL(r, 0); -+ ptr = ib_result_cpu[1]; -+ ptr[0] = GFX_COMPUTE_NOP; -+ ib_info[1].ib_mc_address = ib_result_mc_address[1]; -+ ib_info[1].size = 1; -+ -+ ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; -+ ibs_request[1].number_of_ibs = 1; -+ ibs_request[1].ibs = &ib_info[1]; -+ ibs_request[1].resources = bo_list[1]; -+ ibs_request[1].fence_info.handle = NULL; -+ r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request[1], 1); -+ -+ CU_ASSERT_EQUAL(r, 0); -+ -+ fence_status.context = context_handle[1]; -+ fence_status.ip_type = AMDGPU_HW_IP_GFX; -+ fence_status.fence = ibs_request[1].seq_no; -+ r = amdgpu_cs_query_fence_status(&fence_status, -+ 500000000, 0, &expired); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_EQUAL(expired, true); -+ for (i = 0; i < 2; i++) { -+ r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i], -+ ib_result_mc_address[i], 4096); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_list_destroy(bo_list[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_cs_ctx_free(context_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ r = amdgpu_cs_destroy_semaphore(sem); -+ CU_ASSERT_EQUAL(r, 0); -+} -+ - static void amdgpu_command_submission_compute(void) - { - amdgpu_context_handle context_handle; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0008-amdgpu-list-each-entry-safely-for-sw-semaphore-when-.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0008-amdgpu-list-each-entry-safely-for-sw-semaphore-when-.patch deleted file mode 100644 index 58cb2238..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0008-amdgpu-list-each-entry-safely-for-sw-semaphore-when-.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 6b79c66b841dded6ffa6b56f14e4eb10a90a7c07 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Tue, 8 Dec 2015 08:34:55 +0800 -Subject: [PATCH 008/117] amdgpu: list each entry safely for sw semaphore when - submit ib -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> -Reviewed-by: David Zhou <david1.zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_cs.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 1848ade..b4f41b0 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -179,7 +179,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - struct drm_amdgpu_cs_chunk_dep *dependencies = NULL; - struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL; - struct list_head *sem_list; -- amdgpu_semaphore_handle sem; -+ amdgpu_semaphore_handle sem, tmp; - uint32_t i, size, sem_count = 0; - bool user_fence; - int r = 0; -@@ -282,7 +282,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - goto error_unlock; - } - sem_count = 0; -- LIST_FOR_EACH_ENTRY(sem, sem_list, list) { -+ LIST_FOR_EACH_ENTRY_SAFE(sem, tmp, sem_list, list) { - struct amdgpu_cs_fence *info = &sem->signal_fence; - struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++]; - dep->ip_type = info->ip_type; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0009-amdgpu-Add-new-symbols-to-amdgpu-symbols-check.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0009-amdgpu-Add-new-symbols-to-amdgpu-symbols-check.patch deleted file mode 100644 index 2130d0c9..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0009-amdgpu-Add-new-symbols-to-amdgpu-symbols-check.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 25712f1d35f6f64167ede45d3dc72a410f367ceb Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com> -Date: Wed, 20 Jan 2016 15:59:08 +0900 -Subject: [PATCH 009/117] amdgpu: Add new symbols to amdgpu-symbols-check - -Fixes make check. - -Trivial. ---- - amdgpu/amdgpu-symbol-check | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index 9a0b36c..648db9b 100755 ---- a/amdgpu/amdgpu-symbol-check -+++ b/amdgpu/amdgpu-symbol-check -@@ -24,11 +24,15 @@ amdgpu_bo_set_metadata - amdgpu_bo_va_op - amdgpu_bo_wait_for_idle - amdgpu_create_bo_from_user_mem -+amdgpu_cs_create_semaphore - amdgpu_cs_ctx_create - amdgpu_cs_ctx_free -+amdgpu_cs_destroy_semaphore - amdgpu_cs_query_fence_status - amdgpu_cs_query_reset_state -+amdgpu_cs_signal_semaphore - amdgpu_cs_submit -+amdgpu_cs_wait_semaphore - amdgpu_device_deinitialize - amdgpu_device_initialize - amdgpu_query_buffer_size_alignment --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0010-radeon-Pass-radeon_bo_open-flags-to-the-DRM_RADEON_G.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0010-radeon-Pass-radeon_bo_open-flags-to-the-DRM_RADEON_G.patch deleted file mode 100644 index 2eb10e95..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0010-radeon-Pass-radeon_bo_open-flags-to-the-DRM_RADEON_G.patch +++ /dev/null @@ -1,30 +0,0 @@ -From db138b9ba12a0de5d6140832c0679c2418e3e7e0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com> -Date: Thu, 21 Jan 2016 18:08:49 +0900 -Subject: [PATCH 010/117] radeon: Pass radeon_bo_open flags to the - DRM_RADEON_GEM_CREATE ioctl - -Not doing so makes it impossible for radeon_bo_open callers to set any -RADEON_GEM_* flags for the newly created BO. - -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - radeon/radeon_bo_gem.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c -index c9fe19f..fbd453d 100644 ---- a/radeon/radeon_bo_gem.c -+++ b/radeon/radeon_bo_gem.c -@@ -103,7 +103,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, - args.size = size; - args.alignment = alignment; - args.initial_domain = bo->base.domains; -- args.flags = 0; -+ args.flags = flags; - args.handle = 0; - r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE, - &args, sizeof(args)); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0011-xf86drm-Bound-strstr-to-the-allocated-data.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0011-xf86drm-Bound-strstr-to-the-allocated-data.patch deleted file mode 100644 index ecb7325a..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0011-xf86drm-Bound-strstr-to-the-allocated-data.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 3627f38da9fad7db7fef2a0c6d0faf706c2e21d6 Mon Sep 17 00:00:00 2001 -From: Damien Lespiau <damien.lespiau@intel.com> -Date: Fri, 22 Jan 2016 12:41:55 +0000 -Subject: [PATCH 011/117] xf86drm: Bound strstr() to the allocated data -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -We are reading at most sizeof(data) bytes, but then data may not contain -a terminating '\0', at least in theory, so strstr() may overflow the -stack allocated array. - -Make sure that data always contains at least one '\0'. - -Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> -Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> ---- - xf86drm.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/xf86drm.c b/xf86drm.c -index 7e28b4f..5f587d9 100644 ---- a/xf86drm.c -+++ b/xf86drm.c -@@ -2863,7 +2863,7 @@ static int drmParsePciBusInfo(int maj, int min, drmPciBusInfoPtr info) - { - #ifdef __linux__ - char path[PATH_MAX + 1]; -- char data[128]; -+ char data[128 + 1]; - char *str; - int domain, bus, dev, func; - int fd, ret; -@@ -2874,6 +2874,7 @@ static int drmParsePciBusInfo(int maj, int min, drmPciBusInfoPtr info) - return -errno; - - ret = read(fd, data, sizeof(data)); -+ data[128] = '\0'; - close(fd); - if (ret < 0) - return -errno; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0012-configure.ac-don-t-detect-disabled-options-dependenc.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0012-configure.ac-don-t-detect-disabled-options-dependenc.patch deleted file mode 100644 index eef84dae..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0012-configure.ac-don-t-detect-disabled-options-dependenc.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 798022b61c58d945f9027c823a188dcedecd3d06 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= <marcin.slusarz@gmail.com> -Date: Sun, 24 Jan 2016 13:17:34 +0100 -Subject: [PATCH 012/117] configure.ac: don't detect disabled options - dependencies -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Currently with --disable-amdgpu --disable-valgrind --disable-cairo-tests -cunit, valgrind and cairo are still detected. - -Signed-off-by: Marcin Ślusarz <marcin.slusarz@gmail.com> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - configure.ac | 36 ++++++++++++++++++++++-------------- - 1 file changed, 22 insertions(+), 14 deletions(-) - -diff --git a/configure.ac b/configure.ac -index 057a846..a09be61 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -360,19 +360,23 @@ if test "x$RADEON" = xyes; then - AC_DEFINE(HAVE_RADEON, 1, [Have radeon support]) - fi - --# Detect cunit library --PKG_CHECK_MODULES([CUNIT], [cunit >= 2.1], [have_cunit=yes], [have_cunit=no]) --# If pkg-config does not find cunit, check it using AC_CHECK_LIB. We --# do this because Debian (Ubuntu) lacks pkg-config file for cunit. --# fixed in 2.1-2.dfsg-3: http://anonscm.debian.org/cgit/collab-maint/cunit.git/commit/?h=debian --if test "x${have_cunit}" = "xno"; then -- AC_CHECK_LIB([cunit], [CU_initialize_registry], [have_cunit=yes], [have_cunit=no]) -- if test "x${have_cunit}" = "xyes"; then -- CUNIT_LIBS="-lcunit" -- CUNIT_CFLAGS="" -- AC_SUBST([CUNIT_LIBS]) -- AC_SUBST([CUNIT_CFLAGS]) -+if test "x$AMDGPU" != xno; then -+ # Detect cunit library -+ PKG_CHECK_MODULES([CUNIT], [cunit >= 2.1], [have_cunit=yes], [have_cunit=no]) -+ # If pkg-config does not find cunit, check it using AC_CHECK_LIB. We -+ # do this because Debian (Ubuntu) lacks pkg-config file for cunit. -+ # fixed in 2.1-2.dfsg-3: http://anonscm.debian.org/cgit/collab-maint/cunit.git/commit/?h=debian -+ if test "x${have_cunit}" = "xno"; then -+ AC_CHECK_LIB([cunit], [CU_initialize_registry], [have_cunit=yes], [have_cunit=no]) -+ if test "x${have_cunit}" = "xyes"; then -+ CUNIT_LIBS="-lcunit" -+ CUNIT_CFLAGS="" -+ AC_SUBST([CUNIT_LIBS]) -+ AC_SUBST([CUNIT_CFLAGS]) -+ fi - fi -+else -+ have_cunit=no - fi - AM_CONDITIONAL(HAVE_CUNIT, [test "x$have_cunit" != "xno"]) - -@@ -401,7 +405,9 @@ AC_ARG_ENABLE([cairo-tests], - [AS_HELP_STRING([--enable-cairo-tests], - [Enable support for Cairo rendering in tests (default: auto)])], - [CAIRO=$enableval], [CAIRO=auto]) --PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no]) -+if test "x$CAIRO" != xno; then -+ PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no]) -+fi - AC_MSG_CHECKING([whether to enable Cairo tests]) - if test "x$CAIRO" = xauto; then - CAIRO="$HAVE_CAIRO" -@@ -446,7 +452,9 @@ AC_ARG_ENABLE(valgrind, - [AS_HELP_STRING([--enable-valgrind], - [Build libdrm with valgrind support (default: auto)])], - [VALGRIND=$enableval], [VALGRIND=auto]) --PKG_CHECK_MODULES(VALGRIND, [valgrind], [have_valgrind=yes], [have_valgrind=no]) -+if test "x$VALGRIND" != xno; then -+ PKG_CHECK_MODULES(VALGRIND, [valgrind], [have_valgrind=yes], [have_valgrind=no]) -+fi - AC_MSG_CHECKING([whether to enable Valgrind support]) - if test "x$VALGRIND" = xauto; then - VALGRIND="$have_valgrind" --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0013-kmstest-Use-util_open.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0013-kmstest-Use-util_open.patch deleted file mode 100644 index 88c71442..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0013-kmstest-Use-util_open.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 0caf58a6cb82327a3f6a53f05dea8e02f1412a05 Mon Sep 17 00:00:00 2001 -From: Stefan Agner <stefan@agner.ch> -Date: Sat, 19 Dec 2015 21:52:58 -0800 -Subject: [PATCH 013/117] kmstest: Use util_open() - -Use the new util_open() helper instead of open-coding the method for -finding a usable device. While at it, make the command-line interface -more consistent with that of modetest by adding the -D and -M options. - -Signed-off-by: Stefan Agner <stefan@agner.ch> -v2: correctly use util_open() - swap device, module -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/kmstest/Makefile.am | 4 +++- - tests/kmstest/main.c | 45 +++++++++++++++++++++++++++++---------------- - 2 files changed, 32 insertions(+), 17 deletions(-) - -diff --git a/tests/kmstest/Makefile.am b/tests/kmstest/Makefile.am -index fd21e61..100662e 100644 ---- a/tests/kmstest/Makefile.am -+++ b/tests/kmstest/Makefile.am -@@ -2,6 +2,7 @@ AM_CFLAGS = \ - $(WARN_CFLAGS)\ - -I$(top_srcdir)/include/drm \ - -I$(top_srcdir)/libkms/ \ -+ -I$(top_srcdir)/tests/ \ - -I$(top_srcdir) - - if HAVE_INSTALL_TESTS -@@ -17,7 +18,8 @@ kmstest_SOURCES = \ - - kmstest_LDADD = \ - $(top_builddir)/libdrm.la \ -- $(top_builddir)/libkms/libkms.la -+ $(top_builddir)/libkms/libkms.la \ -+ $(top_builddir)/tests/util/libutil.la - - run: kmstest - ./kmstest -diff --git a/tests/kmstest/main.c b/tests/kmstest/main.c -index 120bc0f..a0e4ebb 100644 ---- a/tests/kmstest/main.c -+++ b/tests/kmstest/main.c -@@ -25,12 +25,14 @@ - * - **************************************************************************/ - -- -+#include <getopt.h> - #include <stdio.h> - #include <string.h> - #include "xf86drm.h" - #include "libkms.h" - -+#include "util/kms.h" -+ - #define CHECK_RET_RETURN(ret, str) \ - if (ret < 0) { \ - printf("%s: %s (%s)\n", __func__, str, strerror(-ret)); \ -@@ -56,26 +58,37 @@ static int test_bo(struct kms_driver *kms) - return 0; - } - --static const char *drivers[] = { -- "i915", -- "radeon", -- "nouveau", -- "vmwgfx", -- "exynos", -- "amdgpu", -- "imx-drm", -- "rockchip", -- "atmel-hlcdc", -- NULL --}; -+static void usage(const char *program) -+{ -+ fprintf(stderr, "Usage: %s [options]\n", program); -+ fprintf(stderr, "\n"); -+ fprintf(stderr, " -D DEVICE open the given device\n"); -+ fprintf(stderr, " -M MODULE open the given module\n"); -+} - - int main(int argc, char** argv) - { -+ static const char optstr[] = "D:M:"; - struct kms_driver *kms; -- int ret, fd, i; -+ int c, fd, ret; -+ char *device = NULL; -+ char *module = NULL; -+ -+ while ((c = getopt(argc, argv, optstr)) != -1) { -+ switch (c) { -+ case 'D': -+ device = optarg; -+ break; -+ case 'M': -+ module = optarg; -+ break; -+ default: -+ usage(argv[0]); -+ return 0; -+ } -+ } - -- for (i = 0, fd = -1; fd < 0 && drivers[i]; i++) -- fd = drmOpen(drivers[i], NULL); -+ fd = util_open(device, module); - CHECK_RET_RETURN(fd, "Could not open device"); - - ret = kms_create(fd, &kms); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0014-tests-add-fsl-dcu-drm-to-modules.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0014-tests-add-fsl-dcu-drm-to-modules.patch deleted file mode 100644 index fd43c02c..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0014-tests-add-fsl-dcu-drm-to-modules.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2ad5ea780b3cca83ae4f531ae0b4159e802ef825 Mon Sep 17 00:00:00 2001 -From: Stefan Agner <stefan@agner.ch> -Date: Sat, 19 Dec 2015 21:52:59 -0800 -Subject: [PATCH 014/117] tests: add fsl-dcu-drm to modules - -Signed-off-by: Stefan Agner <stefan@agner.ch> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/util/kms.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/tests/util/kms.c b/tests/util/kms.c -index 57b0191..dcd5a8e 100644 ---- a/tests/util/kms.c -+++ b/tests/util/kms.c -@@ -139,6 +139,7 @@ static const char * const modules[] = { - "imx-drm", - "rockchip", - "atmel-hlcdc", -+ "fsl-dcu-drm", - }; - - int util_open(const char *device, const char *module) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0015-tests-util-Fixup-util_open-parameter-order.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0015-tests-util-Fixup-util_open-parameter-order.patch deleted file mode 100644 index bb7969bb..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0015-tests-util-Fixup-util_open-parameter-order.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 1674147a149c2165a927a5d8eb0db4eee1f6a4e3 Mon Sep 17 00:00:00 2001 -From: Thierry Reding <treding@nvidia.com> -Date: Tue, 5 Jan 2016 15:21:23 +0100 -Subject: [PATCH 015/117] tests: util: Fixup util_open() parameter order - -util_open() takes a device parameter, followed by a module parameter. -The existing tests used the drmOpen() function, which uses a different -ordering of the parameters, and the old ordering was accidentally kept -during the conversion. - -Signed-off-by: Thierry Reding <treding@nvidia.com> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/modetest/modetest.c | 2 +- - tests/proptest/proptest.c | 2 +- - tests/vbltest/vbltest.c | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c -index 22e3e81..f665240 100644 ---- a/tests/modetest/modetest.c -+++ b/tests/modetest/modetest.c -@@ -1603,7 +1603,7 @@ int main(int argc, char **argv) - if (!args) - encoders = connectors = crtcs = planes = framebuffers = 1; - -- dev.fd = util_open(module, device); -+ dev.fd = util_open(device, module); - if (dev.fd < 0) - return -1; - -diff --git a/tests/proptest/proptest.c b/tests/proptest/proptest.c -index 24c6345..4bd0866 100644 ---- a/tests/proptest/proptest.c -+++ b/tests/proptest/proptest.c -@@ -295,7 +295,7 @@ int main(int argc, char *argv[]) - - args = argc - optind; - -- fd = util_open(module, device); -+ fd = util_open(device, module); - if (fd < 0) - return 1; - -diff --git a/tests/vbltest/vbltest.c b/tests/vbltest/vbltest.c -index 1833321..4475b49 100644 ---- a/tests/vbltest/vbltest.c -+++ b/tests/vbltest/vbltest.c -@@ -120,7 +120,7 @@ int main(int argc, char **argv) - } - } - -- fd = util_open(module, device); -+ fd = util_open(device, module); - if (fd < 0) - return 1; - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0016-tests-Include-sys-select.h.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0016-tests-Include-sys-select.h.patch deleted file mode 100644 index 0427f35f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0016-tests-Include-sys-select.h.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 358615f416a8f3085a63c03a55564f71946083d1 Mon Sep 17 00:00:00 2001 -From: Khem Raj <raj.khem@gmail.com> -Date: Wed, 20 Jan 2016 05:35:11 +0000 -Subject: [PATCH 016/117] tests: Include sys/select.h - -Used in compliance with POSIX 2001/2008 - -Fixes errors e.g. -error: implicit declaration of function 'select' - -and helps with missing definitions of FD_* defines - -v2: conditionally include sys/select.h, include in every test where -needed. - -Signed-off-by: Khem Raj <raj.khem@gmail.com> -Reviewed-by: Thierry Reding <thierry.reding@gmail.com> (v1) -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - configure.ac | 2 +- - tests/kms/kms-steal-crtc.c | 3 +++ - tests/kms/kms-universal-planes.c | 3 +++ - tests/modetest/modetest.c | 3 +++ - tests/vbltest/vbltest.c | 3 +++ - 5 files changed, 13 insertions(+), 1 deletion(-) - -diff --git a/configure.ac b/configure.ac -index a09be61..4635d18 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -53,7 +53,7 @@ AC_USE_SYSTEM_EXTENSIONS - AC_SYS_LARGEFILE - AC_FUNC_ALLOCA - --AC_CHECK_HEADERS([sys/mkdev.h sys/sysctl.h]) -+AC_CHECK_HEADERS([sys/mkdev.h sys/sysctl.h sys/select.h]) - - # Initialize libtool - LT_PREREQ([2.2]) -diff --git a/tests/kms/kms-steal-crtc.c b/tests/kms/kms-steal-crtc.c -index 2f7f327..497772e 100644 ---- a/tests/kms/kms-steal-crtc.c -+++ b/tests/kms/kms-steal-crtc.c -@@ -31,6 +31,9 @@ - #include <stdio.h> - #include <string.h> - #include <unistd.h> -+#ifdef HAVE_SYS_SELECT_H -+#include <sys/select.h> -+#endif - - #include <drm_fourcc.h> - -diff --git a/tests/kms/kms-universal-planes.c b/tests/kms/kms-universal-planes.c -index 9151231..d8e5fc4 100644 ---- a/tests/kms/kms-universal-planes.c -+++ b/tests/kms/kms-universal-planes.c -@@ -32,6 +32,9 @@ - #include <stdio.h> - #include <string.h> - #include <unistd.h> -+#ifdef HAVE_SYS_SELECT_H -+#include <sys/select.h> -+#endif - - #include <drm_fourcc.h> - #include "xf86drm.h" -diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c -index f665240..b8aa94b 100644 ---- a/tests/modetest/modetest.c -+++ b/tests/modetest/modetest.c -@@ -55,6 +55,9 @@ - #include <errno.h> - #include <sys/poll.h> - #include <sys/time.h> -+#ifdef HAVE_SYS_SELECT_H -+#include <sys/select.h> -+#endif - - #include "xf86drm.h" - #include "xf86drmMode.h" -diff --git a/tests/vbltest/vbltest.c b/tests/vbltest/vbltest.c -index 4475b49..97dd44d 100644 ---- a/tests/vbltest/vbltest.c -+++ b/tests/vbltest/vbltest.c -@@ -37,6 +37,9 @@ - #include <errno.h> - #include <sys/poll.h> - #include <sys/time.h> -+#ifdef HAVE_SYS_SELECT_H -+#include <sys/select.h> -+#endif - - #include "xf86drm.h" - #include "xf86drmMode.h" --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0017-tests-Include-poll.h-rather-than-sys-poll.h.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0017-tests-Include-poll.h-rather-than-sys-poll.h.patch deleted file mode 100644 index e95eb5a7..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0017-tests-Include-poll.h-rather-than-sys-poll.h.patch +++ /dev/null @@ -1,46 +0,0 @@ -From ff0c9caa8e1e076b82241304dfd19d5b3e2a2aec Mon Sep 17 00:00:00 2001 -From: Kylie McClain <somasis@exherbo.org> -Date: Tue, 19 Jan 2016 22:27:28 -0500 -Subject: [PATCH 017/117] tests: Include poll.h rather than sys/poll.h - -sys/poll.h is a non-standard location of the poll.h header, and is -incorrect on non-glibc libcs. poll.h, however, is defined in SUS (v2) -and is more portable. - -Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93764 -http://pubs.opengroup.org/onlinepubs/007908799/xsh/poll.h.html -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/modetest/modetest.c | 2 +- - tests/vbltest/vbltest.c | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c -index b8aa94b..a5ac5bd 100644 ---- a/tests/modetest/modetest.c -+++ b/tests/modetest/modetest.c -@@ -53,7 +53,7 @@ - #include <string.h> - #include <strings.h> - #include <errno.h> --#include <sys/poll.h> -+#include <poll.h> - #include <sys/time.h> - #ifdef HAVE_SYS_SELECT_H - #include <sys/select.h> -diff --git a/tests/vbltest/vbltest.c b/tests/vbltest/vbltest.c -index 97dd44d..3f6b803 100644 ---- a/tests/vbltest/vbltest.c -+++ b/tests/vbltest/vbltest.c -@@ -35,7 +35,7 @@ - #include <unistd.h> - #include <string.h> - #include <errno.h> --#include <sys/poll.h> -+#include <poll.h> - #include <sys/time.h> - #ifdef HAVE_SYS_SELECT_H - #include <sys/select.h> --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0018-tests-kmstest-inverse-the-order-of-LDADD-libraries.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0018-tests-kmstest-inverse-the-order-of-LDADD-libraries.patch deleted file mode 100644 index f76604c0..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0018-tests-kmstest-inverse-the-order-of-LDADD-libraries.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 432e08de88a27313608cced27f133a65e8a56c52 Mon Sep 17 00:00:00 2001 -From: Emil Velikov <emil.l.velikov@gmail.com> -Date: Wed, 27 Jan 2016 11:59:43 +0000 -Subject: [PATCH 018/117] tests/kmstest: inverse the order of LDADD libraries - -The utils library depends on libdrm. Flip the order, orderwise we might -error during link stage like below: - - CC main.o - CCLD kmstest -/usr/bin/ld: ../../tests/util/.libs/libutil.a(libutil_la-kms.o): -undefined reference to symbol 'drmOpen' - -Reported-by: Tom Stellard <thomas.stellard@amd.com> -Tested-by: Tom Stellard <thomas.stellard@amd.com> -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/kmstest/Makefile.am | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/tests/kmstest/Makefile.am b/tests/kmstest/Makefile.am -index 100662e..ced541b 100644 ---- a/tests/kmstest/Makefile.am -+++ b/tests/kmstest/Makefile.am -@@ -17,9 +17,9 @@ kmstest_SOURCES = \ - main.c - - kmstest_LDADD = \ -- $(top_builddir)/libdrm.la \ -+ $(top_builddir)/tests/util/libutil.la \ - $(top_builddir)/libkms/libkms.la \ -- $(top_builddir)/tests/util/libutil.la -+ $(top_builddir)/libdrm.la - - run: kmstest - ./kmstest --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0019-vc4-Add-the-DRM-header-file.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0019-vc4-Add-the-DRM-header-file.patch deleted file mode 100644 index b87d376d..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0019-vc4-Add-the-DRM-header-file.patch +++ /dev/null @@ -1,316 +0,0 @@ -From eeb23de23bf2c0aeff4e36b0513ea13ac09c0438 Mon Sep 17 00:00:00 2001 -From: Eric Anholt <eric@anholt.net> -Date: Fri, 22 Jan 2016 16:34:14 -0800 -Subject: [PATCH 019/117] vc4: Add the DRM header file. - -I'll build some libdrm C code soon, but for now this lets libdrm users -use vc4 ioctls. Produced from headers_install of -1df59b8497f47495e873c23abd6d3d290c730505 (drm-next) in the kernel. - -Signed-off-by: Eric Anholt <eric@anholt.net> ---- - Makefile.sources | 1 + - include/drm/vc4_drm.h | 279 ++++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 280 insertions(+) - create mode 100644 include/drm/vc4_drm.h - -diff --git a/Makefile.sources b/Makefile.sources -index a77f48d..1a1f0fe 100644 ---- a/Makefile.sources -+++ b/Makefile.sources -@@ -32,6 +32,7 @@ LIBDRM_INCLUDE_H_FILES := \ - include/drm/savage_drm.h \ - include/drm/sis_drm.h \ - include/drm/tegra_drm.h \ -+ include/drm/vc4_drm.h \ - include/drm/via_drm.h - - LIBDRM_INCLUDE_VMWGFX_H_FILES := \ -diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h -new file mode 100644 -index 0000000..da3caa0 ---- /dev/null -+++ b/include/drm/vc4_drm.h -@@ -0,0 +1,279 @@ -+/* -+ * Copyright © 2014-2015 Broadcom -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+ * IN THE SOFTWARE. -+ */ -+ -+#ifndef _VC4_DRM_H_ -+#define _VC4_DRM_H_ -+ -+#include "drm.h" -+ -+#define DRM_VC4_SUBMIT_CL 0x00 -+#define DRM_VC4_WAIT_SEQNO 0x01 -+#define DRM_VC4_WAIT_BO 0x02 -+#define DRM_VC4_CREATE_BO 0x03 -+#define DRM_VC4_MMAP_BO 0x04 -+#define DRM_VC4_CREATE_SHADER_BO 0x05 -+#define DRM_VC4_GET_HANG_STATE 0x06 -+ -+#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) -+#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) -+#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) -+#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) -+#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) -+#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) -+#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) -+ -+struct drm_vc4_submit_rcl_surface { -+ __u32 hindex; /* Handle index, or ~0 if not present. */ -+ __u32 offset; /* Offset to start of buffer. */ -+ /* -+ * Bits for either render config (color_write) or load/store packet. -+ * Bits should all be 0 for MSAA load/stores. -+ */ -+ __u16 bits; -+ -+#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) -+ __u16 flags; -+}; -+ -+/** -+ * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D -+ * engine. -+ * -+ * Drivers typically use GPU BOs to store batchbuffers / command lists and -+ * their associated state. However, because the VC4 lacks an MMU, we have to -+ * do validation of memory accesses by the GPU commands. If we were to store -+ * our commands in BOs, we'd need to do uncached readback from them to do the -+ * validation process, which is too expensive. Instead, userspace accumulates -+ * commands and associated state in plain memory, then the kernel copies the -+ * data to its own address space, and then validates and stores it in a GPU -+ * BO. -+ */ -+struct drm_vc4_submit_cl { -+ /* Pointer to the binner command list. -+ * -+ * This is the first set of commands executed, which runs the -+ * coordinate shader to determine where primitives land on the screen, -+ * then writes out the state updates and draw calls necessary per tile -+ * to the tile allocation BO. -+ */ -+ __u64 bin_cl; -+ -+ /* Pointer to the shader records. -+ * -+ * Shader records are the structures read by the hardware that contain -+ * pointers to uniforms, shaders, and vertex attributes. The -+ * reference to the shader record has enough information to determine -+ * how many pointers are necessary (fixed number for shaders/uniforms, -+ * and an attribute count), so those BO indices into bo_handles are -+ * just stored as __u32s before each shader record passed in. -+ */ -+ __u64 shader_rec; -+ -+ /* Pointer to uniform data and texture handles for the textures -+ * referenced by the shader. -+ * -+ * For each shader state record, there is a set of uniform data in the -+ * order referenced by the record (FS, VS, then CS). Each set of -+ * uniform data has a __u32 index into bo_handles per texture -+ * sample operation, in the order the QPU_W_TMUn_S writes appear in -+ * the program. Following the texture BO handle indices is the actual -+ * uniform data. -+ * -+ * The individual uniform state blocks don't have sizes passed in, -+ * because the kernel has to determine the sizes anyway during shader -+ * code validation. -+ */ -+ __u64 uniforms; -+ __u64 bo_handles; -+ -+ /* Size in bytes of the binner command list. */ -+ __u32 bin_cl_size; -+ /* Size in bytes of the set of shader records. */ -+ __u32 shader_rec_size; -+ /* Number of shader records. -+ * -+ * This could just be computed from the contents of shader_records and -+ * the address bits of references to them from the bin CL, but it -+ * keeps the kernel from having to resize some allocations it makes. -+ */ -+ __u32 shader_rec_count; -+ /* Size in bytes of the uniform state. */ -+ __u32 uniforms_size; -+ -+ /* Number of BO handles passed in (size is that times 4). */ -+ __u32 bo_handle_count; -+ -+ /* RCL setup: */ -+ __u16 width; -+ __u16 height; -+ __u8 min_x_tile; -+ __u8 min_y_tile; -+ __u8 max_x_tile; -+ __u8 max_y_tile; -+ struct drm_vc4_submit_rcl_surface color_read; -+ struct drm_vc4_submit_rcl_surface color_write; -+ struct drm_vc4_submit_rcl_surface zs_read; -+ struct drm_vc4_submit_rcl_surface zs_write; -+ struct drm_vc4_submit_rcl_surface msaa_color_write; -+ struct drm_vc4_submit_rcl_surface msaa_zs_write; -+ __u32 clear_color[2]; -+ __u32 clear_z; -+ __u8 clear_s; -+ -+ __u32 pad:24; -+ -+#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) -+ __u32 flags; -+ -+ /* Returned value of the seqno of this render job (for the -+ * wait ioctl). -+ */ -+ __u64 seqno; -+}; -+ -+/** -+ * struct drm_vc4_wait_seqno - ioctl argument for waiting for -+ * DRM_VC4_SUBMIT_CL completion using its returned seqno. -+ * -+ * timeout_ns is the timeout in nanoseconds, where "0" means "don't -+ * block, just return the status." -+ */ -+struct drm_vc4_wait_seqno { -+ __u64 seqno; -+ __u64 timeout_ns; -+}; -+ -+/** -+ * struct drm_vc4_wait_bo - ioctl argument for waiting for -+ * completion of the last DRM_VC4_SUBMIT_CL on a BO. -+ * -+ * This is useful for cases where multiple processes might be -+ * rendering to a BO and you want to wait for all rendering to be -+ * completed. -+ */ -+struct drm_vc4_wait_bo { -+ __u32 handle; -+ __u32 pad; -+ __u64 timeout_ns; -+}; -+ -+/** -+ * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. -+ * -+ * There are currently no values for the flags argument, but it may be -+ * used in a future extension. -+ */ -+struct drm_vc4_create_bo { -+ __u32 size; -+ __u32 flags; -+ /** Returned GEM handle for the BO. */ -+ __u32 handle; -+ __u32 pad; -+}; -+ -+/** -+ * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. -+ * -+ * This doesn't actually perform an mmap. Instead, it returns the -+ * offset you need to use in an mmap on the DRM device node. This -+ * means that tools like valgrind end up knowing about the mapped -+ * memory. -+ * -+ * There are currently no values for the flags argument, but it may be -+ * used in a future extension. -+ */ -+struct drm_vc4_mmap_bo { -+ /** Handle for the object being mapped. */ -+ __u32 handle; -+ __u32 flags; -+ /** offset into the drm node to use for subsequent mmap call. */ -+ __u64 offset; -+}; -+ -+/** -+ * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 -+ * shader BOs. -+ * -+ * Since allowing a shader to be overwritten while it's also being -+ * executed from would allow privlege escalation, shaders must be -+ * created using this ioctl, and they can't be mmapped later. -+ */ -+struct drm_vc4_create_shader_bo { -+ /* Size of the data argument. */ -+ __u32 size; -+ /* Flags, currently must be 0. */ -+ __u32 flags; -+ -+ /* Pointer to the data. */ -+ __u64 data; -+ -+ /** Returned GEM handle for the BO. */ -+ __u32 handle; -+ /* Pad, must be 0. */ -+ __u32 pad; -+}; -+ -+struct drm_vc4_get_hang_state_bo { -+ __u32 handle; -+ __u32 paddr; -+ __u32 size; -+ __u32 pad; -+}; -+ -+/** -+ * struct drm_vc4_hang_state - ioctl argument for collecting state -+ * from a GPU hang for analysis. -+*/ -+struct drm_vc4_get_hang_state { -+ /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ -+ __u64 bo; -+ /** -+ * On input, the size of the bo array. Output is the number -+ * of bos to be returned. -+ */ -+ __u32 bo_count; -+ -+ __u32 start_bin, start_render; -+ -+ __u32 ct0ca, ct0ea; -+ __u32 ct1ca, ct1ea; -+ __u32 ct0cs, ct1cs; -+ __u32 ct0ra0, ct1ra0; -+ -+ __u32 bpca, bpcs; -+ __u32 bpoa, bpos; -+ -+ __u32 vpmbase; -+ -+ __u32 dbge; -+ __u32 fdbgo; -+ __u32 fdbgb; -+ __u32 fdbgr; -+ __u32 fdbgs; -+ __u32 errstat; -+ -+ /* Pad that we may save more registers into in the future. */ -+ __u32 pad[16]; -+}; -+ -+#endif /* _VC4_DRM_H_ */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0020-util-Add-support-for-vc4.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0020-util-Add-support-for-vc4.patch deleted file mode 100644 index 4f5473e2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0020-util-Add-support-for-vc4.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 0ad32e7ff48e106d654acca79445389651ed6909 Mon Sep 17 00:00:00 2001 -From: Eric Anholt <eric@anholt.net> -Date: Fri, 22 Jan 2016 16:37:25 -0800 -Subject: [PATCH 020/117] util: Add support for vc4. - -This lets allows using modetest for overlay plane testing. - -Signed-off-by: Eric Anholt <eric@anholt.net> ---- - tests/util/kms.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/tests/util/kms.c b/tests/util/kms.c -index dcd5a8e..ce8aaab 100644 ---- a/tests/util/kms.c -+++ b/tests/util/kms.c -@@ -140,6 +140,7 @@ static const char * const modules[] = { - "rockchip", - "atmel-hlcdc", - "fsl-dcu-drm", -+ "vc4", - }; - - int util_open(const char *device, const char *module) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch deleted file mode 100644 index 3b6181fe..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch +++ /dev/null @@ -1,870 +0,0 @@ -From 3c717f61f885240980bfc4273dbd1fc837edc391 Mon Sep 17 00:00:00 2001 -From: Eric Anholt <eric@anholt.net> -Date: Mon, 25 Jan 2016 10:16:56 -0800 -Subject: [PATCH 021/117] vc4: Add headers and .pc files for VC4 userspace - development. - -The headers were originally written in Mesa, imported to the kernel, -and improved upon in vc4-gpu-tools. These come from the v-g-t copies -and will replace the Mesa and v-g-t copies, and hopefully be used from -new tests in igt, as well. - -v2: Fix linking against libdrm_intel instead of libdrm. -v3: Drop Libs and Cflags since they'll be inherited from libdrm. -v4: Switch to Requires.private. I was wrong about standard practice, - apparently only Intel was doing plain Requires (sorry to all - involved). - -Signed-off-by: Eric Anholt <eric@anholt.net> ---- - Makefile.am | 6 + - configure.ac | 19 +++ - vc4/Makefile.am | 34 +++++ - vc4/Makefile.sources | 3 + - vc4/libdrm_vc4.pc.in | 9 ++ - vc4/vc4_packet.h | 397 ++++++++++++++++++++++++++++++++++++++++++++++++++ - vc4/vc4_qpu_defines.h | 274 ++++++++++++++++++++++++++++++++++ - 7 files changed, 742 insertions(+) - create mode 100644 vc4/Makefile.am - create mode 100644 vc4/Makefile.sources - create mode 100644 vc4/libdrm_vc4.pc.in - create mode 100644 vc4/vc4_packet.h - create mode 100644 vc4/vc4_qpu_defines.h - -diff --git a/Makefile.am b/Makefile.am -index ca41508..feecba7 100644 ---- a/Makefile.am -+++ b/Makefile.am -@@ -29,6 +29,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \ - --enable-radeon \ - --enable-amdgpu \ - --enable-nouveau \ -+ --enable-vc4 \ - --enable-vmwgfx \ - --enable-omap-experimental-api \ - --enable-exynos-experimental-api \ -@@ -79,6 +80,10 @@ if HAVE_TEGRA - TEGRA_SUBDIR = tegra - endif - -+if HAVE_VC4 -+VC4_SUBDIR = vc4 -+endif -+ - if BUILD_MANPAGES - if HAVE_MANPAGES_STYLESHEET - MAN_SUBDIR = man -@@ -96,6 +101,7 @@ SUBDIRS = \ - $(EXYNOS_SUBDIR) \ - $(FREEDRENO_SUBDIR) \ - $(TEGRA_SUBDIR) \ -+ $(VC4_SUBDIR) \ - tests \ - $(MAN_SUBDIR) - -diff --git a/configure.ac b/configure.ac -index 4635d18..4eeebfb 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -126,6 +126,11 @@ AC_ARG_ENABLE(tegra-experimental-api, - [Enable support for Tegra's experimental API (default: disabled)]), - [TEGRA=$enableval], [TEGRA=no]) - -+AC_ARG_ENABLE(vc4, -+ AS_HELP_STRING([--disable-vc4], -+ [Enable support for vc4's API (default: auto, enabled on arm)]), -+ [VC4=$enableval], [VC4=auto]) -+ - AC_ARG_ENABLE(install-test-programs, - AS_HELP_STRING([--enable-install-test-programs], - [Install test programs (default: no)]), -@@ -290,6 +295,12 @@ else - *) FREEDRENO=no ;; - esac - fi -+ if test "x$VC4" = xauto; then -+ case $host_cpu in -+ arm*|aarch64) VC4=yes ;; -+ *) VC4=no ;; -+ esac -+ fi - fi - - if test "x$INTEL" != "xno"; then -@@ -396,6 +407,11 @@ if test "x$TEGRA" = xyes; then - AC_DEFINE(HAVE_TEGRA, 1, [Have Tegra support]) - fi - -+AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes]) -+if test "x$VC4" = xyes; then -+ AC_DEFINE(HAVE_VC4, 1, [Have VC4 support]) -+fi -+ - AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes]) - if test "x$INSTALL_TESTS" = xyes; then - AC_DEFINE(HAVE_INSTALL_TESTS, 1, [Install test programs]) -@@ -505,6 +521,8 @@ AC_CONFIG_FILES([ - freedreno/libdrm_freedreno.pc - tegra/Makefile - tegra/libdrm_tegra.pc -+ vc4/Makefile -+ vc4/libdrm_vc4.pc - tests/Makefile - tests/modeprint/Makefile - tests/modetest/Makefile -@@ -535,4 +553,5 @@ echo " OMAP API $OMAP" - echo " EXYNOS API $EXYNOS" - echo " Freedreno API $FREEDRENO (kgsl: $FREEDRENO_KGSL)" - echo " Tegra API $TEGRA" -+echo " VC4 API $VC4" - echo "" -diff --git a/vc4/Makefile.am b/vc4/Makefile.am -new file mode 100644 -index 0000000..7e486b4 ---- /dev/null -+++ b/vc4/Makefile.am -@@ -0,0 +1,34 @@ -+# Copyright © 2016 Broadcom -+# -+# Permission is hereby granted, free of charge, to any person obtaining a -+# copy of this software and associated documentation files (the "Software"), -+# to deal in the Software without restriction, including without limitation -+# the rights to use, copy, modify, merge, publish, distribute, sublicense, -+# and/or sell copies of the Software, and to permit persons to whom the -+# Software is furnished to do so, subject to the following conditions: -+# -+# The above copyright notice and this permission notice (including the next -+# paragraph) shall be included in all copies or substantial portions of the -+# Software. -+# -+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+# IN THE SOFTWARE. -+ -+include Makefile.sources -+ -+AM_CFLAGS = \ -+ $(WARN_CFLAGS) \ -+ -I$(top_srcdir) \ -+ $(PTHREADSTUBS_CFLAGS) \ -+ $(VALGRIND_CFLAGS) \ -+ -I$(top_srcdir)/include/drm -+ -+libdrm_vc4includedir = ${includedir}/libdrm -+libdrm_vc4include_HEADERS = $(LIBDRM_VC4_H_FILES) -+ -+pkgconfig_DATA = libdrm_vc4.pc -diff --git a/vc4/Makefile.sources b/vc4/Makefile.sources -new file mode 100644 -index 0000000..8bf97ff ---- /dev/null -+++ b/vc4/Makefile.sources -@@ -0,0 +1,3 @@ -+LIBDRM_VC4_H_FILES := \ -+ vc4_packet.h \ -+ vc4_qpu_defines.h -diff --git a/vc4/libdrm_vc4.pc.in b/vc4/libdrm_vc4.pc.in -new file mode 100644 -index 0000000..a92678e ---- /dev/null -+++ b/vc4/libdrm_vc4.pc.in -@@ -0,0 +1,9 @@ -+prefix=@prefix@ -+exec_prefix=@exec_prefix@ -+libdir=@libdir@ -+includedir=@includedir@ -+ -+Name: libdrm_vc4 -+Description: Userspace interface to vc4 kernel DRM services -+Version: @PACKAGE_VERSION@ -+Requires.private: libdrm -diff --git a/vc4/vc4_packet.h b/vc4/vc4_packet.h -new file mode 100644 -index 0000000..e18e0bd ---- /dev/null -+++ b/vc4/vc4_packet.h -@@ -0,0 +1,397 @@ -+/* -+ * Copyright © 2014 Broadcom -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+ * IN THE SOFTWARE. -+ */ -+ -+#ifndef VC4_PACKET_H -+#define VC4_PACKET_H -+ -+enum vc4_packet { -+ VC4_PACKET_HALT = 0, -+ VC4_PACKET_NOP = 1, -+ -+ VC4_PACKET_FLUSH = 4, -+ VC4_PACKET_FLUSH_ALL = 5, -+ VC4_PACKET_START_TILE_BINNING = 6, -+ VC4_PACKET_INCREMENT_SEMAPHORE = 7, -+ VC4_PACKET_WAIT_ON_SEMAPHORE = 8, -+ -+ VC4_PACKET_BRANCH = 16, -+ VC4_PACKET_BRANCH_TO_SUB_LIST = 17, -+ VC4_PACKET_RETURN_FROM_SUB_LIST = 18, -+ -+ VC4_PACKET_STORE_MS_TILE_BUFFER = 24, -+ VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, -+ VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, -+ VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, -+ VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, -+ VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, -+ -+ VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, -+ VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, -+ -+ VC4_PACKET_COMPRESSED_PRIMITIVE = 48, -+ VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, -+ -+ VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, -+ -+ VC4_PACKET_GL_SHADER_STATE = 64, -+ VC4_PACKET_NV_SHADER_STATE = 65, -+ VC4_PACKET_VG_SHADER_STATE = 66, -+ -+ VC4_PACKET_CONFIGURATION_BITS = 96, -+ VC4_PACKET_FLAT_SHADE_FLAGS = 97, -+ VC4_PACKET_POINT_SIZE = 98, -+ VC4_PACKET_LINE_WIDTH = 99, -+ VC4_PACKET_RHT_X_BOUNDARY = 100, -+ VC4_PACKET_DEPTH_OFFSET = 101, -+ VC4_PACKET_CLIP_WINDOW = 102, -+ VC4_PACKET_VIEWPORT_OFFSET = 103, -+ VC4_PACKET_Z_CLIPPING = 104, -+ VC4_PACKET_CLIPPER_XY_SCALING = 105, -+ VC4_PACKET_CLIPPER_Z_SCALING = 106, -+ -+ VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, -+ VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, -+ VC4_PACKET_CLEAR_COLORS = 114, -+ VC4_PACKET_TILE_COORDINATES = 115, -+ -+ /* Not an actual hardware packet -- this is what we use to put -+ * references to GEM bos in the command stream, since we need the u32 -+ * int the actual address packet in order to store the offset from the -+ * start of the BO. -+ */ -+ VC4_PACKET_GEM_HANDLES = 254, -+} __attribute__ ((__packed__)); -+ -+#define VC4_PACKET_HALT_SIZE 1 -+#define VC4_PACKET_NOP_SIZE 1 -+#define VC4_PACKET_FLUSH_SIZE 1 -+#define VC4_PACKET_FLUSH_ALL_SIZE 1 -+#define VC4_PACKET_START_TILE_BINNING_SIZE 1 -+#define VC4_PACKET_INCREMENT_SEMAPHORE_SIZE 1 -+#define VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE 1 -+#define VC4_PACKET_BRANCH_SIZE 5 -+#define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE 5 -+#define VC4_PACKET_RETURN_FROM_SUB_LIST_SIZE 1 -+#define VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE 1 -+#define VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE 1 -+#define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE 5 -+#define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE 5 -+#define VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE 7 -+#define VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE 7 -+#define VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE 14 -+#define VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE 10 -+#define VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE 1 -+#define VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE 1 -+#define VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE 2 -+#define VC4_PACKET_GL_SHADER_STATE_SIZE 5 -+#define VC4_PACKET_NV_SHADER_STATE_SIZE 5 -+#define VC4_PACKET_VG_SHADER_STATE_SIZE 5 -+#define VC4_PACKET_CONFIGURATION_BITS_SIZE 4 -+#define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE 5 -+#define VC4_PACKET_POINT_SIZE_SIZE 5 -+#define VC4_PACKET_LINE_WIDTH_SIZE 5 -+#define VC4_PACKET_RHT_X_BOUNDARY_SIZE 3 -+#define VC4_PACKET_DEPTH_OFFSET_SIZE 5 -+#define VC4_PACKET_CLIP_WINDOW_SIZE 9 -+#define VC4_PACKET_VIEWPORT_OFFSET_SIZE 5 -+#define VC4_PACKET_Z_CLIPPING_SIZE 9 -+#define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9 -+#define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9 -+#define VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE 16 -+#define VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE 11 -+#define VC4_PACKET_CLEAR_COLORS_SIZE 14 -+#define VC4_PACKET_TILE_COORDINATES_SIZE 3 -+#define VC4_PACKET_GEM_HANDLES_SIZE 9 -+ -+#define VC4_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) -+/* Using the GNU statement expression extension */ -+#define VC4_SET_FIELD(value, field) \ -+ ({ \ -+ uint32_t fieldval = (value) << field ## _SHIFT; \ -+ assert((fieldval & ~ field ## _MASK) == 0); \ -+ fieldval & field ## _MASK; \ -+ }) -+ -+#define VC4_GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) -+ -+/** @{ -+ * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and -+ * VC4_PACKET_TILE_RENDERING_MODE_CONFIG. -+*/ -+#define VC4_TILING_FORMAT_LINEAR 0 -+#define VC4_TILING_FORMAT_T 1 -+#define VC4_TILING_FORMAT_LT 2 -+/** @} */ -+ -+/** @{ -+ * -+ * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and -+ * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. -+ */ -+#define VC4_LOADSTORE_FULL_RES_EOF (1 << 3) -+#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2) -+#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1) -+#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0) -+ -+/** @{ -+ * -+ * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and -+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address) -+ */ -+ -+#define VC4_LOADSTORE_TILE_BUFFER_EOF (1 << 3) -+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2) -+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS (1 << 1) -+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR (1 << 0) -+ -+/** @} */ -+ -+/** @{ -+ * -+ * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and -+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL -+ */ -+#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15) -+#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 14) -+#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 13) -+#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 12) -+ -+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8) -+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8 -+#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888 0 -+#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER 1 -+#define VC4_LOADSTORE_TILE_BUFFER_BGR565 2 -+/** @} */ -+ -+/** @{ -+ * -+ * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and -+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL -+ */ -+#define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6) -+#define VC4_STORE_TILE_BUFFER_MODE_SHIFT 6 -+#define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0 (0 << 6) -+#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4 (1 << 6) -+#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16 (2 << 6) -+ -+/** The values of the field are VC4_TILING_FORMAT_* */ -+#define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4) -+#define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT 4 -+ -+#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0) -+#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT 0 -+#define VC4_LOADSTORE_TILE_BUFFER_NONE 0 -+#define VC4_LOADSTORE_TILE_BUFFER_COLOR 1 -+#define VC4_LOADSTORE_TILE_BUFFER_ZS 2 -+#define VC4_LOADSTORE_TILE_BUFFER_Z 3 -+#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK 4 -+#define VC4_LOADSTORE_TILE_BUFFER_FULL 5 -+/** @} */ -+ -+#define VC4_INDEX_BUFFER_U8 (0 << 4) -+#define VC4_INDEX_BUFFER_U16 (1 << 4) -+ -+/* This flag is only present in NV shader state. */ -+#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS (1 << 3) -+#define VC4_SHADER_FLAG_ENABLE_CLIPPING (1 << 2) -+#define VC4_SHADER_FLAG_VS_POINT_SIZE (1 << 1) -+#define VC4_SHADER_FLAG_FS_SINGLE_THREAD (1 << 0) -+ -+/** @{ byte 2 of config bits. */ -+#define VC4_CONFIG_BITS_EARLY_Z_UPDATE (1 << 1) -+#define VC4_CONFIG_BITS_EARLY_Z (1 << 0) -+/** @} */ -+ -+/** @{ byte 1 of config bits. */ -+#define VC4_CONFIG_BITS_Z_UPDATE (1 << 7) -+/** same values in this 3-bit field as PIPE_FUNC_* */ -+#define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT 4 -+#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE (1 << 3) -+ -+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO (0 << 1) -+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD (1 << 1) -+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR (2 << 1) -+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO (3 << 1) -+ -+#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT (1 << 0) -+/** @} */ -+ -+/** @{ byte 0 of config bits. */ -+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6) -+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X (1 << 6) -+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X (2 << 6) -+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_MASK (3 << 6) -+ -+#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES (1 << 4) -+#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET (1 << 3) -+#define VC4_CONFIG_BITS_CW_PRIMITIVES (1 << 2) -+#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK (1 << 1) -+#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT (1 << 0) -+/** @} */ -+ -+/** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */ -+#define VC4_BIN_CONFIG_DB_NON_MS (1 << 7) -+ -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5) -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT 5 -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 0 -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64 1 -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128 2 -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256 3 -+ -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3) -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT 3 -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32 0 -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64 1 -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128 2 -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256 3 -+ -+#define VC4_BIN_CONFIG_AUTO_INIT_TSDA (1 << 2) -+#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT (1 << 1) -+#define VC4_BIN_CONFIG_MS_MODE_4X (1 << 0) -+/** @} */ -+ -+/** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */ -+#define VC4_RENDER_CONFIG_DB_NON_MS (1 << 12) -+#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11) -+#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G (1 << 10) -+#define VC4_RENDER_CONFIG_COVERAGE_MODE (1 << 9) -+#define VC4_RENDER_CONFIG_ENABLE_VG_MASK (1 << 8) -+ -+/** The values of the field are VC4_TILING_FORMAT_* */ -+#define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6) -+#define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT 6 -+ -+#define VC4_RENDER_CONFIG_DECIMATE_MODE_1X (0 << 4) -+#define VC4_RENDER_CONFIG_DECIMATE_MODE_4X (1 << 4) -+#define VC4_RENDER_CONFIG_DECIMATE_MODE_16X (2 << 4) -+#define VC4_RENDER_CONFIG_DECIMATE_MODE_MASK (3 << 4) -+ -+#define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2) -+#define VC4_RENDER_CONFIG_FORMAT_SHIFT 2 -+#define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED 0 -+#define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1 -+#define VC4_RENDER_CONFIG_FORMAT_BGR565 2 -+ -+#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT (1 << 1) -+#define VC4_RENDER_CONFIG_MS_MODE_4X (1 << 0) -+ -+#define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX (1 << 4) -+#define VC4_PRIMITIVE_LIST_FORMAT_32_XY (3 << 4) -+#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS (0 << 0) -+#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES (1 << 0) -+#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES (2 << 0) -+#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT (3 << 0) -+ -+enum vc4_texture_data_type { -+ VC4_TEXTURE_TYPE_RGBA8888 = 0, -+ VC4_TEXTURE_TYPE_RGBX8888 = 1, -+ VC4_TEXTURE_TYPE_RGBA4444 = 2, -+ VC4_TEXTURE_TYPE_RGBA5551 = 3, -+ VC4_TEXTURE_TYPE_RGB565 = 4, -+ VC4_TEXTURE_TYPE_LUMINANCE = 5, -+ VC4_TEXTURE_TYPE_ALPHA = 6, -+ VC4_TEXTURE_TYPE_LUMALPHA = 7, -+ VC4_TEXTURE_TYPE_ETC1 = 8, -+ VC4_TEXTURE_TYPE_S16F = 9, -+ VC4_TEXTURE_TYPE_S8 = 10, -+ VC4_TEXTURE_TYPE_S16 = 11, -+ VC4_TEXTURE_TYPE_BW1 = 12, -+ VC4_TEXTURE_TYPE_A4 = 13, -+ VC4_TEXTURE_TYPE_A1 = 14, -+ VC4_TEXTURE_TYPE_RGBA64 = 15, -+ VC4_TEXTURE_TYPE_RGBA32R = 16, -+ VC4_TEXTURE_TYPE_YUV422R = 17, -+}; -+ -+#define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12) -+#define VC4_TEX_P0_OFFSET_SHIFT 12 -+#define VC4_TEX_P0_CSWIZ_MASK VC4_MASK(11, 10) -+#define VC4_TEX_P0_CSWIZ_SHIFT 10 -+#define VC4_TEX_P0_CMMODE_MASK VC4_MASK(9, 9) -+#define VC4_TEX_P0_CMMODE_SHIFT 9 -+#define VC4_TEX_P0_FLIPY_MASK VC4_MASK(8, 8) -+#define VC4_TEX_P0_FLIPY_SHIFT 8 -+#define VC4_TEX_P0_TYPE_MASK VC4_MASK(7, 4) -+#define VC4_TEX_P0_TYPE_SHIFT 4 -+#define VC4_TEX_P0_MIPLVLS_MASK VC4_MASK(3, 0) -+#define VC4_TEX_P0_MIPLVLS_SHIFT 0 -+ -+#define VC4_TEX_P1_TYPE4_MASK VC4_MASK(31, 31) -+#define VC4_TEX_P1_TYPE4_SHIFT 31 -+#define VC4_TEX_P1_HEIGHT_MASK VC4_MASK(30, 20) -+#define VC4_TEX_P1_HEIGHT_SHIFT 20 -+#define VC4_TEX_P1_ETCFLIP_MASK VC4_MASK(19, 19) -+#define VC4_TEX_P1_ETCFLIP_SHIFT 19 -+#define VC4_TEX_P1_WIDTH_MASK VC4_MASK(18, 8) -+#define VC4_TEX_P1_WIDTH_SHIFT 8 -+ -+#define VC4_TEX_P1_MAGFILT_MASK VC4_MASK(7, 7) -+#define VC4_TEX_P1_MAGFILT_SHIFT 7 -+# define VC4_TEX_P1_MAGFILT_LINEAR 0 -+# define VC4_TEX_P1_MAGFILT_NEAREST 1 -+ -+#define VC4_TEX_P1_MINFILT_MASK VC4_MASK(6, 4) -+#define VC4_TEX_P1_MINFILT_SHIFT 4 -+# define VC4_TEX_P1_MINFILT_LINEAR 0 -+# define VC4_TEX_P1_MINFILT_NEAREST 1 -+# define VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR 2 -+# define VC4_TEX_P1_MINFILT_NEAR_MIP_LIN 3 -+# define VC4_TEX_P1_MINFILT_LIN_MIP_NEAR 4 -+# define VC4_TEX_P1_MINFILT_LIN_MIP_LIN 5 -+ -+#define VC4_TEX_P1_WRAP_T_MASK VC4_MASK(3, 2) -+#define VC4_TEX_P1_WRAP_T_SHIFT 2 -+#define VC4_TEX_P1_WRAP_S_MASK VC4_MASK(1, 0) -+#define VC4_TEX_P1_WRAP_S_SHIFT 0 -+# define VC4_TEX_P1_WRAP_REPEAT 0 -+# define VC4_TEX_P1_WRAP_CLAMP 1 -+# define VC4_TEX_P1_WRAP_MIRROR 2 -+# define VC4_TEX_P1_WRAP_BORDER 3 -+ -+#define VC4_TEX_P2_PTYPE_MASK VC4_MASK(31, 30) -+#define VC4_TEX_P2_PTYPE_SHIFT 30 -+# define VC4_TEX_P2_PTYPE_IGNORED 0 -+# define VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE 1 -+# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS 2 -+# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS 3 -+ -+/* VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE bits */ -+#define VC4_TEX_P2_CMST_MASK VC4_MASK(29, 12) -+#define VC4_TEX_P2_CMST_SHIFT 12 -+#define VC4_TEX_P2_BSLOD_MASK VC4_MASK(0, 0) -+#define VC4_TEX_P2_BSLOD_SHIFT 0 -+ -+/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS */ -+#define VC4_TEX_P2_CHEIGHT_MASK VC4_MASK(22, 12) -+#define VC4_TEX_P2_CHEIGHT_SHIFT 12 -+#define VC4_TEX_P2_CWIDTH_MASK VC4_MASK(10, 0) -+#define VC4_TEX_P2_CWIDTH_SHIFT 0 -+ -+/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS */ -+#define VC4_TEX_P2_CYOFF_MASK VC4_MASK(22, 12) -+#define VC4_TEX_P2_CYOFF_SHIFT 12 -+#define VC4_TEX_P2_CXOFF_MASK VC4_MASK(10, 0) -+#define VC4_TEX_P2_CXOFF_SHIFT 0 -+ -+#endif /* VC4_PACKET_H */ -diff --git a/vc4/vc4_qpu_defines.h b/vc4/vc4_qpu_defines.h -new file mode 100644 -index 0000000..26fcf50 ---- /dev/null -+++ b/vc4/vc4_qpu_defines.h -@@ -0,0 +1,274 @@ -+/* -+ * Copyright © 2014 Broadcom -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+ * IN THE SOFTWARE. -+ */ -+ -+#ifndef VC4_QPU_DEFINES_H -+#define VC4_QPU_DEFINES_H -+ -+enum qpu_op_add { -+ QPU_A_NOP, -+ QPU_A_FADD, -+ QPU_A_FSUB, -+ QPU_A_FMIN, -+ QPU_A_FMAX, -+ QPU_A_FMINABS, -+ QPU_A_FMAXABS, -+ QPU_A_FTOI, -+ QPU_A_ITOF, -+ QPU_A_ADD = 12, -+ QPU_A_SUB, -+ QPU_A_SHR, -+ QPU_A_ASR, -+ QPU_A_ROR, -+ QPU_A_SHL, -+ QPU_A_MIN, -+ QPU_A_MAX, -+ QPU_A_AND, -+ QPU_A_OR, -+ QPU_A_XOR, -+ QPU_A_NOT, -+ QPU_A_CLZ, -+ QPU_A_V8ADDS = 30, -+ QPU_A_V8SUBS = 31, -+}; -+ -+enum qpu_op_mul { -+ QPU_M_NOP, -+ QPU_M_FMUL, -+ QPU_M_MUL24, -+ QPU_M_V8MULD, -+ QPU_M_V8MIN, -+ QPU_M_V8MAX, -+ QPU_M_V8ADDS, -+ QPU_M_V8SUBS, -+}; -+ -+enum qpu_raddr { -+ QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */ -+ /* 0-31 are the plain regfile a or b fields */ -+ QPU_R_UNIF = 32, -+ QPU_R_VARY = 35, -+ QPU_R_ELEM_QPU = 38, -+ QPU_R_NOP, -+ QPU_R_XY_PIXEL_COORD = 41, -+ QPU_R_MS_REV_FLAGS = 42, -+ QPU_R_VPM = 48, -+ QPU_R_VPM_LD_BUSY, -+ QPU_R_VPM_LD_WAIT, -+ QPU_R_MUTEX_ACQUIRE, -+}; -+ -+enum qpu_waddr { -+ /* 0-31 are the plain regfile a or b fields */ -+ QPU_W_ACC0 = 32, /* aka r0 */ -+ QPU_W_ACC1, -+ QPU_W_ACC2, -+ QPU_W_ACC3, -+ QPU_W_TMU_NOSWAP, -+ QPU_W_ACC5, -+ QPU_W_HOST_INT, -+ QPU_W_NOP, -+ QPU_W_UNIFORMS_ADDRESS, -+ QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */ -+ QPU_W_MS_FLAGS = 42, -+ QPU_W_REV_FLAG = 42, -+ QPU_W_TLB_STENCIL_SETUP = 43, -+ QPU_W_TLB_Z, -+ QPU_W_TLB_COLOR_MS, -+ QPU_W_TLB_COLOR_ALL, -+ QPU_W_TLB_ALPHA_MASK, -+ QPU_W_VPM, -+ QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */ -+ QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */ -+ QPU_W_MUTEX_RELEASE, -+ QPU_W_SFU_RECIP, -+ QPU_W_SFU_RECIPSQRT, -+ QPU_W_SFU_EXP, -+ QPU_W_SFU_LOG, -+ QPU_W_TMU0_S, -+ QPU_W_TMU0_T, -+ QPU_W_TMU0_R, -+ QPU_W_TMU0_B, -+ QPU_W_TMU1_S, -+ QPU_W_TMU1_T, -+ QPU_W_TMU1_R, -+ QPU_W_TMU1_B, -+}; -+ -+enum qpu_sig_bits { -+ QPU_SIG_SW_BREAKPOINT, -+ QPU_SIG_NONE, -+ QPU_SIG_THREAD_SWITCH, -+ QPU_SIG_PROG_END, -+ QPU_SIG_WAIT_FOR_SCOREBOARD, -+ QPU_SIG_SCOREBOARD_UNLOCK, -+ QPU_SIG_LAST_THREAD_SWITCH, -+ QPU_SIG_COVERAGE_LOAD, -+ QPU_SIG_COLOR_LOAD, -+ QPU_SIG_COLOR_LOAD_END, -+ QPU_SIG_LOAD_TMU0, -+ QPU_SIG_LOAD_TMU1, -+ QPU_SIG_ALPHA_MASK_LOAD, -+ QPU_SIG_SMALL_IMM, -+ QPU_SIG_LOAD_IMM, -+ QPU_SIG_BRANCH -+}; -+ -+enum qpu_mux { -+ /* hardware mux values */ -+ QPU_MUX_R0, -+ QPU_MUX_R1, -+ QPU_MUX_R2, -+ QPU_MUX_R3, -+ QPU_MUX_R4, -+ QPU_MUX_R5, -+ QPU_MUX_A, -+ QPU_MUX_B, -+ -+ /** -+ * Non-hardware mux value, stores a small immediate field to be -+ * programmed into raddr_b in the qpu_reg.index. -+ */ -+ QPU_MUX_SMALL_IMM, -+}; -+ -+enum qpu_cond { -+ QPU_COND_NEVER, -+ QPU_COND_ALWAYS, -+ QPU_COND_ZS, -+ QPU_COND_ZC, -+ QPU_COND_NS, -+ QPU_COND_NC, -+ QPU_COND_CS, -+ QPU_COND_CC, -+}; -+ -+enum qpu_pack_mul { -+ QPU_PACK_MUL_NOP, -+ QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */ -+ QPU_PACK_MUL_8A, -+ QPU_PACK_MUL_8B, -+ QPU_PACK_MUL_8C, -+ QPU_PACK_MUL_8D, -+}; -+ -+enum qpu_pack_a { -+ QPU_PACK_A_NOP, -+ /* convert to 16 bit float if float input, or to int16. */ -+ QPU_PACK_A_16A, -+ QPU_PACK_A_16B, -+ /* replicated to each 8 bits of the 32-bit dst. */ -+ QPU_PACK_A_8888, -+ /* Convert to 8-bit unsigned int. */ -+ QPU_PACK_A_8A, -+ QPU_PACK_A_8B, -+ QPU_PACK_A_8C, -+ QPU_PACK_A_8D, -+ -+ /* Saturating variants of the previous instructions. */ -+ QPU_PACK_A_32_SAT, /* int-only */ -+ QPU_PACK_A_16A_SAT, /* int or float */ -+ QPU_PACK_A_16B_SAT, -+ QPU_PACK_A_8888_SAT, -+ QPU_PACK_A_8A_SAT, -+ QPU_PACK_A_8B_SAT, -+ QPU_PACK_A_8C_SAT, -+ QPU_PACK_A_8D_SAT, -+}; -+ -+enum qpu_unpack { -+ QPU_UNPACK_NOP, -+ QPU_UNPACK_16A, -+ QPU_UNPACK_16B, -+ QPU_UNPACK_8D_REP, -+ QPU_UNPACK_8A, -+ QPU_UNPACK_8B, -+ QPU_UNPACK_8C, -+ QPU_UNPACK_8D, -+}; -+ -+#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low)) -+/* Using the GNU statement expression extension */ -+#define QPU_SET_FIELD(value, field) \ -+ ({ \ -+ uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \ -+ assert((fieldval & ~ field ## _MASK) == 0); \ -+ fieldval & field ## _MASK; \ -+ }) -+ -+#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) -+ -+#define QPU_UPDATE_FIELD(inst, value, field) \ -+ (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field)) -+ -+#define QPU_SIG_SHIFT 60 -+#define QPU_SIG_MASK QPU_MASK(63, 60) -+ -+#define QPU_UNPACK_SHIFT 57 -+#define QPU_UNPACK_MASK QPU_MASK(59, 57) -+ -+/** -+ * If set, the pack field means PACK_MUL or R4 packing, instead of normal -+ * regfile a packing. -+ */ -+#define QPU_PM ((uint64_t)1 << 56) -+ -+#define QPU_PACK_SHIFT 52 -+#define QPU_PACK_MASK QPU_MASK(55, 52) -+ -+#define QPU_COND_ADD_SHIFT 49 -+#define QPU_COND_ADD_MASK QPU_MASK(51, 49) -+#define QPU_COND_MUL_SHIFT 46 -+#define QPU_COND_MUL_MASK QPU_MASK(48, 46) -+ -+#define QPU_SF ((uint64_t)1 << 45) -+ -+#define QPU_WADDR_ADD_SHIFT 38 -+#define QPU_WADDR_ADD_MASK QPU_MASK(43, 38) -+#define QPU_WADDR_MUL_SHIFT 32 -+#define QPU_WADDR_MUL_MASK QPU_MASK(37, 32) -+ -+#define QPU_OP_MUL_SHIFT 29 -+#define QPU_OP_MUL_MASK QPU_MASK(31, 29) -+ -+#define QPU_RADDR_A_SHIFT 18 -+#define QPU_RADDR_A_MASK QPU_MASK(23, 18) -+#define QPU_RADDR_B_SHIFT 12 -+#define QPU_RADDR_B_MASK QPU_MASK(17, 12) -+#define QPU_SMALL_IMM_SHIFT 12 -+#define QPU_SMALL_IMM_MASK QPU_MASK(17, 12) -+ -+#define QPU_ADD_A_SHIFT 9 -+#define QPU_ADD_A_MASK QPU_MASK(11, 9) -+#define QPU_ADD_B_SHIFT 6 -+#define QPU_ADD_B_MASK QPU_MASK(8, 6) -+#define QPU_MUL_A_SHIFT 3 -+#define QPU_MUL_A_MASK QPU_MASK(5, 3) -+#define QPU_MUL_B_SHIFT 0 -+#define QPU_MUL_B_MASK QPU_MASK(2, 0) -+ -+#define QPU_WS ((uint64_t)1 << 44) -+ -+#define QPU_OP_ADD_SHIFT 24 -+#define QPU_OP_ADD_MASK QPU_MASK(28, 24) -+ -+#endif /* VC4_QPU_DEFINES_H */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0022-amdgpu-add-libdrm-as-private-requirement-dependency.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0022-amdgpu-add-libdrm-as-private-requirement-dependency.patch deleted file mode 100644 index 7a7efb6e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0022-amdgpu-add-libdrm-as-private-requirement-dependency.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 87b3bf643de35223d9d038febc7d5e232325e7b2 Mon Sep 17 00:00:00 2001 -From: Emil Velikov <emil.l.velikov@gmail.com> -Date: Thu, 28 Jan 2016 11:26:24 +0000 -Subject: [PATCH 022/117] amdgpu: add libdrm as private requirement/dependency -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Otherwise libdrm.so won't end up in the --libs, when one static links -libdrm_amdgpu. - -Cc: Christian König <christian.koenig@amd.com> -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> ---- - amdgpu/libdrm_amdgpu.pc.in | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/amdgpu/libdrm_amdgpu.pc.in b/amdgpu/libdrm_amdgpu.pc.in -index 417865e..f1c552a 100644 ---- a/amdgpu/libdrm_amdgpu.pc.in -+++ b/amdgpu/libdrm_amdgpu.pc.in -@@ -8,3 +8,4 @@ Description: Userspace interface to kernel DRM services for amdgpu - Version: @PACKAGE_VERSION@ - Libs: -L${libdir} -ldrm_amdgpu - Cflags: -I${includedir} -I${includedir}/libdrm -+Requires.private: libdrm --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0023-radeon-add-libdrm-to-Requires.private.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0023-radeon-add-libdrm-to-Requires.private.patch deleted file mode 100644 index e8f750aa..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0023-radeon-add-libdrm-to-Requires.private.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 31badf031c90aba4609e1464e252311f96733a5e Mon Sep 17 00:00:00 2001 -From: Emil Velikov <emil.l.velikov@gmail.com> -Date: Thu, 28 Jan 2016 11:33:34 +0000 -Subject: [PATCH 023/117] radeon: add libdrm to Requires.private -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Equivalent to the amdgpu commit before. Additionally, when libdrm is -installed to a 'non-default' location, users of libdrm_radeon will fail -to build, as radeon_cs.h (and maybe others) won't have their -dependencies (drm.h radeon_drm.h) fulfilled. - -Cc: Christian König <christian.koenig@amd.com> -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> ---- - radeon/libdrm_radeon.pc.in | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/radeon/libdrm_radeon.pc.in b/radeon/libdrm_radeon.pc.in -index 68ef0ab..432993a 100644 ---- a/radeon/libdrm_radeon.pc.in -+++ b/radeon/libdrm_radeon.pc.in -@@ -8,3 +8,4 @@ Description: Userspace interface to kernel DRM services for radeon - Version: @PACKAGE_VERSION@ - Libs: -L${libdir} -ldrm_radeon - Cflags: -I${includedir} -I${includedir}/libdrm -+Requires.private: libdrm --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0024-libkms-add-libdrm-to-Requires.private.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0024-libkms-add-libdrm-to-Requires.private.patch deleted file mode 100644 index 9f3ee23b..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0024-libkms-add-libdrm-to-Requires.private.patch +++ /dev/null @@ -1,29 +0,0 @@ -From ca5017b69c43ef3bfada0abb77a82de1de345075 Mon Sep 17 00:00:00 2001 -From: Emil Velikov <emil.l.velikov@gmail.com> -Date: Thu, 28 Jan 2016 11:39:03 +0000 -Subject: [PATCH 024/117] libkms: add libdrm to Requires.private -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Analogous to last two changes (amdgpu and radeon). - -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> -Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> ---- - libkms/libkms.pc.in | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/libkms/libkms.pc.in b/libkms/libkms.pc.in -index 511535a..1421b3e 100644 ---- a/libkms/libkms.pc.in -+++ b/libkms/libkms.pc.in -@@ -8,3 +8,4 @@ Description: Library that abstract aways the different mm interface for kernel d - Version: 1.0.0 - Libs: -L${libdir} -lkms - Cflags: -I${includedir}/libkms -+Requires.private: libdrm --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0025-android-enable-building-static-version-of-libdrm.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0025-android-enable-building-static-version-of-libdrm.patch deleted file mode 100644 index 98c11e7b..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0025-android-enable-building-static-version-of-libdrm.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 682eaa05e6bc6b191b826e1c9db4446caea43c49 Mon Sep 17 00:00:00 2001 -From: Sumit Semwal <sumit.semwal@linaro.org> -Date: Fri, 29 Jan 2016 10:00:47 -0600 -Subject: [PATCH 025/117] android: enable building static version of libdrm - -Android needs libdrm built statically for recovery; -enable that as well. - -Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org> -Signed-off-by: Rob Herring <robh@kernel.org> -Cc: Chih-Wei Huang <cwhuang@linux.org.tw> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - Android.mk | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/Android.mk b/Android.mk -index 90cdcb3..1d8cd65 100644 ---- a/Android.mk -+++ b/Android.mk -@@ -27,6 +27,8 @@ include $(CLEAR_VARS) - # Import variables LIBDRM_{,H_,INCLUDE_H_,INCLUDE_VMWGFX_H_}FILES - include $(LOCAL_PATH)/Makefile.sources - -+#static library for the device (recovery) -+include $(CLEAR_VARS) - LOCAL_MODULE := libdrm - LOCAL_MODULE_TAGS := optional - -@@ -41,7 +43,24 @@ LOCAL_C_INCLUDES := \ - LOCAL_CFLAGS := \ - -DHAVE_VISIBILITY=1 \ - -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 -+include $(BUILD_STATIC_LIBRARY) -+ -+# Shared library for the device -+include $(CLEAR_VARS) -+LOCAL_MODULE := libdrm -+LOCAL_MODULE_TAGS := optional - -+LOCAL_SRC_FILES := $(LIBDRM_FILES) -+LOCAL_EXPORT_C_INCLUDE_DIRS := \ -+ $(LOCAL_PATH) \ -+ $(LOCAL_PATH)/include/drm -+ -+LOCAL_C_INCLUDES := \ -+ $(LOCAL_PATH)/include/drm -+ -+LOCAL_CFLAGS := \ -+ -DHAVE_VISIBILITY=1 \ -+ -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 - include $(BUILD_SHARED_LIBRARY) - - include $(call all-makefiles-under,$(LOCAL_PATH)) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch deleted file mode 100644 index 67dd46bc..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 30da7e6ac1682b5de547686369d1b8199c6929c3 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 19 Aug 2015 17:39:37 +0800 -Subject: [PATCH 026/117] amdgpu: add the interface of waiting multiple fences -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> ---- - amdgpu/amdgpu.h | 22 +++++++++++++++ - amdgpu/amdgpu_cs.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 27 ++++++++++++++++++ - 3 files changed, 121 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 0851306..8822a0c 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -907,6 +907,28 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - uint64_t flags, - uint32_t *expired); - -+/** -+ * Wait for multiple fences -+ * -+ * \param fences - \c [in] The fence array to wait -+ * \param fence_count - \c [in] The fence count -+ * \param wait_all - \c [in] If true, wait all fences to be signaled, -+ * otherwise, wait at least one fence -+ * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds -+ * \param status - \c [out] '1' for signaled, '0' for timeout -+ * -+ * \return 0 on success -+ * <0 - Negative POSIX Error code -+ * -+ * \note Currently it supports only one amdgpu_device. All fences come from -+ * the same amdgpu_device with the same fd. -+*/ -+int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, -+ uint32_t fence_count, -+ bool wait_all, -+ uint64_t timeout_ns, -+ uint32_t *status); -+ - /* - * Query / Info API - * -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index b4f41b0..896352b 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -435,6 +435,78 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - return r; - } - -+static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, -+ uint32_t fence_count, -+ bool wait_all, -+ uint64_t timeout_ns, -+ uint32_t *status) -+{ -+ struct drm_amdgpu_fence *drm_fences; -+ amdgpu_device_handle dev = fences[0].context->dev; -+ union drm_amdgpu_wait_fences args; -+ int r; -+ uint32_t i; -+ -+ drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count); -+ for (i = 0; i < fence_count; i++) { -+ drm_fences[i].ctx_id = fences[i].context->id; -+ drm_fences[i].ip_type = fences[i].ip_type; -+ drm_fences[i].ip_instance = fences[i].ip_instance; -+ drm_fences[i].ring = fences[i].ring; -+ drm_fences[i].seq_no = fences[i].fence; -+ } -+ -+ memset(&args, 0, sizeof(args)); -+ args.in.fences = (uint64_t)(uintptr_t)drm_fences; -+ args.in.fence_count = fence_count; -+ args.in.wait_all = wait_all; -+ args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns); -+ -+ r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, &args); -+ if (r) -+ return -errno; -+ -+ *status = args.out.status; -+ return 0; -+} -+ -+int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, -+ uint32_t fence_count, -+ bool wait_all, -+ uint64_t timeout_ns, -+ uint32_t *status) -+{ -+ uint32_t ioctl_status = 0; -+ uint32_t i; -+ int r; -+ -+ /* Sanity check */ -+ if (NULL == fences) -+ return -EINVAL; -+ if (NULL == status) -+ return -EINVAL; -+ if (fence_count <= 0) -+ return -EINVAL; -+ for (i = 0; i < fence_count; i++) { -+ if (NULL == fences[i].context) -+ return -EINVAL; -+ if (fences[i].ip_type >= AMDGPU_HW_IP_NUM) -+ return -EINVAL; -+ if (fences[i].ring >= AMDGPU_CS_MAX_RINGS) -+ return -EINVAL; -+ } -+ -+ *status = 0; -+ -+ r = amdgpu_ioctl_wait_fences(fences, fence_count, wait_all, timeout_ns, -+ &ioctl_status); -+ -+ if (!r) -+ *status = ioctl_status; -+ -+ return r; -+} -+ - int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) - { - struct amdgpu_semaphore *gpu_semaphore; -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index fbdd118..2cbea72 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -46,6 +46,7 @@ - #define DRM_AMDGPU_WAIT_CS 0x09 - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 -+#define DRM_AMDGPU_WAIT_FENCES 0x12 - - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) - #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -59,6 +60,7 @@ - #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) -+#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -297,6 +299,31 @@ union drm_amdgpu_wait_cs { - struct drm_amdgpu_wait_cs_out out; - }; - -+struct drm_amdgpu_fence { -+ uint32_t ctx_id; -+ uint32_t ip_type; -+ uint32_t ip_instance; -+ uint32_t ring; -+ uint64_t seq_no; -+}; -+ -+struct drm_amdgpu_wait_fences_in { -+ /** This points to uint64_t * which points to fences */ -+ uint64_t fences; -+ uint32_t fence_count; -+ uint32_t wait_all; -+ uint64_t timeout_ns; -+}; -+ -+struct drm_amdgpu_wait_fences_out { -+ uint64_t status; -+}; -+ -+union drm_amdgpu_wait_fences { -+ struct drm_amdgpu_wait_fences_in in; -+ struct drm_amdgpu_wait_fences_out out; -+}; -+ - #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 - #define AMDGPU_GEM_OP_SET_PLACEMENT 1 - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch deleted file mode 100644 index 11eddff2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch +++ /dev/null @@ -1,139 +0,0 @@ -From 41469768b0e55ae414aaf6b61b0d83f348518169 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Fri, 21 Aug 2015 10:14:48 +0800 -Subject: [PATCH 027/117] amdgpu/tests: add multi-fence test in base test - -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> ---- - tests/amdgpu/basic_tests.c | 100 +++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 100 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index fa0ed12..56db935 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -46,6 +46,7 @@ static void amdgpu_memory_alloc(void); - static void amdgpu_command_submission_gfx(void); - static void amdgpu_command_submission_compute(void); - static void amdgpu_command_submission_sdma(void); -+static void amdgpu_command_submission_multi_fence(void); - static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); - -@@ -56,6 +57,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, - { "Command submission Test (Compute)", amdgpu_command_submission_compute }, - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, -+ { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, - { "SW semaphore Test", amdgpu_semaphore_test }, - CU_TEST_INFO_NULL, - }; -@@ -898,6 +900,104 @@ static void amdgpu_command_submission_sdma(void) - amdgpu_command_submission_sdma_copy_linear(); - } - -+static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) -+{ -+ amdgpu_context_handle context_handle; -+ amdgpu_bo_handle ib_result_handle, ib_result_ce_handle; -+ void *ib_result_cpu, *ib_result_ce_cpu; -+ uint64_t ib_result_mc_address, ib_result_ce_mc_address; -+ struct amdgpu_cs_request ibs_request[2] = {0}; -+ struct amdgpu_cs_ib_info ib_info[2]; -+ struct amdgpu_cs_fence fence_status[2] = {0}; -+ uint32_t *ptr; -+ uint32_t expired; -+ amdgpu_bo_list_handle bo_list; -+ amdgpu_va_handle va_handle, va_handle_ce; -+ int r; -+ int i, ib_cs_num = 2; -+ -+ r = amdgpu_cs_ctx_create(device_handle, &context_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, -+ AMDGPU_GEM_DOMAIN_GTT, 0, -+ &ib_result_handle, &ib_result_cpu, -+ &ib_result_mc_address, &va_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, -+ AMDGPU_GEM_DOMAIN_GTT, 0, -+ &ib_result_ce_handle, &ib_result_ce_cpu, -+ &ib_result_ce_mc_address, &va_handle_ce); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, -+ ib_result_ce_handle, &bo_list); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info)); -+ -+ /* IT_SET_CE_DE_COUNTERS */ -+ ptr = ib_result_ce_cpu; -+ ptr[0] = 0xc0008900; -+ ptr[1] = 0; -+ ptr[2] = 0xc0008400; -+ ptr[3] = 1; -+ ib_info[0].ib_mc_address = ib_result_ce_mc_address; -+ ib_info[0].size = 4; -+ ib_info[0].flags = AMDGPU_IB_FLAG_CE; -+ -+ /* IT_WAIT_ON_CE_COUNTER */ -+ ptr = ib_result_cpu; -+ ptr[0] = 0xc0008600; -+ ptr[1] = 0x00000001; -+ ib_info[1].ib_mc_address = ib_result_mc_address; -+ ib_info[1].size = 2; -+ -+ for (i = 0; i < ib_cs_num; i++) { -+ ibs_request[i].ip_type = AMDGPU_HW_IP_GFX; -+ ibs_request[i].number_of_ibs = 2; -+ ibs_request[i].ibs = ib_info; -+ ibs_request[i].resources = bo_list; -+ ibs_request[i].fence_info.handle = NULL; -+ } -+ -+ r = amdgpu_cs_submit(context_handle, 0,ibs_request, ib_cs_num); -+ -+ CU_ASSERT_EQUAL(r, 0); -+ -+ for (i = 0; i < ib_cs_num; i++) { -+ fence_status[i].context = context_handle; -+ fence_status[i].ip_type = AMDGPU_HW_IP_GFX; -+ fence_status[i].fence = ibs_request[i].seq_no; -+ } -+ -+ r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all, -+ AMDGPU_TIMEOUT_INFINITE, -+ &expired); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, -+ ib_result_mc_address, 4096); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_unmap_and_free(ib_result_ce_handle, va_handle_ce, -+ ib_result_ce_mc_address, 4096); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_list_destroy(bo_list); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_cs_ctx_free(context_handle); -+ CU_ASSERT_EQUAL(r, 0); -+} -+ -+static void amdgpu_command_submission_multi_fence(void) -+{ -+ amdgpu_command_submission_multi_fence_wait_all(true); -+ amdgpu_command_submission_multi_fence_wait_all(false); -+} -+ - static void amdgpu_userptr_test(void) - { - int i, r, j; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0028-amdgpu-add-query-for-aperture-va-range.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0028-amdgpu-add-query-for-aperture-va-range.patch deleted file mode 100644 index 041f04e4..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0028-amdgpu-add-query-for-aperture-va-range.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 6699587911b702ad612ad0e942214186ca04c1c2 Mon Sep 17 00:00:00 2001 -From: Flora Cui <flora.cui@amd.com> -Date: Sat, 10 Oct 2015 17:25:06 +0800 -Subject: [PATCH 028/117] amdgpu: add query for aperture va range - -Change-Id: I4358cdd7cd86f172967e063eac13708941c4e566 -Signed-off-by: Flora Cui <flora.cui@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - amdgpu/amdgpu.h | 30 ++++++++++++++++++++++++++++++ - amdgpu/amdgpu_gpu_info.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 16 ++++++++++++++++ - 3 files changed, 91 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 8822a0c..ccb4971 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -1081,6 +1081,36 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, - struct amdgpu_gds_resource_info *gds_info); - - /** -+* Query private aperture range -+* -+* \param dev - [in] Device handle. See #amdgpu_device_initialize() -+* \param start - \c [out] Start of private aperture -+* \param end - \c [out] End of private aperture -+* -+* \return 0 on success\n -+* <0 - Negative POSIX Error code -+* -+*/ -+int amdgpu_query_private_aperture(amdgpu_device_handle dev, -+ uint64_t *start, -+ uint64_t *end); -+ -+/** -+* Query shared aperture range -+* -+* \param dev - [in] Device handle. See #amdgpu_device_initialize() -+* \param start - \c [out] Start of shared aperture -+* \param end - \c [out] End of shared aperture -+* -+* \return 0 on success\n -+* <0 - Negative POSIX Error code -+* -+*/ -+int amdgpu_query_shared_aperture(amdgpu_device_handle dev, -+ uint64_t *start, -+ uint64_t *end); -+ -+/** - * Read a set of consecutive memory-mapped registers. - * Not all registers are allowed to be read by userspace. - * -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 0cc17f1..73d8d11 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -308,3 +308,48 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, - - return 0; - } -+ -+static int amdgpu_query_virtual_range_info(amdgpu_device_handle dev, -+ uint32_t aperture, -+ uint64_t *start, -+ uint64_t *end) -+{ -+ struct drm_amdgpu_virtual_range range_info; -+ struct drm_amdgpu_info request; -+ int r; -+ -+ memset(&range_info, 0, sizeof(range_info)); -+ request.return_pointer = (uintptr_t)&range_info; -+ request.return_size = sizeof(range_info); -+ request.query = AMDGPU_INFO_VIRTUAL_RANGE; -+ request.virtual_range.aperture = aperture; -+ -+ r = drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, -+ sizeof(struct drm_amdgpu_info)); -+ if (r) -+ return r; -+ -+ *start = range_info.start; -+ *end = range_info.end; -+ return 0; -+} -+ -+int amdgpu_query_private_aperture(amdgpu_device_handle dev, -+ uint64_t *start, -+ uint64_t *end) -+{ -+ return amdgpu_query_virtual_range_info(dev, -+ AMDGPU_SUA_APERTURE_PRIVATE, -+ start, -+ end); -+} -+ -+int amdgpu_query_shared_aperture(amdgpu_device_handle dev, -+ uint64_t *start, -+ uint64_t *end) -+{ -+ return amdgpu_query_virtual_range_info(dev, -+ AMDGPU_SUA_APERTURE_SHARED, -+ start, -+ end); -+} -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 2cbea72..f97acd1 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -504,6 +504,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_DEV_INFO 0x16 - /* visible vram usage */ - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 -+/* virtual range */ -+#define AMDGPU_INFO_VIRTUAL_RANGE 0x18 - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -@@ -560,6 +562,11 @@ struct drm_amdgpu_info { - uint32_t index; - uint32_t _pad; - } query_fw; -+ -+ struct { -+ uint32_t aperture; -+ uint32_t _pad; -+ } virtual_range; - }; - }; - -@@ -669,4 +676,13 @@ struct drm_amdgpu_info_hw_ip { - #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ - #define AMDGPU_FAMILY_CZ 135 /* Carrizo */ - -+/** -+ * Definition of System Unified Address (SUA) apertures -+ */ -+#define AMDGPU_SUA_APERTURE_PRIVATE 1 -+#define AMDGPU_SUA_APERTURE_SHARED 2 -+struct drm_amdgpu_virtual_range { -+ uint64_t start; -+ uint64_t end; -+}; - #endif --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0029-amdgpu-Implement-SVM-v2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0029-amdgpu-Implement-SVM-v2.patch deleted file mode 100644 index 948d9072..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0029-amdgpu-Implement-SVM-v2.patch +++ /dev/null @@ -1,305 +0,0 @@ -From f34f4232b7a2dad9bb1aaaa68f77ed5a5fa76456 Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 20 Oct 2015 11:47:14 -0400 -Subject: [PATCH 029/117] amdgpu: Implement SVM v2 - -SWDEV-75927: Coarse Grain SVM support for OpenCL 2.0 -Add SVM API. -Implement SVM to reserve CPU and GPU VM address space for SVM. Implement commit/uncommit function for SVM. - -v2: -Merge patch1 and patch2. -Update description of the commit. -Address review comments on coding style. -Update comments in source code. -Fix one issue in function amdgpu_va_range_query. The start of the range should be dev->vamgr_svm->va_min. -Fix an error code. - -Change-Id: Ib804b075347646ee6c4b4159583f1b4a0325df08 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - amdgpu/amdgpu.h | 28 ++++++++- - amdgpu/amdgpu_device.c | 3 + - amdgpu/amdgpu_internal.h | 6 ++ - amdgpu/amdgpu_vamgr.c | 145 ++++++++++++++++++++++++++++++++++++++++++++++- - 4 files changed, 178 insertions(+), 4 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index ccb4971..79314fb 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -87,7 +87,9 @@ enum amdgpu_bo_handle_type { - enum amdgpu_gpu_va_range - { - /** Allocate from "normal"/general range */ -- amdgpu_gpu_va_range_general = 0 -+ amdgpu_gpu_va_range_general = 0, -+ /** Allocate from svm range */ -+ amdgpu_gpu_va_range_svm = 1 - }; - - /*--------------------------------------------------------------------------*/ -@@ -1238,6 +1240,30 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, - uint32_t ops); - - /** -+ * Commit SVM allocation in a process -+ * -+ * \param va_range_handle - \c [in] Handle of SVM allocation -+ * \param cpu - \c [out] CPU pointer. The value is equal to GPU VM address. -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_svm_commit(amdgpu_va_handle va_range_handle, -+ void **cpu); -+ -+/** -+ * Uncommit SVM alloation in process's CPU_VM -+ * -+ * \param va_range_handle - \c [in] Handle of SVM allocation -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_svm_uncommit(amdgpu_va_handle va_range_handle); -+ -+/** - * create semaphore - * - * \param sem - \c [out] semaphore handle -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index e5a923e..eb71c44 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -130,6 +130,7 @@ static int amdgpu_get_auth(int fd, int *auth) - - static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { -+ amdgpu_svm_vamgr_deinit(dev); - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); - amdgpu_vamgr_deinit(dev->vamgr_32); -@@ -275,6 +276,8 @@ int amdgpu_device_initialize(int fd, - amdgpu_vamgr_init(dev->vamgr_32, start, max, - dev->dev_info.virtual_address_alignment); - -+ amdgpu_svm_vamgr_init(dev); -+ - *major_version = dev->major_version; - *minor_version = dev->minor_version; - *device_handle = dev; -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 557ba1f..3ae92d9 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -54,6 +54,7 @@ struct amdgpu_bo_va_hole { - struct amdgpu_bo_va_mgr { - /* the start virtual address */ - uint64_t va_offset; -+ uint64_t va_min; - uint64_t va_max; - struct list_head va_holes; - pthread_mutex_t bo_va_mutex; -@@ -87,6 +88,8 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr *vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr *vamgr_32; -+ /** The VA manager for SVM address space */ -+ struct amdgpu_bo_va_mgr *vamgr_svm; - }; - - struct amdgpu_bo { -@@ -148,6 +151,9 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - drm_private void - amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size); - -+int amdgpu_svm_vamgr_init(struct amdgpu_device *dev); -+void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev); -+ - drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); - - drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 8a707cb..f664216 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -36,18 +36,30 @@ - int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) - { -- if (type == amdgpu_gpu_va_range_general) { -+ switch (type) { -+ case amdgpu_gpu_va_range_general: - *start = dev->dev_info.virtual_address_offset; - *end = dev->dev_info.virtual_address_max; - return 0; -+ case amdgpu_gpu_va_range_svm: -+ if (dev->vamgr_svm) { -+ *start = dev->vamgr_svm->va_min; -+ *end = dev->vamgr_svm->va_max; -+ } else { -+ *start = 0ULL; -+ *end = 0ULL; -+ } -+ return 0; -+ default: -+ return -EINVAL; - } -- return -EINVAL; - } - - drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, - uint64_t max, uint64_t alignment) - { - mgr->va_offset = start; -+ mgr->va_min = start; - mgr->va_max = max; - mgr->va_alignment = alignment; - -@@ -235,7 +247,12 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - { - struct amdgpu_bo_va_mgr *vamgr; - -- if (flags & AMDGPU_VA_RANGE_32_BIT) -+ if (amdgpu_gpu_va_range_svm == va_range_type) { -+ vamgr = dev->vamgr_svm; -+ if (!vamgr) -+ return -EINVAL; -+ } -+ else if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = dev->vamgr_32; - else - vamgr = dev->vamgr; -@@ -285,3 +302,125 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) - free(va_range_handle); - return 0; - } -+ -+/** -+ * Initialize SVM VAM manager. -+ * When this function return error, future SVM allocation will fail. -+ * Caller may ignore the error code returned by this function. -+ * -+ * \param dev - \c [in] amdgpu_device pointer -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ */ -+int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) -+{ -+ uint64_t start; -+ uint64_t end; -+ /* size of SVM range */ -+ uint64_t size; -+ uint64_t base_required; -+ /* Size of step when looking for SVM range. */ -+ uint64_t step; -+ /*Will not search less than this address. */ -+ uint64_t min_base_required; -+ void * cpu_address; -+ /* return value of this function. */ -+ int ret; -+ -+ ret = amdgpu_va_range_query(dev, amdgpu_gpu_va_range_general, &start, &end); -+ if (ret) -+ return ret; -+ -+ /* size of the general VM */ -+ size = end - start; -+ /* size of SVM range */ -+ size = size / 4; -+ /* at least keep lower 4G for process usage in CPU address space*/ -+ min_base_required = 4ULL * 1024ULL * 1024ULL * 1024ULL; -+ step = size / 8; -+ -+ ret = -ENOSPC; -+ /* We try to find a hole both in CPU/GPU VM address space for SVM from top -+ * to bottom. -+ */ -+ for (base_required = end - size; base_required >= min_base_required; -+ base_required -= step) { -+ start = amdgpu_vamgr_find_va(dev->vamgr, size, -+ dev->dev_info.virtual_address_alignment, base_required); -+ if (start != base_required) -+ continue; -+ -+ /* Try to map the SVM range in CPU VM */ -+ cpu_address = mmap((void *)start, size, PROT_NONE, -+ MAP_PRIVATE | MAP_NORESERVE | MAP_ANONYMOUS, -1, 0); -+ if (cpu_address == (void *)start) { -+ dev->vamgr_svm = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); -+ if (dev->vamgr_svm == NULL) { -+ amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ munmap(cpu_address, size); -+ ret = -ENOMEM; -+ } else { -+ amdgpu_vamgr_init(dev->vamgr_svm, start, start + size, -+ dev->dev_info.virtual_address_alignment); -+ ret = 0; -+ } -+ break; -+ } else if (cpu_address == MAP_FAILED) { -+ /* Probably there is no space in this process's address space for -+ such size of SVM range. This is very rare for 64 bit CPU. -+ */ -+ amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ ret = -ENOMEM; -+ break; -+ } else { /* cpu_address != (void *)start */ -+ /* This CPU VM address (start) is not available*/ -+ amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ munmap(cpu_address, size); -+ base_required -= step; -+ } -+ } -+ -+ return ret; -+} -+ -+void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev) -+{ -+ if (dev->vamgr_svm) { -+ amdgpu_vamgr_deinit(dev->vamgr_svm); -+ munmap((void *)dev->vamgr_svm->va_min, -+ dev->vamgr_svm->va_max - dev->vamgr_svm->va_min); -+ free(dev->vamgr_svm); -+ } -+} -+ -+int amdgpu_svm_commit(amdgpu_va_handle va_range_handle, -+ void **cpu) -+{ -+ if (!va_range_handle || !va_range_handle->address) -+ return -EINVAL; -+ if (va_range_handle->range != amdgpu_gpu_va_range_svm) -+ return -EINVAL; -+ -+ if (mprotect((void *)va_range_handle->address, -+ va_range_handle->size, PROT_READ | PROT_WRITE) == 0) { -+ *cpu = (void *)va_range_handle->address; -+ return 0; -+ } else -+ return errno; -+} -+ -+int amdgpu_svm_uncommit(amdgpu_va_handle va_range_handle) -+{ -+ if (!va_range_handle || !va_range_handle->address) -+ return -EINVAL; -+ if (va_range_handle->range != amdgpu_gpu_va_range_svm) -+ return -EINVAL; -+ -+ if (mprotect((void *)va_range_handle->address, -+ va_range_handle->size, PROT_NONE) == 0) { -+ return 0; -+ } else -+ return errno; -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0030-amdgpu-SVM-test-v2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0030-amdgpu-SVM-test-v2.patch deleted file mode 100644 index bacd7388..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0030-amdgpu-SVM-test-v2.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 7b1f524b40c1ec014265f49646d10ef8cd52659d Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 20 Oct 2015 11:52:08 -0400 -Subject: [PATCH 030/117] amdgpu: SVM test v2 - -SWDEV-75927: Coarse Grain SVM support for OpenCL 2.0 Add SVM relevant test. - -v2: -Update the description of this commit. -Fix an issue that the SVM feature should not be tested when SVM range is not supported. -Remove test for query function for general VM range. - -Change-Id: I21fad07611d88280ffa1375ecf1de95c305cac22 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - tests/amdgpu/basic_tests.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 46 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 56db935..eb73578 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -49,6 +49,7 @@ static void amdgpu_command_submission_sdma(void); - static void amdgpu_command_submission_multi_fence(void); - static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); -+static void amdgpu_svm_test(void); - - CU_TestInfo basic_tests[] = { - { "Query Info Test", amdgpu_query_info_test }, -@@ -59,9 +60,11 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, - { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, - { "SW semaphore Test", amdgpu_semaphore_test }, -+ { "SVM Test", amdgpu_svm_test }, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) -+#define SVM_TEST_COUNT 16 - #define SDMA_PKT_HEADER_op_offset 0 - #define SDMA_PKT_HEADER_op_mask 0x000000FF - #define SDMA_PKT_HEADER_op_shift 0 -@@ -1077,3 +1080,46 @@ static void amdgpu_userptr_test(void) - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); - } -+ -+static void amdgpu_svm_test(void) -+{ -+ int r; -+ uint64_t svm_mc; -+ amdgpu_va_handle va_handle[SVM_TEST_COUNT]; -+ void *cpu; -+ uint64_t start; -+ uint64_t end; -+ int i; -+ -+ r = amdgpu_va_range_query(device_handle, -+ amdgpu_gpu_va_range_svm, &start, &end); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ /* If there is no SVM range, exit this function.*/ -+ if (start == 0ULL && end == 0ULL) -+ return; -+ -+ CU_ASSERT(start < end); -+ CU_ASSERT(end - start >= 1ULL * 1024ULL * 1024ULL * 1024ULL); -+ -+ for (i = 0; i < SVM_TEST_COUNT; i++) { -+ r = amdgpu_va_range_alloc(device_handle, -+ amdgpu_gpu_va_range_svm, -+ 64 * 1024 * 1024, 1, 0, &svm_mc, -+ &va_handle[i], 0); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_svm_commit(va_handle[i], &cpu); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_PTR_NOT_NULL(cpu); -+ CU_ASSERT_EQUAL(svm_mc, (uint64_t)cpu); -+ } -+ -+ for (i = 0; i < SVM_TEST_COUNT; i++) { -+ r = amdgpu_svm_uncommit(va_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_va_range_free(va_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch deleted file mode 100644 index 1e2c81e7..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch +++ /dev/null @@ -1,167 +0,0 @@ -From e977542110f13aa8b0d3e4cf89f56140f0a0009f Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Thu, 29 Oct 2015 16:13:45 -0400 -Subject: [PATCH 031/117] amdgpu: Implement multiGPU SVM support v2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -With this change, if there are multiple GPU devices, SVM range and allocation is global to all GPU devices. -This is to meet the OpenCL 2.0 SVM requirement. This is not a perfect solution. But we have not found better solution. - -Constraints: - 1. Application should initialize all relevant devices before allocate SVM address. - 2. If devices do not have similar GPU VM configuration, libdrm can disable SVM when new device are initialized. - -v2: - 1. Put svm_refcount and svm_valid as a field of amdgpu_bo_va_mgr. - 2. Adjust title. - -Change-Id: I2cfa97e61a9ae1184da9a95f15398e050cb5caaf -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_internal.h | 6 +++-- - amdgpu/amdgpu_vamgr.c | 61 ++++++++++++++++++++++++++++++++---------------- - 2 files changed, 45 insertions(+), 22 deletions(-) - -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 3ae92d9..0506853 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -59,6 +59,10 @@ struct amdgpu_bo_va_mgr { - struct list_head va_holes; - pthread_mutex_t bo_va_mutex; - uint32_t va_alignment; -+ /* reference count. It is used by SVM for mulit GPU.*/ -+ atomic_t refcount; -+ /* Is the VM manager valid. It is used by SVM for mulit GPU.*/ -+ bool valid; - }; - - struct amdgpu_va { -@@ -88,8 +92,6 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr *vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr *vamgr_32; -- /** The VA manager for SVM address space */ -- struct amdgpu_bo_va_mgr *vamgr_svm; - }; - - struct amdgpu_bo { -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index f664216..945b006 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -33,6 +33,9 @@ - #include "amdgpu_internal.h" - #include "util_math.h" - -+/* Devices share SVM range. So a global SVM VAM manager is needed. */ -+static struct amdgpu_bo_va_mgr vamgr_svm; -+ - int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) - { -@@ -42,9 +45,9 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, - *end = dev->dev_info.virtual_address_max; - return 0; - case amdgpu_gpu_va_range_svm: -- if (dev->vamgr_svm) { -- *start = dev->vamgr_svm->va_min; -- *end = dev->vamgr_svm->va_max; -+ if (vamgr_svm.valid) { -+ *start = vamgr_svm.va_min; -+ *end = vamgr_svm.va_max; - } else { - *start = 0ULL; - *end = 0ULL; -@@ -248,8 +251,8 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - struct amdgpu_bo_va_mgr *vamgr; - - if (amdgpu_gpu_va_range_svm == va_range_type) { -- vamgr = dev->vamgr_svm; -- if (!vamgr) -+ vamgr = &vamgr_svm; -+ if (!vamgr->valid) - return -EINVAL; - } - else if (flags & AMDGPU_VA_RANGE_32_BIT) -@@ -329,6 +332,23 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - /* return value of this function. */ - int ret; - -+ if (atomic_inc_return(&vamgr_svm.refcount) != 1) { -+ /* This is not the first time to initialize SVM in this process. */ -+ if (!vamgr_svm.valid) -+ return -ENOSPC; -+ -+ start = amdgpu_vamgr_find_va(dev->vamgr, -+ vamgr_svm.va_max - vamgr_svm.va_min, -+ dev->dev_info.virtual_address_alignment, vamgr_svm.va_min); -+ -+ if (start != vamgr_svm.va_min) { -+ vamgr_svm.valid = false; -+ return -ENOSPC; -+ } -+ -+ return 0; -+ } -+ - ret = amdgpu_va_range_query(dev, amdgpu_gpu_va_range_general, &start, &end); - if (ret) - return ret; -@@ -356,16 +376,9 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - cpu_address = mmap((void *)start, size, PROT_NONE, - MAP_PRIVATE | MAP_NORESERVE | MAP_ANONYMOUS, -1, 0); - if (cpu_address == (void *)start) { -- dev->vamgr_svm = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); -- if (dev->vamgr_svm == NULL) { -- amdgpu_vamgr_free_va(dev->vamgr, start, size); -- munmap(cpu_address, size); -- ret = -ENOMEM; -- } else { -- amdgpu_vamgr_init(dev->vamgr_svm, start, start + size, -- dev->dev_info.virtual_address_alignment); -- ret = 0; -- } -+ amdgpu_vamgr_init(&vamgr_svm, start, start + size, -+ dev->dev_info.virtual_address_alignment); -+ ret = 0; - break; - } else if (cpu_address == MAP_FAILED) { - /* Probably there is no space in this process's address space for -@@ -382,16 +395,24 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - } - } - -+ if (!ret) -+ vamgr_svm.valid = true; -+ - return ret; - } - - void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev) - { -- if (dev->vamgr_svm) { -- amdgpu_vamgr_deinit(dev->vamgr_svm); -- munmap((void *)dev->vamgr_svm->va_min, -- dev->vamgr_svm->va_max - dev->vamgr_svm->va_min); -- free(dev->vamgr_svm); -+ if (atomic_dec_and_test(&vamgr_svm.refcount)) { -+ /* This is the last device referencing SVM. */ -+ if (vamgr_svm.va_max != 0) { -+ /* SVM was initialized successfull. So SVM need uninitialization.*/ -+ amdgpu_vamgr_deinit(&vamgr_svm); -+ munmap((void *)vamgr_svm.va_min, -+ vamgr_svm.va_max - vamgr_svm.va_min); -+ vamgr_svm.va_max = 0; -+ } -+ vamgr_svm.valid = false; - } - } - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch deleted file mode 100644 index 388419d8..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch +++ /dev/null @@ -1,335 +0,0 @@ -From ce7de7e34c1a87d56bcc7a8ebeac1a25756c5991 Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Fri, 30 Oct 2015 12:04:07 -0400 -Subject: [PATCH 032/117] tests/amdgpu: Add test for multi GPUs SVM test v3 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. We try to open all GPUs when test starts. -2. Test multi GPUs for SVM -3. Add verbose output option and facility into this unit test app. - -v2: -1. Adjust title -2. Use drmGetDevices to get the number of cards available. -3. Add warning output option and facility into this unit test app. -4. Adjust a comment and delete useless C statement when open function call fails. -5. Add two informative outputs in single SVM test. - -v3: -1. Use general device name from drmGetDevices instead of fixed name. -2. open devices in a single "for" statement. -3. Create a function to close all devices. - -Change-Id: I313c13eabd6f0c2d3107ba37413e8ebd871faa0e -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Acked-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/amdgpu_test.c | 92 +++++++++++++++++++++++++++++++++++++++------- - tests/amdgpu/amdgpu_test.h | 5 +++ - tests/amdgpu/basic_tests.c | 71 +++++++++++++++++++++++++++++++++++ - 3 files changed, 154 insertions(+), 14 deletions(-) - -diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c -index 71f357c..1e71fbf 100644 ---- a/tests/amdgpu/amdgpu_test.c -+++ b/tests/amdgpu/amdgpu_test.c -@@ -56,6 +56,10 @@ - */ - int drm_amdgpu[MAX_CARDS_SUPPORTED]; - -+static int num_devices; -+static bool verbose = false; -+static bool warning = false; -+ - /** The table of all known test suites to run */ - static CU_SuiteInfo suites[] = { - { -@@ -106,14 +110,24 @@ static void display_test_suites(void) - } - } - -+static void amdgpu_close_all() -+{ -+ int i; -+ for (i = 0; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) -+ close(drm_amdgpu[i]); -+} - - /** Help string for command line parameters */ --static const char usage[] = "Usage: %s [-hl] [<-s <suite id>> [-t <test id>]]\n" -+static const char usage[] = -+ "Usage: %s [-hlvw] [<-s <suite id>> [-t <test id>]]\n" - "where:\n" - " l - Display all suites and their tests\n" -+ " v - Verbose output\n" -+ " w - Output warning message\n" - " h - Display this help\n"; - /** Specified options strings for getopt */ --static const char options[] = "hls:t:"; -+static const char options[] = "hlvws:t:"; - - /* The main() function for setting up and running the tests. - * Returns a CUE_SUCCESS on successful running, another -@@ -127,8 +141,10 @@ int main(int argc, char **argv) - int test_id = -1; /* By default run all tests in the suite */ - CU_pSuite pSuite = NULL; - CU_pTest pTest = NULL; -+ drmDevicePtr devices[MAX_CARDS_SUPPORTED]; - - int aval = drmAvailable(); -+ char card_name[256]; - - if (aval == 0) { - fprintf(stderr, "DRM driver is not available\n"); -@@ -153,6 +169,12 @@ int main(int argc, char **argv) - case 't': - test_id = atoi(optarg); - break; -+ case 'v': -+ verbose = true; -+ break; -+ case 'w': -+ warning = true; -+ break; - case '?': - case 'h': - fprintf(stderr, usage, argv[0]); -@@ -163,17 +185,31 @@ int main(int argc, char **argv) - } - } - -- /* Try to open all possible radeon connections -- * Right now: Open only the 0. -+ /* Try to open all possible amdgpu connections - */ -- printf("Try to open the card 0..\n"); -- drm_amdgpu[0] = open("/dev/dri/card0", O_RDWR | O_CLOEXEC); -- -- if (drm_amdgpu[0] < 0) { -- perror("Cannot open /dev/dri/card0\n"); -+ num_devices = drmGetDevices(devices, MAX_CARDS_SUPPORTED); -+ amdgpu_vprintf("\n Number of DRI devices is %d\n", num_devices); -+ if (num_devices > MAX_CARDS_SUPPORTED) -+ num_devices = MAX_CARDS_SUPPORTED; -+ if (num_devices <= 0) { -+ perror("Cannot query number of DRI devices.\n"); - exit(EXIT_FAILURE); - } - -+ for (i = 0; i < num_devices; i++) { -+ amdgpu_vprintf("Try to open %s..\n", -+ devices[i]->nodes[DRM_NODE_PRIMARY]); -+ drm_amdgpu[i] = open(devices[i]->nodes[DRM_NODE_PRIMARY], -+ O_RDWR | O_CLOEXEC); -+ if (i == 0 && drm_amdgpu[i] < 0) { -+ drmFreeDevices(devices, num_devices); -+ /* It is essential to open first connection to run any test. */ -+ perror("Cannot open first card.\n"); -+ exit(EXIT_FAILURE); -+ } -+ } -+ drmFreeDevices(devices, num_devices); -+ - /** Display version of DRM driver */ - drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); - -@@ -191,7 +227,7 @@ int main(int argc, char **argv) - - /* initialize the CUnit test registry */ - if (CUE_SUCCESS != CU_initialize_registry()) { -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); - return CU_get_error(); - } - -@@ -200,7 +236,7 @@ int main(int argc, char **argv) - fprintf(stderr, "suite registration failed - %s\n", - CU_get_error_msg()); - CU_cleanup_registry(); -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); - exit(EXIT_FAILURE); - } - -@@ -222,7 +258,7 @@ int main(int argc, char **argv) - fprintf(stderr, "Invalid test id: %d\n", - test_id); - CU_cleanup_registry(); -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); - exit(EXIT_FAILURE); - } - } else -@@ -231,13 +267,41 @@ int main(int argc, char **argv) - fprintf(stderr, "Invalid suite id : %d\n", - suite_id); - CU_cleanup_registry(); -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); - exit(EXIT_FAILURE); - } - } else - CU_basic_run_tests(); - - CU_cleanup_registry(); -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); -+ - return CU_get_error(); - } -+ -+void amdgpu_vprintf(char *fmt, ...) -+{ -+ va_list args; -+ if (verbose) { -+ va_start(args, fmt); -+ vprintf(fmt, args); -+ va_end(args); -+ } -+} -+ -+void amdgpu_warning(bool condition, char *fmt, ...) -+{ -+ if (warning && condition) -+ { -+ printf ("WARNING: "); -+ va_list args; -+ va_start(args, fmt); -+ vprintf(fmt, args); -+ va_end(args); -+ } -+} -+ -+int amdgpu_num_devices() -+{ -+ return num_devices; -+} -diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h -index fca92ad..5c47ba3 100644 ---- a/tests/amdgpu/amdgpu_test.h -+++ b/tests/amdgpu/amdgpu_test.h -@@ -104,6 +104,11 @@ extern CU_TestInfo vce_tests[]; - /** - * Helper functions - */ -+ -+void amdgpu_vprintf(char *fmt, ...); -+void amdgpu_warning(bool condition, char *fmt, ...); -+int amdgpu_num_devices(); -+ - static inline amdgpu_bo_handle gpu_mem_alloc( - amdgpu_device_handle device_handle, - uint64_t size, -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index eb73578..23178e0 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -50,6 +50,7 @@ static void amdgpu_command_submission_multi_fence(void); - static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); - static void amdgpu_svm_test(void); -+static void amdgpu_multi_svm_test(void); - - CU_TestInfo basic_tests[] = { - { "Query Info Test", amdgpu_query_info_test }, -@@ -61,6 +62,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, - { "SW semaphore Test", amdgpu_semaphore_test }, - { "SVM Test", amdgpu_svm_test }, -+ { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) -@@ -1094,6 +1096,8 @@ static void amdgpu_svm_test(void) - r = amdgpu_va_range_query(device_handle, - amdgpu_gpu_va_range_svm, &start, &end); - CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf("\n"); -+ amdgpu_vprintf("SVM range is from 0x%llx to 0x%llx.\n", start, end); - - /* If there is no SVM range, exit this function.*/ - if (start == 0ULL && end == 0ULL) -@@ -1108,6 +1112,7 @@ static void amdgpu_svm_test(void) - 64 * 1024 * 1024, 1, 0, &svm_mc, - &va_handle[i], 0); - CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf("Allocate SVM MC 0x%llx.\n", svm_mc); - - r = amdgpu_svm_commit(va_handle[i], &cpu); - CU_ASSERT_EQUAL(r, 0); -@@ -1123,3 +1128,69 @@ static void amdgpu_svm_test(void) - CU_ASSERT_EQUAL(r, 0); - } - } -+ -+static void amdgpu_multi_svm_test(void) -+{ -+ int r; -+ int i; -+ uint64_t svm_mcs[MAX_CARDS_SUPPORTED]; -+ amdgpu_va_handle va_handles[MAX_CARDS_SUPPORTED]; -+ amdgpu_device_handle device_handles[MAX_CARDS_SUPPORTED]; -+ uint32_t major_version; -+ uint32_t minor_version; -+ int num_devices; -+ -+ device_handles[0] = device_handle; -+ num_devices = amdgpu_num_devices(); -+ -+ for (i = 1; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_device_initialize(drm_amdgpu[i], &major_version, -+ &minor_version, &device_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ amdgpu_vprintf("\n"); -+ amdgpu_vprintf(" Testing to alloc and free SVM in all GPUs.\n"); -+ amdgpu_vprintf(" The svm_mcs generally are same.\n"); -+ for (i = 0; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_va_range_alloc(device_handles[i], -+ amdgpu_gpu_va_range_svm, -+ 0x1000000, 1, 0, &svm_mcs[i], -+ &va_handles[i], 0); -+ CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf(" card %d, svm_mc 0x%llx\n", i, svm_mcs[i]); -+ amdgpu_warning(svm_mcs[i] != svm_mcs[0], -+ "The SVM from different GPUs should be able to be allocated" -+ " from same location."); -+ r = amdgpu_va_range_free(va_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ amdgpu_vprintf(" Testing to alloc SVM in all GPUs.\n"); -+ amdgpu_vprintf(" The svm_mcs are generally different by 0x1000000\n"); -+ for (i = 0; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_va_range_alloc(device_handles[i], -+ amdgpu_gpu_va_range_svm, -+ 0x1000000, 1, 0, &svm_mcs[i], -+ &va_handles[i], 0); -+ CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf(" card %d, svm_mc 0x%llx\n", i, svm_mcs[i]); -+ amdgpu_warning(svm_mcs[i] - svm_mcs[0] != 0x1000000 * i, -+ "The SVM from GPUs should be allocated sequentially."); -+ } -+ -+ for (i = 0; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_va_range_free(va_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ for (i = 1; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_device_deinitialize(device_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0033-tests-amdgpu-Add-verbose-outputs-v2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0033-tests-amdgpu-Add-verbose-outputs-v2.patch deleted file mode 100644 index 81be4d87..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0033-tests-amdgpu-Add-verbose-outputs-v2.patch +++ /dev/null @@ -1,245 +0,0 @@ -From cb0741a52b97b4cf14a3407e74b5bf3973735a2f Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 3 Nov 2015 11:03:21 -0500 -Subject: [PATCH 033/117] tests/amdgpu: Add verbose outputs v2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. Add verbose output for information of compute rings. -2. Add verbose output for other hardware information, probably for test of harvesting. -3. Add verbose output for GPU information. This can provide information when reporting JIRA issue. -4. Add verbose output for firmware version. This can provide developer with firmware information. - -v2: Use 8 for the maximum ring number in function amd_query_hw_info_test - -Change-Id: I6e37332345007625456b33a20d7bfb8850eb53d5 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by:Jammy Zhou<Jammy.Zhou@amd.com> -Acked-by:Christian König<christian.koenig@amd.com> ---- - tests/amdgpu/amdgpu_test.c | 19 ++++++ - tests/amdgpu/amdgpu_test.h | 1 + - tests/amdgpu/basic_tests.c | 149 ++++++++++++++++++++++++++++++++++++++++++++- - 3 files changed, 167 insertions(+), 2 deletions(-) - -diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c -index 1e71fbf..46f55c7 100644 ---- a/tests/amdgpu/amdgpu_test.c -+++ b/tests/amdgpu/amdgpu_test.c -@@ -305,3 +305,22 @@ int amdgpu_num_devices() - { - return num_devices; - } -+ -+/* Translate HW IP type to name. */ -+char * amdgpu_hw_ip_type_to_name(unsigned type) -+{ -+ switch (type) { -+ case AMDGPU_HW_IP_GFX: -+ return "graphic"; -+ case AMDGPU_HW_IP_COMPUTE: -+ return "compute"; -+ case AMDGPU_HW_IP_DMA: -+ return "DMA"; -+ case AMDGPU_HW_IP_UVD: -+ return "UVD"; -+ case AMDGPU_HW_IP_VCE: -+ return "VCE"; -+ default: -+ return NULL; -+ } -+} -diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h -index 5c47ba3..dd88eb5 100644 ---- a/tests/amdgpu/amdgpu_test.h -+++ b/tests/amdgpu/amdgpu_test.h -@@ -108,6 +108,7 @@ extern CU_TestInfo vce_tests[]; - void amdgpu_vprintf(char *fmt, ...); - void amdgpu_warning(bool condition, char *fmt, ...); - int amdgpu_num_devices(); -+char * amdgpu_hw_ip_type_to_name(unsigned type); - - static inline amdgpu_bo_handle gpu_mem_alloc( - amdgpu_device_handle device_handle, -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 23178e0..47c796e 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -112,18 +112,161 @@ int suite_basic_tests_clean(void) - return CUE_SCLEAN_FAILED; - } - --static void amdgpu_query_info_test(void) -+static void amdgpu_query_hw_info_test(unsigned type) -+{ -+ int r; -+ int i; -+ bool first_ring = true; -+ struct drm_amdgpu_info_hw_ip ip_info; -+ char *name; -+ -+ name = amdgpu_hw_ip_type_to_name(type); -+ CU_ASSERT_NOT_EQUAL(name, NULL); -+ -+ r = amdgpu_query_hw_ip_info(device_handle, type, -+ 0, &ip_info); -+ -+ CU_ASSERT_EQUAL(r, 0); -+ -+ amdgpu_vprintf("\n %s HW IP...\n", name); -+ amdgpu_vprintf(" major version:%d\n", ip_info.hw_ip_version_major); -+ amdgpu_vprintf(" minor version:%d\n", ip_info.hw_ip_version_minor); -+ amdgpu_vprintf(" capabilities_flags:0x%llx\n", -+ ip_info.capabilities_flags); -+ amdgpu_vprintf(" IB start alignment:%d\n", ip_info.ib_start_alignment); -+ amdgpu_vprintf(" IB size alignment:%d\n", ip_info.ib_size_alignment); -+ amdgpu_vprintf(" Following rings are supported: "); -+ for (i = 0; i < 8; i++) -+ if (ip_info.available_rings & 1 << i) { -+ if (first_ring) -+ first_ring = false; -+ else -+ amdgpu_vprintf(", "); -+ -+ amdgpu_vprintf("%d", i); -+ } -+ -+ amdgpu_vprintf(".\n"); -+} -+ -+static void amdgpu_query_gpu_info_test() - { - struct amdgpu_gpu_info gpu_info = {0}; -- uint32_t version, feature; - int r; -+ int i, j; - - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - -+ amdgpu_vprintf("\n GPU info...\n"); -+ -+ amdgpu_vprintf(" Asic id:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.asic_id); -+ amdgpu_vprintf(" Chip revision:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.chip_rev); -+ amdgpu_vprintf(" Chip external revision:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.chip_external_rev); -+ amdgpu_vprintf(" Family ID:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.family_id); -+ amdgpu_vprintf(" Special flags:"); -+ amdgpu_vprintf("0x%llx\n", gpu_info.ids_flags); -+ amdgpu_vprintf(" max engine clock:"); -+ amdgpu_vprintf("0x%llx\n", gpu_info.max_engine_clk); -+ amdgpu_vprintf(" max memory clock:"); -+ amdgpu_vprintf("0x%llx\n", gpu_info.max_memory_clk); -+ amdgpu_vprintf(" number of shader engines:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.num_shader_engines); -+ amdgpu_vprintf(" number of shader arrays per engine:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.num_shader_arrays_per_engine); -+ amdgpu_vprintf(" Number of available good shader pipes:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.avail_quad_shader_pipes); -+ amdgpu_vprintf(" Max. number of shader pipes." -+ "(including good and bad pipes :"); -+ amdgpu_vprintf("0x%x\n", gpu_info.max_quad_shader_pipes); -+ amdgpu_vprintf(" Number of parameter cache entries per shader quad " -+ "pipe:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.cache_entries_per_quad_pipe); -+ amdgpu_vprintf(" Number of available graphics context:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.num_hw_gfx_contexts); -+ amdgpu_vprintf(" Number of render backend pipes:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.rb_pipes); -+ amdgpu_vprintf(" Enabled render backend pipe mask:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.enabled_rb_pipes_mask); -+ amdgpu_vprintf(" Frequency of GPU Counter:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.gpu_counter_freq); -+ -+ amdgpu_vprintf(" CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE:\n"); -+ for (i = 0; i < 4; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.backend_disable[i]); -+ -+ amdgpu_vprintf(" Value of MC_ARB_RAMCFG register:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.mc_arb_ramcfg); -+ amdgpu_vprintf(" Value of GB_ADDR_CONFIG:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.gb_addr_cfg); -+ -+ amdgpu_vprintf(" Values of the GB_TILE_MODE0..31 registers:\n"); -+ for (i = 0; i < 32; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.gb_tile_mode[i]); -+ -+ amdgpu_vprintf(" Values of GB_MACROTILE_MODE0..15 registers:\n"); -+ for (i = 0; i < 16; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.gb_macro_tile_mode[i]); -+ -+ amdgpu_vprintf(" Value of PA_SC_RASTER_CONFIG register per SE:\n"); -+ for (i = 0; i < 4; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.pa_sc_raster_cfg[i]); -+ -+ amdgpu_vprintf(" Value of PA_SC_RASTER_CONFIG_1 register per SE:\n"); -+ for (i = 0; i < 4; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.pa_sc_raster_cfg1[i]); -+ -+ amdgpu_vprintf(" CU info (active number):"); -+ amdgpu_vprintf("0x%x\n", gpu_info.cu_active_number); -+ amdgpu_vprintf(" CU info (AU mask):"); -+ amdgpu_vprintf("0x%x\n", gpu_info.cu_ao_mask); -+ -+ amdgpu_vprintf(" CU info (AU bit map):"); -+ for (i = 0; i < 4; i++) { -+ amdgpu_vprintf("\n "); -+ for (j = 0; j < 4; j++) -+ amdgpu_vprintf(" [%d][%d]=0x%08x", i, j, gpu_info.cu_bitmap[i][j]); -+ } -+ amdgpu_vprintf("\n"); -+ -+ amdgpu_vprintf(" video memory type info:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.vram_type); -+ amdgpu_vprintf(" video memory bit width:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.vram_bit_width); -+ amdgpu_vprintf(" constant engine ram size:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.ce_ram_size); -+ amdgpu_vprintf(" vce harvesting instance:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.vce_harvest_config); -+ amdgpu_vprintf(" PCI revision ID:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.pci_rev_id); -+} -+ -+static void amdgpu_query_firmware_info_test(void) -+{ -+ uint32_t version, feature; -+ int r; -+ - r = amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0, - 0, &version, &feature); - CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf("\n VCE firmware info...\n"); -+ amdgpu_vprintf(" vce version: 0x%x\n", version); -+ amdgpu_vprintf(" vce feature: 0x%x\n", feature); -+} -+ -+static void amdgpu_query_info_test(void) -+{ -+ amdgpu_query_gpu_info_test(); -+ amdgpu_query_firmware_info_test(); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_GFX); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_COMPUTE); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_DMA); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_UVD); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_VCE); - } - - static void amdgpu_memory_alloc(void) -@@ -491,7 +634,9 @@ static void amdgpu_command_submission_compute(void) - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - -+ amdgpu_vprintf("\n"); - for (instance = 0; instance < 8; instance++) { -+ amdgpu_vprintf(" Submit NOP command on ring %d.\n", instance); - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch deleted file mode 100644 index f22421ea..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch +++ /dev/null @@ -1,38 +0,0 @@ -From e32955cf3b88b111e8d80a0c45e6e6d284d7d9a2 Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 3 Nov 2015 15:26:09 -0500 -Subject: [PATCH 034/117] amdgpu: Free/uninit vamgr_32 in theoretically correct - order -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -vamgr_32 is a region inside general VAM range. It is better to free and deinitialize it before general VAM range. - -Change-Id: Iaafaf5c1be7f274e933f1295a8822d90c1c6200d -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_device.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index eb71c44..a58a9d4 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -131,10 +131,10 @@ static int amdgpu_get_auth(int fd, int *auth) - static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { - amdgpu_svm_vamgr_deinit(dev); -- amdgpu_vamgr_deinit(dev->vamgr); -- free(dev->vamgr); - amdgpu_vamgr_deinit(dev->vamgr_32); - free(dev->vamgr_32); -+ amdgpu_vamgr_deinit(dev->vamgr); -+ free(dev->vamgr); - util_hash_table_destroy(dev->bo_flink_names); - util_hash_table_destroy(dev->bo_handles); - pthread_mutex_destroy(&dev->bo_table_mutex); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch deleted file mode 100644 index 790f0641..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 98342e54c0e8d290a70bfea2b0631169ea414787 Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 3 Nov 2015 15:46:33 -0500 -Subject: [PATCH 035/117] amdgpu: vamgr_32 can be a struct instead of a pointer -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -vamgr_32 is an integral part of amdgpu_device. We don't need to callac and free it. -This can save CPU time. Reduce heap fragment. - -Change-Id: I7b5797058e68d0b4c12705d628d32a996b2f3644 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_device.c | 8 ++------ - amdgpu/amdgpu_internal.h | 2 +- - amdgpu/amdgpu_vamgr.c | 4 ++-- - 3 files changed, 5 insertions(+), 9 deletions(-) - -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index a58a9d4..259c1cc 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -131,8 +131,7 @@ static int amdgpu_get_auth(int fd, int *auth) - static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { - amdgpu_svm_vamgr_deinit(dev); -- amdgpu_vamgr_deinit(dev->vamgr_32); -- free(dev->vamgr_32); -+ amdgpu_vamgr_deinit(&dev->vamgr_32); - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); - util_hash_table_destroy(dev->bo_flink_names); -@@ -270,10 +269,7 @@ int amdgpu_device_initialize(int fd, - if (start > 0xffffffff) - goto free_va; /* shouldn't get here */ - -- dev->vamgr_32 = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); -- if (dev->vamgr_32 == NULL) -- goto free_va; -- amdgpu_vamgr_init(dev->vamgr_32, start, max, -+ amdgpu_vamgr_init(&dev->vamgr_32, start, max, - dev->dev_info.virtual_address_alignment); - - amdgpu_svm_vamgr_init(dev); -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 0506853..892b467 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -91,7 +91,7 @@ struct amdgpu_device { - /** The global VA manager for the whole virtual address space */ - struct amdgpu_bo_va_mgr *vamgr; - /** The VA manager for the 32bit address space */ -- struct amdgpu_bo_va_mgr *vamgr_32; -+ struct amdgpu_bo_va_mgr vamgr_32; - }; - - struct amdgpu_bo { -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 945b006..916eb9e 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -256,7 +256,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - return -EINVAL; - } - else if (flags & AMDGPU_VA_RANGE_32_BIT) -- vamgr = dev->vamgr_32; -+ vamgr = &dev->vamgr_32; - else - vamgr = dev->vamgr; - -@@ -269,7 +269,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - if (!(flags & AMDGPU_VA_RANGE_32_BIT) && - (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { - /* fallback to 32bit address */ -- vamgr = dev->vamgr_32; -+ vamgr = &dev->vamgr_32; - *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, - va_base_alignment, va_base_required); - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch deleted file mode 100644 index 04da011e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 8326d0420e94fffc413eb9ef23de37074a20efeb Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 3 Nov 2015 15:52:57 -0500 -Subject: [PATCH 036/117] amdgpu: vamgr can be a struct instead of a pointer -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -vamgr is an integral part of amdgpu_device. We don't need to callac and free it. -This can save CPU time. Reduce heap fragment. - -Change-Id: Ib5ca9e93d007370d2d746aea2c21c2f91aefa3c2 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_device.c | 16 +++++----------- - amdgpu/amdgpu_internal.h | 2 +- - amdgpu/amdgpu_vamgr.c | 10 +++++----- - 3 files changed, 11 insertions(+), 17 deletions(-) - -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index 259c1cc..b1a7182 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -132,8 +132,7 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { - amdgpu_svm_vamgr_deinit(dev); - amdgpu_vamgr_deinit(&dev->vamgr_32); -- amdgpu_vamgr_deinit(dev->vamgr); -- free(dev->vamgr); -+ amdgpu_vamgr_deinit(&dev->vamgr); - util_hash_table_destroy(dev->bo_flink_names); - util_hash_table_destroy(dev->bo_handles); - pthread_mutex_destroy(&dev->bo_table_mutex); -@@ -254,16 +253,12 @@ int amdgpu_device_initialize(int fd, - if (r) - goto cleanup; - -- dev->vamgr = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); -- if (dev->vamgr == NULL) -- goto cleanup; -- -- amdgpu_vamgr_init(dev->vamgr, dev->dev_info.virtual_address_offset, -+ amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset, - dev->dev_info.virtual_address_max, - dev->dev_info.virtual_address_alignment); - - max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); -- start = amdgpu_vamgr_find_va(dev->vamgr, -+ start = amdgpu_vamgr_find_va(&dev->vamgr, - max - dev->dev_info.virtual_address_offset, - dev->dev_info.virtual_address_alignment, 0); - if (start > 0xffffffff) -@@ -284,10 +279,9 @@ int amdgpu_device_initialize(int fd, - - free_va: - r = -ENOMEM; -- amdgpu_vamgr_free_va(dev->vamgr, start, -+ amdgpu_vamgr_free_va(&dev->vamgr, start, - max - dev->dev_info.virtual_address_offset); -- amdgpu_vamgr_deinit(dev->vamgr); -- free(dev->vamgr); -+ amdgpu_vamgr_deinit(&dev->vamgr); - - cleanup: - if (dev->fd >= 0) -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 892b467..caec2a2 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -89,7 +89,7 @@ struct amdgpu_device { - struct drm_amdgpu_info_device dev_info; - struct amdgpu_gpu_info info; - /** The global VA manager for the whole virtual address space */ -- struct amdgpu_bo_va_mgr *vamgr; -+ struct amdgpu_bo_va_mgr vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr vamgr_32; - }; -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 916eb9e..64a3543 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -258,7 +258,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - else if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = &dev->vamgr_32; - else -- vamgr = dev->vamgr; -+ vamgr = &dev->vamgr; - - va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); - size = ALIGN(size, vamgr->va_alignment); -@@ -337,7 +337,7 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - if (!vamgr_svm.valid) - return -ENOSPC; - -- start = amdgpu_vamgr_find_va(dev->vamgr, -+ start = amdgpu_vamgr_find_va(&dev->vamgr, - vamgr_svm.va_max - vamgr_svm.va_min, - dev->dev_info.virtual_address_alignment, vamgr_svm.va_min); - -@@ -367,7 +367,7 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - */ - for (base_required = end - size; base_required >= min_base_required; - base_required -= step) { -- start = amdgpu_vamgr_find_va(dev->vamgr, size, -+ start = amdgpu_vamgr_find_va(&dev->vamgr, size, - dev->dev_info.virtual_address_alignment, base_required); - if (start != base_required) - continue; -@@ -384,12 +384,12 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - /* Probably there is no space in this process's address space for - such size of SVM range. This is very rare for 64 bit CPU. - */ -- amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ amdgpu_vamgr_free_va(&dev->vamgr, start, size); - ret = -ENOMEM; - break; - } else { /* cpu_address != (void *)start */ - /* This CPU VM address (start) is not available*/ -- amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ amdgpu_vamgr_free_va(&dev->vamgr, start, size); - munmap(cpu_address, size); - base_required -= step; - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0037-tests-amdgpu-add-the-heap-info-for-query.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0037-tests-amdgpu-add-the-heap-info-for-query.patch deleted file mode 100644 index 2b79b5ae..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0037-tests-amdgpu-add-the-heap-info-for-query.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 30625ac043a1dd882df4f9d1feed4b08ebdd6371 Mon Sep 17 00:00:00 2001 -From: Jammy Zhou <Jammy.Zhou@amd.com> -Date: Mon, 9 Nov 2015 13:40:41 +0800 -Subject: [PATCH 037/117] tests/amdgpu: add the heap info for query - -Change-Id: Icdaad4e373c316e0dde9a24cda4252ffd5163f1a -Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - tests/amdgpu/basic_tests.c | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 47c796e..ec68dac 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -258,6 +258,32 @@ static void amdgpu_query_firmware_info_test(void) - amdgpu_vprintf(" vce feature: 0x%x\n", feature); - } - -+static void amdgpu_query_heap_info_test(void) -+{ -+ struct amdgpu_heap_info info; -+ uint64_t total_vram, total_vram_used; -+ -+ amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, -+ 0, &info); -+ total_vram = info.heap_size; -+ total_vram_used = info.heap_usage; -+ -+ amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, -+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &info); -+ amdgpu_vprintf("\n Visible VRAM info...\n"); -+ amdgpu_vprintf(" size: 0x%x\n", info.heap_size); -+ amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); -+ amdgpu_vprintf("\n Invisible VRAM info...\n"); -+ amdgpu_vprintf(" size: 0x%x\n", total_vram - info.heap_size); -+ amdgpu_vprintf(" usage: 0x%x\n", total_vram_used - info.heap_usage); -+ -+ amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, -+ 0, &info); -+ amdgpu_vprintf("\n GTT info...\n"); -+ amdgpu_vprintf(" size: 0x%x\n", info.heap_size); -+ amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); -+} -+ - static void amdgpu_query_info_test(void) - { - amdgpu_query_gpu_info_test(); -@@ -267,6 +293,7 @@ static void amdgpu_query_info_test(void) - amdgpu_query_hw_info_test(AMDGPU_HW_IP_DMA); - amdgpu_query_hw_info_test(AMDGPU_HW_IP_UVD); - amdgpu_query_hw_info_test(AMDGPU_HW_IP_VCE); -+ amdgpu_query_heap_info_test(); - } - - static void amdgpu_memory_alloc(void) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch deleted file mode 100644 index 34cb4fd3..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch +++ /dev/null @@ -1,172 +0,0 @@ -From f639b2e37ecdcc49b4dbaf1dedac51ecabf7e20e Mon Sep 17 00:00:00 2001 -From: Jammy Zhou <Jammy.Zhou@amd.com> -Date: Tue, 10 Nov 2015 21:17:22 +0800 -Subject: [PATCH 038/117] amdgpu: reserve SVM range explicitly by clients (v3) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The SVM range is only used by OCL 2.0 now, and it shouldn't be -reserved when only other clients are used. With this change: - -amdgpu_svm_init() should be called to reserve the SVM range -amdgpu_svm_deinit() should be called to unreserve this range - -v3: fix a typo -v2: update the unit test as well - -Change-Id: Ia2495c3471a0c71c6b05fd81d84d5acfaf9a0a4c -Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> ---- - amdgpu/amdgpu.h | 21 +++++++++++++++++++++ - amdgpu/amdgpu_device.c | 3 --- - amdgpu/amdgpu_internal.h | 3 --- - amdgpu/amdgpu_vamgr.c | 4 ++-- - tests/amdgpu/basic_tests.c | 14 ++++++++++++++ - 5 files changed, 37 insertions(+), 8 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 79314fb..1db47c3 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -1240,6 +1240,27 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, - uint32_t ops); - - /** -+ * Reserve the virtual address range for SVM support -+ * -+ * \param amdgpu_device_handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_svm_init(amdgpu_device_handle dev); -+ -+/** -+ * Free the virtual address range for SVM support -+ * -+ * \param amdgpu_device_handle -+ * -+ * \return -+ * -+*/ -+void amdgpu_svm_deinit(amdgpu_device_handle dev); -+ -+/** - * Commit SVM allocation in a process - * - * \param va_range_handle - \c [in] Handle of SVM allocation -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index b1a7182..b517b1a 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -130,7 +130,6 @@ static int amdgpu_get_auth(int fd, int *auth) - - static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { -- amdgpu_svm_vamgr_deinit(dev); - amdgpu_vamgr_deinit(&dev->vamgr_32); - amdgpu_vamgr_deinit(&dev->vamgr); - util_hash_table_destroy(dev->bo_flink_names); -@@ -267,8 +266,6 @@ int amdgpu_device_initialize(int fd, - amdgpu_vamgr_init(&dev->vamgr_32, start, max, - dev->dev_info.virtual_address_alignment); - -- amdgpu_svm_vamgr_init(dev); -- - *major_version = dev->major_version; - *minor_version = dev->minor_version; - *device_handle = dev; -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index caec2a2..3760f94 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -153,9 +153,6 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - drm_private void - amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size); - --int amdgpu_svm_vamgr_init(struct amdgpu_device *dev); --void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev); -- - drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); - - drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 64a3543..973274d 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -317,7 +317,7 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) - * <0 - Negative POSIX Error code - * - */ --int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) -+int amdgpu_svm_init(amdgpu_device_handle dev) - { - uint64_t start; - uint64_t end; -@@ -401,7 +401,7 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - return ret; - } - --void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev) -+void amdgpu_svm_deinit(amdgpu_device_handle dev) - { - if (atomic_dec_and_test(&vamgr_svm.refcount)) { - /* This is the last device referencing SVM. */ -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index ec68dac..408a432 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -1265,6 +1265,9 @@ static void amdgpu_svm_test(void) - uint64_t end; - int i; - -+ r = amdgpu_svm_init(device_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ - r = amdgpu_va_range_query(device_handle, - amdgpu_gpu_va_range_svm, &start, &end); - CU_ASSERT_EQUAL(r, 0); -@@ -1299,6 +1302,8 @@ static void amdgpu_svm_test(void) - r = amdgpu_va_range_free(va_handle[i]); - CU_ASSERT_EQUAL(r, 0); - } -+ -+ amdgpu_svm_deinit(device_handle); - } - - static void amdgpu_multi_svm_test(void) -@@ -1315,11 +1320,17 @@ static void amdgpu_multi_svm_test(void) - device_handles[0] = device_handle; - num_devices = amdgpu_num_devices(); - -+ r = amdgpu_svm_init(device_handles[0]); -+ CU_ASSERT_EQUAL(r, 0); -+ - for (i = 1; i < num_devices; i++) - if (drm_amdgpu[i] > 0) { - r = amdgpu_device_initialize(drm_amdgpu[i], &major_version, - &minor_version, &device_handles[i]); - CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_svm_init(device_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); - } - - amdgpu_vprintf("\n"); -@@ -1362,7 +1373,10 @@ static void amdgpu_multi_svm_test(void) - - for (i = 1; i < num_devices; i++) - if (drm_amdgpu[i] > 0) { -+ amdgpu_svm_deinit(device_handles[i]); - r = amdgpu_device_deinitialize(device_handles[i]); - CU_ASSERT_EQUAL(r, 0); - } -+ -+ amdgpu_svm_deinit(device_handles[0]); - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch deleted file mode 100644 index 371bc6de..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 3fb478b00e1f3123f4c9b1efbd4a7e804679b64b Mon Sep 17 00:00:00 2001 -From: Jammy Zhou <Jammy.Zhou@amd.com> -Date: Mon, 9 Nov 2015 12:42:52 +0800 -Subject: [PATCH 039/117] amdgpu: expose the AMDGPU_GEM_CREATE_NO_EVICT flag - -With this flag specified, the buffer will be pinned at allocation time. - -Change-Id: Ibb75f27dc79ca678e58590b188a749b762429fce -Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> ---- - include/drm/amdgpu_drm.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index f97acd1..1df0d9c 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -75,6 +75,8 @@ - #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) - /* Flag that USWC attributes should be used for GTT */ - #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) -+/* Flag that the memory allocation should be pinned */ -+#define AMDGPU_GEM_CREATE_NO_EVICT (1 << 3) - - struct drm_amdgpu_gem_create_in { - /** the requested memory size */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0040-amdgpu-add-query-amdgpu-capability-defination.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0040-amdgpu-add-query-amdgpu-capability-defination.patch deleted file mode 100644 index 1da9f9ea..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0040-amdgpu-add-query-amdgpu-capability-defination.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 813fc7d4532d77b0fc46c0f80813fb63c86e8097 Mon Sep 17 00:00:00 2001 -From: jimqu <Jim.Qu@amd.com> -Date: Mon, 16 Nov 2015 15:13:00 +0800 -Subject: [PATCH 040/117] amdgpu: add query amdgpu capability defination - -Signed-off-by: JimQu <Jim.Qu@amd.com> - -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> - -Change-Id: Id615b06a59bc5a49aa8f7c7e658eb1bb1f318bd6 ---- - include/drm/amdgpu_drm.h | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 1df0d9c..981b346 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -508,6 +508,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 - /* virtual range */ - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 -+/* gpu capability */ -+#define AMDGPU_INFO_CAPABILITY 0x50 - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -@@ -569,6 +571,10 @@ struct drm_amdgpu_info { - uint32_t aperture; - uint32_t _pad; - } virtual_range; -+ -+ struct { -+ uint64_t type; -+ } query_capability; - }; - }; - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch deleted file mode 100644 index 1194b8e8..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 231f4155aba4fcef48298c44d02047db111885ca Mon Sep 17 00:00:00 2001 -From: jimqu <Jim.Qu@amd.com> -Date: Mon, 16 Nov 2015 15:15:14 +0800 -Subject: [PATCH 041/117] amdgpu: add query amdgpu pinning memory capability - defination - -Signed-off-by: JimQu <Jim.Qu@amd.com> - -Change-Id: I5f0095ef0cb550fad67aca222009b71634d79b4b -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> ---- - include/drm/amdgpu_drm.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 981b346..4ddb649 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -510,6 +510,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -+ /* query pin memory capability */ -+ #define AMDGPU_INFO_CAPABILITY_PIN_MEM 0x01 - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0042-amdgpu-add-amdgpu_query_capability-interface.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0042-amdgpu-add-amdgpu_query_capability-interface.patch deleted file mode 100644 index 61db1a40..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0042-amdgpu-add-amdgpu_query_capability-interface.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 8b7c227c3cb6429e2c53fd8375c415021626886d Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Mon, 16 Nov 2015 18:06:16 +0800 -Subject: [PATCH 042/117] amdgpu: add amdgpu_query_capability interface - -Change-Id: Iffdd157e411c19f4d9980994dad6952b183ef1a5 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Jim Qu <Jim.Qu@amd.com> ---- - amdgpu/amdgpu.h | 18 ++++++++++++++++++ - amdgpu/amdgpu_gpu_info.c | 6 ++++++ - include/drm/amdgpu_drm.h | 8 +++----- - 3 files changed, 27 insertions(+), 5 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 1db47c3..baae113 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -62,6 +62,11 @@ struct drm_amdgpu_info_hw_ip; - */ - #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) - -+/** -+ * Used in amdgpu_query_capability(), meaning if pin feature is enabled. -+ */ -+#define AMDGPU_CAP_PIN_MEM (1 << 0) -+ - /*--------------------------------------------------------------------------*/ - /* ----------------------------- Enums ------------------------------------ */ - /*--------------------------------------------------------------------------*/ -@@ -1070,6 +1075,19 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, - unsigned size, void *value); - - /** -+ * Query hardware or driver capabilities. -+ * -+ * -+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -+ * \param value - \c [out] Pointer to the return value. -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX error code -+ * -+*/ -+int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value); -+ -+/** - * Query information about GDS - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 73d8d11..133952d 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -48,6 +48,12 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, - sizeof(struct drm_amdgpu_info)); - } - -+int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value) -+{ -+ return amdgpu_query_info(dev, AMDGPU_INFO_CAPABILITY, -+ sizeof(uint64_t), value); -+} -+ - int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, - int32_t *result) - { -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 4ddb649..050e7fe 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -508,10 +508,11 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 - /* virtual range */ - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 -+ - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -- /* query pin memory capability */ -- #define AMDGPU_INFO_CAPABILITY_PIN_MEM 0x01 -+/* query pin memory capability */ -+#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -@@ -574,9 +575,6 @@ struct drm_amdgpu_info { - uint32_t _pad; - } virtual_range; - -- struct { -- uint64_t type; -- } query_capability; - }; - }; - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch deleted file mode 100644 index 4e0bc1ae..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch +++ /dev/null @@ -1,143 +0,0 @@ -From c8b1ce6872eaf7793065b0e4ed308b2a92032f95 Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 26 Nov 2015 17:01:07 +0800 -Subject: [PATCH 043/117] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -userspace needs to know if the user memory is from BO or malloc. - -Change-Id: Ie2dbc13f1c02bc0a996f64f9db83a21da63c1d70 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu.h | 24 ++++++++++++++++++++++++ - amdgpu/amdgpu_bo.c | 37 +++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 12 ++++++++++++ - 3 files changed, 73 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index baae113..4925056 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -672,6 +672,30 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, - amdgpu_bo_handle *buf_handle); - - /** -+ * Validate if the user memory comes from BO -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param cpu - [in] CPU address of user allocated memory which we -+ * want to map to GPU address space (make GPU accessible) -+ * (This address must be correctly aligned). -+ * \param size - [in] Size of allocation (must be correctly aligned) -+ * \param buf_handle - [out] Buffer handle for the userptr memory -+ * if the user memory is not from BO, the buf_handle will be NULL. -+ * \param offset_in_bo - [out] offset in this BO for this user memory -+ * -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, -+ void *cpu, -+ uint64_t size, -+ amdgpu_bo_handle *buf_handle, -+ uint64_t *offset_in_bo); -+ -+ -+/** - * Free previosuly allocated memory - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index d30fd1e..ff78039 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -529,6 +529,43 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, - } - } - -+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, -+ void *cpu, -+ uint64_t size, -+ amdgpu_bo_handle *buf_handle, -+ uint64_t *offset_in_bo) -+{ -+ int r; -+ struct amdgpu_bo *bo; -+ struct drm_amdgpu_gem_find_bo args; -+ -+ args.addr = (uintptr_t)cpu; -+ args.size = size; -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_FIND_BO, -+ &args, sizeof(args)); -+ if (r) -+ return r; -+ if (args.handle == 0) -+ return -EINVAL; -+ bo = util_hash_table_get(dev->bo_handles, -+ (void*)(uintptr_t)args.handle); -+ if (!bo) { -+ bo = calloc(1, sizeof(struct amdgpu_bo)); -+ if (!bo) -+ return -ENOMEM; -+ atomic_set(&bo->refcount, 1); -+ bo->dev = dev; -+ bo->alloc_size = size; -+ bo->handle = args.handle; -+ } else -+ atomic_inc(&bo->refcount); -+ -+ *buf_handle = bo; -+ *offset_in_bo = args.offset; -+ return r; -+} -+ -+ - int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, - void *cpu, - uint64_t size, -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 050e7fe..e07904c 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -47,6 +47,7 @@ - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 - #define DRM_AMDGPU_WAIT_FENCES 0x12 -+#define DRM_AMDGPU_GEM_FIND_BO 0x13 - - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) - #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -61,6 +62,7 @@ - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) -+#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -201,6 +203,16 @@ struct drm_amdgpu_gem_userptr { - uint32_t handle; - }; - -+struct drm_amdgpu_gem_find_bo { -+ uint64_t addr; -+ uint64_t size; -+ uint32_t flags; -+ /* Resulting GEM handle */ -+ uint32_t handle; -+ /* offset in bo */ -+ uint64_t offset; -+}; -+ - /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ - #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 - #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0044-amdgpu-support-alloc-va-from-range.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0044-amdgpu-support-alloc-va-from-range.patch deleted file mode 100644 index 61ce6f88..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0044-amdgpu-support-alloc-va-from-range.patch +++ /dev/null @@ -1,265 +0,0 @@ -From 6cac1ca7faba752980ae58e4b10aef5b89c097dd Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 4 Feb 2016 09:42:45 +0800 -Subject: [PATCH 044/117] amdgpu: support alloc va from range - -Change-Id: Ib41ca6a99ce500fe783a1b1650f25be9cebec83a -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu.h | 51 +++++++++++++++ - amdgpu/amdgpu_vamgr.c | 169 ++++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 220 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 4925056..455f388 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -1226,6 +1226,57 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - uint64_t flags); - - /** -+ * Allocate virtual address range in client defined range -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param va_range_type - \c [in] Type of MC va range from which to allocate -+ * \param size - \c [in] Size of range. Size must be correctly* aligned. -+ * It is client responsibility to correctly aligned size based on the future -+ * usage of allocated range. -+ * \param va_base_alignment - \c [in] Overwrite base address alignment -+ * requirement for GPU VM MC virtual -+ * address assignment. Must be multiple of size alignments received as -+ * 'amdgpu_buffer_size_alignments'. -+ * If 0 use the default one. -+ * \param va_base_required - \c [in] Specified required va base address. -+ * If 0 then library choose available one between [va_base_min, va_base_max]. -+ * If !0 value will be passed and those value already "in use" then -+ * corresponding error status will be returned. -+ * \param va_base_min- \c [in] Specified required va range min address. -+ * valid if va_base_required is 0 -+ * \param va_base_max - \c [in] Specified required va range max address. -+ * valid if va_base_required is 0 -+ * \param va_base_allocated - \c [out] On return: Allocated VA base to be used -+ * by client. -+ * \param va_range_handle - \c [out] On return: Handle assigned to allocation -+ * \param flags - \c [in] flags for special VA range -+ * -+ * \return 0 on success\n -+ * >0 - AMD specific error code\n -+ * <0 - Negative POSIX Error code -+ * -+ * \notes \n -+ * It is client responsibility to correctly handle VA assignments and usage. -+ * Neither kernel driver nor libdrm_amdpgu are able to prevent and -+ * detect wrong va assignemnt. -+ * -+ * It is client responsibility to correctly handle multi-GPU cases and to pass -+ * the corresponding arrays of all devices handles where corresponding VA will -+ * be used. -+ * -+*/ -+int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, -+ enum amdgpu_gpu_va_range va_range_type, -+ uint64_t size, -+ uint64_t va_base_alignment, -+ uint64_t va_base_required, -+ uint64_t va_range_min, -+ uint64_t va_range_max, -+ uint64_t *va_base_allocated, -+ amdgpu_va_handle *va_range_handle, -+ uint64_t flags); -+ -+/** - * Free previously allocated virtual address range - * - * -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 973274d..82653e9 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -169,6 +169,94 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - return offset; - } - -+static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint64_t size, -+ uint64_t alignment, uint64_t range_min, uint64_t range_max) -+{ -+ struct amdgpu_bo_va_hole *hole, *n; -+ uint64_t offset = 0, waste = 0; -+ -+ if (mgr->va_min >= range_max || -+ mgr->va_max <= range_min) -+ return AMDGPU_INVALID_VA_ADDRESS; -+ -+ alignment = MAX2(alignment, mgr->va_alignment); -+ size = ALIGN(size, mgr->va_alignment); -+ -+ pthread_mutex_lock(&mgr->bo_va_mutex); -+ /* TODO: using more appropriate way to track the holes */ -+ /* first look for a hole */ -+ LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { -+ if (hole->offset > range_max || -+ hole->offset + hole->size < range_min || -+ (hole->offset > range_min && hole->offset + size > range_max) || -+ (hole->offset < range_min && range_min + size > hole->offset + hole->size) || -+ hole->size < size) -+ continue; -+ offset = hole->offset; -+ waste = offset % alignment; -+ waste = waste ? alignment - waste : 0; -+ offset += waste; -+ if (offset >= (hole->offset + hole->size)) { -+ continue; -+ } -+ -+ if (!waste && hole->size == size) { -+ offset = hole->offset; -+ list_del(&hole->list); -+ free(hole); -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; -+ } -+ if ((hole->size - waste) > size) { -+ if (waste) { -+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); -+ n->size = waste; -+ n->offset = hole->offset; -+ list_add(&n->list, &hole->list); -+ } -+ hole->size -= (size + waste); -+ hole->offset += size + waste; -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; -+ } -+ if ((hole->size - waste) == size) { -+ hole->size = waste; -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; -+ } -+ } -+ -+ if (mgr->va_offset > range_max) { -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return AMDGPU_INVALID_VA_ADDRESS; -+ } else if (mgr->va_offset > range_min) { -+ offset = mgr->va_offset; -+ waste = offset % alignment; -+ waste = waste ? alignment - waste : 0; -+ if (offset + waste + size > range_max) { -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return AMDGPU_INVALID_VA_ADDRESS; -+ } -+ } else { -+ offset = mgr->va_offset; -+ waste = range_min % alignment; -+ waste = waste ? alignment - waste : 0; -+ waste += range_min - offset ; -+ } -+ -+ if (waste) { -+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); -+ n->size = waste; -+ n->offset = offset; -+ list_add(&n->list, &mgr->va_holes); -+ } -+ -+ offset += waste; -+ mgr->va_offset = size + offset; -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; -+} -+ - drm_private void - amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) - { -@@ -294,6 +382,87 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - return 0; - } - -+static int _amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, -+ enum amdgpu_gpu_va_range va_range_type, -+ uint64_t size, -+ uint64_t va_base_alignment, -+ uint64_t va_range_min, -+ uint64_t va_range_max, -+ uint64_t *va_base_allocated, -+ amdgpu_va_handle *va_range_handle, -+ uint64_t flags) -+{ -+ struct amdgpu_bo_va_mgr *vamgr; -+ -+ if (amdgpu_gpu_va_range_svm == va_range_type) { -+ vamgr = &vamgr_svm; -+ if (!vamgr->valid) -+ return -EINVAL; -+ } -+ else if (flags & AMDGPU_VA_RANGE_32_BIT) -+ vamgr = &dev->vamgr_32; -+ else -+ vamgr = &dev->vamgr; -+ -+ va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); -+ size = ALIGN(size, vamgr->va_alignment); -+ -+ *va_base_allocated = amdgpu_vamgr_find_va_in_range(vamgr, size, -+ va_base_alignment, va_range_min, va_range_max); -+ -+ if (!(flags & AMDGPU_VA_RANGE_32_BIT) && -+ (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { -+ /* fallback to 32bit address */ -+ vamgr = &dev->vamgr_32; -+ *va_base_allocated = amdgpu_vamgr_find_va_in_range(vamgr, size, -+ va_base_alignment, va_range_min, va_range_max); -+ } -+ -+ if (*va_base_allocated != AMDGPU_INVALID_VA_ADDRESS) { -+ struct amdgpu_va* va; -+ va = calloc(1, sizeof(struct amdgpu_va)); -+ if(!va){ -+ amdgpu_vamgr_free_va(vamgr, *va_base_allocated, size); -+ return -ENOMEM; -+ } -+ va->dev = dev; -+ va->address = *va_base_allocated; -+ va->size = size; -+ va->range = va_range_type; -+ va->vamgr = vamgr; -+ *va_range_handle = va; -+ } else { -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, -+ enum amdgpu_gpu_va_range va_range_type, -+ uint64_t size, -+ uint64_t va_base_alignment, -+ uint64_t va_base_required, -+ uint64_t va_range_min, -+ uint64_t va_range_max, -+ uint64_t *va_base_allocated, -+ amdgpu_va_handle *va_range_handle, -+ uint64_t flags) -+{ -+ if (va_base_required) -+ return amdgpu_va_range_alloc(dev, va_range_type, -+ size, va_base_alignment, -+ va_base_required, va_base_allocated, -+ va_range_handle, flags); -+ else -+ return _amdgpu_va_range_alloc_in_range(dev, -+ va_range_type, size, -+ va_base_alignment, -+ va_range_min, va_range_max, -+ va_base_allocated, -+ va_range_handle, flags); -+} -+ - int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) - { - if(!va_range_handle || !va_range_handle->address) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0045-tests-amdgpu-add-alloc-va-from-range-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0045-tests-amdgpu-add-alloc-va-from-range-test.patch deleted file mode 100644 index fe892fc5..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0045-tests-amdgpu-add-alloc-va-from-range-test.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 9622440df581fd23d8dbf5fb2188b1fdad524b6f Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 4 Feb 2016 09:54:32 +0800 -Subject: [PATCH 045/117] tests/amdgpu: add alloc va from range test - -Change-Id: I22fa0255ad8f0b7e881a6d4d2de6a054ce3572db -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - tests/amdgpu/basic_tests.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 408a432..78388a9 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -51,6 +51,7 @@ static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); - static void amdgpu_svm_test(void); - static void amdgpu_multi_svm_test(void); -+static void amdgpu_va_range_test(void); - - CU_TestInfo basic_tests[] = { - { "Query Info Test", amdgpu_query_info_test }, -@@ -63,6 +64,7 @@ CU_TestInfo basic_tests[] = { - { "SW semaphore Test", amdgpu_semaphore_test }, - { "SVM Test", amdgpu_svm_test }, - { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, -+ { "VA range Test", amdgpu_va_range_test}, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) -@@ -1380,3 +1382,55 @@ static void amdgpu_multi_svm_test(void) - - amdgpu_svm_deinit(device_handles[0]); - } -+ -+#define VA_RANGE_TEST_CNT 66 -+#define VA_RANGE_TEST_INT_BEL_CNT 20 -+#define VA_RANGE_TEST_INT_ABO_CNT 20 -+static void amdgpu_va_range_test(void) -+{ -+ amdgpu_va_handle va_handles[VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT+VA_RANGE_TEST_INT_ABO_CNT]; -+ uint64_t va; -+ int i, r; -+ -+ amdgpu_vprintf("\n"); -+ amdgpu_vprintf(" Testing to alloc and free VA in user defined range.\n"); -+ memset(va_handles, 0, sizeof(va_handles)); -+ for (i = 0; i < VA_RANGE_TEST_CNT; i++) { -+ r = amdgpu_va_range_alloc_in_range(device_handle, -+ amdgpu_gpu_va_range_general, -+ 0x1000000, 9, 0, -+ 0x800000000, 0x840000000, -+ &va, &va_handles[i], 0); -+ amdgpu_vprintf(" test loop %d, alloc %s\n", i, (r==0)? "success" : "fail"); -+ if (!r) -+ amdgpu_vprintf(" alloc on addr %#llx\n", va); -+ CU_ASSERT_TRUE((r == 0) || -+ (r && i>=(0x840000000-0x800000000)/0x1000000)); -+ } -+ for (i = VA_RANGE_TEST_CNT; i < VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT; i++) { -+ r = amdgpu_va_range_alloc_in_range(device_handle, -+ amdgpu_gpu_va_range_general, -+ 0x1000000, 9, 0, -+ 0x600000000, 0x840000000, -+ &va, &va_handles[i], 0); -+ amdgpu_vprintf(" test loop %d, alloc %s\n", i, (r==0)? "success" : "fail"); -+ if (!r) -+ amdgpu_vprintf(" alloc on addr %#llx\n", va); -+ CU_ASSERT_TRUE (r == 0 && va <=0x800000000); -+ } -+ for (i = VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT; i < VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT+VA_RANGE_TEST_INT_ABO_CNT; i++) { -+ r = amdgpu_va_range_alloc_in_range(device_handle, -+ amdgpu_gpu_va_range_general, -+ 0x1000000, 9, 0, -+ 0x800000000, 0x940000000, -+ &va, &va_handles[i], 0); -+ amdgpu_vprintf(" test loop %d, alloc %s\n", i, (r==0)? "success" : "fail"); -+ if (!r) -+ amdgpu_vprintf(" alloc on addr %#llx\n", va); -+ CU_ASSERT_TRUE (r == 0 && va >= 0x840000000); -+ } -+ for (i = 0; i < VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT+VA_RANGE_TEST_INT_ABO_CNT; i++) { -+ r = amdgpu_va_range_free(va_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0046-amdgpu-fix-for-submition-with-no-ibs.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0046-amdgpu-fix-for-submition-with-no-ibs.patch deleted file mode 100644 index 0af5f509..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0046-amdgpu-fix-for-submition-with-no-ibs.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 8494f5ecd3dae4266805c809f894495a29e73b38 Mon Sep 17 00:00:00 2001 -From: Ken Wang <Qingqing.Wang@amd.com> -Date: Thu, 4 Feb 2016 13:52:22 +0800 -Subject: [PATCH 046/117] amdgpu: fix for submition with no ibs - -Change-Id: I0b582ff0021c02fad9d77d51971a48d9ee5d1146 -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> -Acked-by: Alex Deucher <Alexander.Deucher@amd.com> ---- - amdgpu/amdgpu_cs.c | 8 ++++++++ - amdgpu/amdgpu_internal.h | 1 + - 2 files changed, 9 insertions(+) - -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 896352b..0c9bcc4 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -190,6 +190,10 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - return -EINVAL; - if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT) - return -EINVAL; -+ if (ibs_request->number_of_ibs == 0) { -+ ibs_request->seq_no = AMDGPU_NULL_SUBMIT_SEQ; -+ return 0; -+ } - user_fence = (ibs_request->fence_info.handle != NULL); - - size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1; -@@ -422,6 +426,10 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - return -EINVAL; - if (fence->ring >= AMDGPU_CS_MAX_RINGS) - return -EINVAL; -+ if (fence->fence == AMDGPU_NULL_SUBMIT_SEQ) { -+ *expired = true; -+ return 0; -+ } - - *expired = false; - -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 3760f94..1160a12 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -44,6 +44,7 @@ - #define ROUND_DOWN(x, y) ((x) & ~__round_mask(x, y)) - - #define AMDGPU_INVALID_VA_ADDRESS 0xffffffffffffffff -+#define AMDGPU_NULL_SUBMIT_SEQ 0 - - struct amdgpu_bo_va_hole { - struct list_head list; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0047-tests-amdgpu-move-va_range_test-above-svm_test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0047-tests-amdgpu-move-va_range_test-above-svm_test.patch deleted file mode 100644 index e2b547cd..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0047-tests-amdgpu-move-va_range_test-above-svm_test.patch +++ /dev/null @@ -1,32 +0,0 @@ -From c7c7f25b214b694541d69bc3fb1a096a1725d6fb Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Fri, 5 Feb 2016 13:20:27 +0800 -Subject: [PATCH 047/117] tests/amdgpu: move va_range_test above svm_test - -svm_test won't release va range at exit. va_range_test would fail as the -desired range is occupied. - -Change-Id: I36bb3c23f185baa26a383e02a87a0b02f613e2d0 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> ---- - tests/amdgpu/basic_tests.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 78388a9..b7e6270 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -62,9 +62,9 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, - { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, - { "SW semaphore Test", amdgpu_semaphore_test }, -+ { "VA range Test", amdgpu_va_range_test}, - { "SVM Test", amdgpu_svm_test }, - { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, -- { "VA range Test", amdgpu_va_range_test}, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0048-amdgpu-add-the-function-to-get-the-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0048-amdgpu-add-the-function-to-get-the-marketing-name.patch deleted file mode 100644 index dc1572c1..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0048-amdgpu-add-the-function-to-get-the-marketing-name.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 36a9c41b7b44bc8dee072733f1fc944e4bf66703 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Fri, 4 Mar 2016 13:00:09 +0800 -Subject: [PATCH 048/117] amdgpu: add the function to get the marketing name - -Change-Id: I6031d8012531de89d604f24e1d1bd1743012f980 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu.h | 10 +++++ - amdgpu/amdgpu_asic_id.h | 116 ++++++++++++++++++++++++++++++++++++++++++++++++ - amdgpu/amdgpu_device.c | 15 +++++++ - 3 files changed, 141 insertions(+) - create mode 100644 amdgpu/amdgpu_asic_id.h - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 455f388..5415bd0 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -1437,4 +1437,14 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, - */ - int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); - -+/** -+ * Get the ASIC marketing name -+ * -+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -+ * -+ * \return the constant string of the marketing name -+ * "NULL" means the ASIC is not found -+*/ -+const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); -+ - #endif /* #ifdef _AMDGPU_H_ */ -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -new file mode 100644 -index 0000000..4130de6 ---- /dev/null -+++ b/amdgpu/amdgpu_asic_id.h -@@ -0,0 +1,116 @@ -+struct amdgpu_asic_id_table_t { -+ uint32_t did; -+ uint32_t rid; -+ char marketing_name[64]; -+} const amdgpu_asic_id_table [] = { -+ {0x6600, 0x0, "AMD Radeon HD 8600/8700M"}, -+ {0x6600, 0x81, "AMD Radeon (TM) R7 M370"}, -+ {0x6601, 0x0, "AMD Radeon (TM) HD 8500M/8700M"}, -+ {0x6604, 0x0, "AMD Radeon R7 M265 Series"}, -+ {0x6604, 0x81, "AMD Radeon (TM) R7 M350"}, -+ {0x6605, 0x0, "AMD Radeon R7 M260 Series"}, -+ {0x6605, 0x81, "AMD Radeon (TM) R7 M340"}, -+ {0x6606, 0x0, "AMD Radeon HD 8790M"}, -+ {0x6607, 0x0, "AMD Radeon (TM) HD8530M"}, -+ {0x6608, 0x0, "AMD FirePro W2100"}, -+ {0x6610, 0x0, "AMD Radeon HD 8600 Series"}, -+ {0x6610, 0x81, "AMD Radeon (TM) R7 350"}, -+ {0x6610, 0x83, "AMD Radeon (TM) R5 340"}, -+ {0x6611, 0x0, "AMD Radeon HD 8500 Series"}, -+ {0x6613, 0x0, "AMD Radeon HD 8500 series"}, -+ {0x6617, 0xC7, "AMD Radeon R7 240 Series"}, -+ {0x6640, 0x0, "AMD Radeon HD 8950"}, -+ {0x6640, 0x80, "AMD Radeon (TM) R9 M380"}, -+ {0x6646, 0x0, "AMD Radeon R9 M280X"}, -+ {0x6646, 0x80, "AMD Radeon (TM) R9 M385"}, -+ {0x6647, 0x0, "AMD Radeon R9 M270X"}, -+ {0x6647, 0x80, "AMD Radeon (TM) R9 M380"}, -+ {0x6649, 0x0, "AMD FirePro W5100"}, -+ {0x6658, 0x0, "AMD Radeon R7 200 Series"}, -+ {0x665C, 0x0, "AMD Radeon HD 7700 Series"}, -+ {0x665D, 0x0, "AMD Radeon R7 200 Series"}, -+ {0x665F, 0x81, "AMD Radeon (TM) R7 300 Series"}, -+ {0x6660, 0x0, "AMD Radeon HD 8600M Series"}, -+ {0x6660, 0x81, "AMD Radeon (TM) R5 M335"}, -+ {0x6660, 0x83, "AMD Radeon (TM) R5 M330"}, -+ {0x6663, 0x0, "AMD Radeon HD 8500M Series"}, -+ {0x6663, 0x83, "AMD Radeon (TM) R5 M320"}, -+ {0x6664, 0x0, "AMD Radeon R5 M200 Series"}, -+ {0x6665, 0x0, "AMD Radeon R5 M200 Series"}, -+ {0x6665, 0x83, "AMD Radeon (TM) R5 M320"}, -+ {0x6667, 0x0, "AMD Radeon R5 M200 Series"}, -+ {0x666F, 0x0, "AMD Radeon HD 8500M"}, -+ {0x6780, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"}, -+ {0x678A, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"}, -+ {0x6798, 0x0, "AMD Radeon HD 7900 Series"}, -+ {0x679A, 0x0, "AMD Radeon HD 7900 Series"}, -+ {0x679B, 0x0, "AMD Radeon HD 7900 Series"}, -+ {0x679E, 0x0, "AMD Radeon HD 7800 Series"}, -+ {0x67A0, 0x0, "HAWAII XTGL (67A0)"}, -+ {0x67A1, 0x0, "HAWAII GL40 (67A1)"}, -+ {0x67B0, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x67B0, 0x80, "AMD Radeon (TM) R9 390 Series"}, -+ {0x67B1, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x67B1, 0x80, "AMD Radeon (TM) R9 390 Series"}, -+ {0x67B9, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x6800, 0x0, "AMD Radeon HD 7970M"}, -+ {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, -+ {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, -+ {0x6809, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, -+ {0x6810, 0x0, "AMD Radeon(TM) HD 8800 Series"}, -+ {0x6810, 0x81, "AMD Radeon (TM) R7 370 Series"}, -+ {0x6811, 0x0, "AMD Radeon(TM) HD8800 Series"}, -+ {0x6811, 0x81, "AMD Radeon (TM) R7 300 Series"}, -+ {0x6818, 0x0, "AMD Radeon HD 7800 Series"}, -+ {0x6819, 0x0, "AMD Radeon HD 7800 Series"}, -+ {0x6820, 0x0, "AMD Radeon HD 8800M Series"}, -+ {0x6820, 0x81, "AMD Radeon (TM) R9 M375"}, -+ {0x6820, 0x83, "AMD Radeon (TM) R9 M375X"}, -+ {0x6821, 0x0, "AMD Radeon HD 8800M Series"}, -+ {0x6821, 0x87, "AMD Radeon (TM) R7 M380"}, -+ {0x6821, 0x83, "AMD Radeon R9 (TM) M370X"}, -+ {0x6822, 0x0, "AMD Radeon E8860"}, -+ {0x6823, 0x0, "AMD Radeon HD 8800M Series"}, -+ {0x6825, 0x0, "AMD Radeon HD 7800M Series"}, -+ {0x6827, 0x0, "AMD Radeon HD 7800M Series"}, -+ {0x6828, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, -+ {0x682B, 0x0, "AMD Radeon HD 8800M Series"}, -+ {0x682B, 0x87, "AMD Radeon (TM) R9 M360"}, -+ {0x682C, 0x0, "AMD FirePro W4100"}, -+ {0x682D, 0x0, "AMD Radeon HD 7700M Series"}, -+ {0x682F, 0x0, "AMD Radeon HD 7700M Series"}, -+ {0x6835, 0x0, "AMD Radeon R7 Series / HD 9000 Series"}, -+ {0x6837, 0x0, "AMD Radeon HD7700 Series"}, -+ {0x683D, 0x0, "AMD Radeon HD 7700 Series"}, -+ {0x683F, 0x0, "AMD Radeon HD 7700 Series"}, -+ {0x6900, 0x0, "AMD Radeon R7 M260"}, -+ {0x6900, 0x81, "AMD Radeon (TM) R7 M360"}, -+ {0x6900, 0x83, "AMD Radeon (TM) R7 M340"}, -+ {0x6901, 0x0, "AMD Radeon R5 M255"}, -+ {0x6907, 0x0, "AMD Radeon R5 M255"}, -+ {0x6907, 0x87, "AMD Radeon (TM) R5 M315"}, -+ {0x6920, 0x0, "AMD RADEON R9 M395X"}, -+ {0x6920, 0x1, "AMD RADEON R9 M390X"}, -+ {0x6921, 0x0, "AMD Radeon R9 M295X"}, -+ {0x6929, 0x0, "AMD FirePro S7150"}, -+ {0x692B, 0x0, "AMD FirePro W7100"}, -+ {0x6938, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x6938, 0xF0, "AMD Radeon R9 200 Series"}, -+ {0x6938, 0xF1, "AMD Radeon (TM) R9 380 Series"}, -+ {0x6939, 0xF0, "AMD Radeon R9 200 Series"}, -+ {0x6939, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x6939, 0xF1, "AMD Radeon (TM) R9 380 Series"}, -+ {0x7300, 0xC8, "AMD Radeon (TM) R9 Fury Series"}, -+ {0x7300, 0xCB, "AMD Radeon (TM) R9 Fury Series"}, -+ {0x7300, 0xCA, "AMD Radeon (TM) R9 Fury Series"}, -+ {0x9874, 0xC4, "AMD Radeon R7 Graphics"}, -+ {0x9874, 0xC5, "AMD Radeon R6 Graphics"}, -+ {0x9874, 0xC6, "AMD Radeon R6 Graphics"}, -+ {0x9874, 0xC7, "AMD Radeon R5 Graphics"}, -+ {0x9874, 0x81, "AMD Radeon R6 Graphics"}, -+ {0x9874, 0x87, "AMD Radeon R5 Graphics"}, -+ {0x9874, 0x85, "AMD Radeon R6 Graphics"}, -+ {0x9874, 0x84, "AMD Radeon R7 Graphics"}, -+ -+ {0x0000, 0x0, "\0"}, -+}; -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index b517b1a..8f1f781 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -44,6 +44,7 @@ - #include "amdgpu_internal.h" - #include "util_hash_table.h" - #include "util_math.h" -+#include "amdgpu_asic_id.h" - - #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) - #define UINT_TO_PTR(x) ((void *)((intptr_t)(x))) -@@ -293,3 +294,17 @@ int amdgpu_device_deinitialize(amdgpu_device_handle dev) - amdgpu_device_reference(&dev, NULL); - return 0; - } -+ -+const char *amdgpu_get_marketing_name(amdgpu_device_handle dev) -+{ -+ const struct amdgpu_asic_id_table_t *t = amdgpu_asic_id_table; -+ -+ while (t->did) { -+ if ((t->did == dev->info.asic_id) && -+ (t->rid == dev->info.pci_rev_id)) -+ return t->marketing_name; -+ t++; -+ } -+ -+ return NULL; -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch deleted file mode 100644 index dc93abd6..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch +++ /dev/null @@ -1,59 +0,0 @@ -From de7234f8ae699b3c78043a19e32fc7a9596fbeac Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Tue, 8 Mar 2016 17:57:06 +0800 -Subject: [PATCH 049/117] tests/amdgpu: remove none amdgpu devices for hybrid - GPU platforms -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I5991e74ddea212bde4954924de12b26c1ac54936 -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/amdgpu_test.c | 22 +++++++++++++++++++++- - 1 file changed, 21 insertions(+), 1 deletion(-) - -diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c -index 46f55c7..dccf221 100644 ---- a/tests/amdgpu/amdgpu_test.c -+++ b/tests/amdgpu/amdgpu_test.c -@@ -136,7 +136,7 @@ static const char options[] = "hlvws:t:"; - int main(int argc, char **argv) - { - int c; /* Character received from getopt */ -- int i = 0; -+ int i = 0, j = 0; - int suite_id = -1; /* By default run everything */ - int test_id = -1; /* By default run all tests in the suite */ - CU_pSuite pSuite = NULL; -@@ -210,6 +210,26 @@ int main(int argc, char **argv) - } - drmFreeDevices(devices, num_devices); - -+ /* remove none amdgpu devices */ -+ for (i = 0; i < num_devices; i++) { -+ drmVersionPtr retval = drmGetVersion(drm_amdgpu[i]); -+ if (retval && !strcmp("amdgpu", retval->name)) { -+ if (i != j) { -+ drm_amdgpu[j] = drm_amdgpu[i]; -+ drm_amdgpu[i] = -1; -+ } -+ j++; -+ } -+ else { -+ close(drm_amdgpu[i]); -+ drm_amdgpu[i] = -1; -+ } -+ } -+ if (drm_amdgpu[0] < 0) { -+ perror("no amdgpu device found"); -+ exit(EXIT_FAILURE); -+ } -+ - /** Display version of DRM driver */ - drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0050-amdgpu-tests-Fiji-VCE-is-one-instance.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0050-amdgpu-tests-Fiji-VCE-is-one-instance.patch deleted file mode 100644 index b6221c08..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0050-amdgpu-tests-Fiji-VCE-is-one-instance.patch +++ /dev/null @@ -1,60 +0,0 @@ -From c246e19bebdefd47f4d9f676391722ca5c98f2c2 Mon Sep 17 00:00:00 2001 -From: Sonny Jiang <sonny.jiang@amd.com> -Date: Thu, 18 Feb 2016 10:59:56 -0500 -Subject: [PATCH 050/117] amdgpu/tests: Fiji VCE is one instance - -Change-Id: I7a00160cfa3510ae072964981c921bf49c707155 -Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> -Reviewed-by: Leo Liu <leo.liu@amd.com> ---- - tests/amdgpu/vce_tests.c | 20 ++++++++++++-------- - 1 file changed, 12 insertions(+), 8 deletions(-) - -diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c -index 32fc001..4915170 100644 ---- a/tests/amdgpu/vce_tests.c -+++ b/tests/amdgpu/vce_tests.c -@@ -65,6 +65,7 @@ static amdgpu_device_handle device_handle; - static uint32_t major_version; - static uint32_t minor_version; - static uint32_t family_id; -+static uint32_t vce_harvest_config; - - static amdgpu_context_handle context_handle; - static amdgpu_bo_handle ib_handle; -@@ -97,6 +98,7 @@ int suite_vce_tests_init(void) - return CUE_SINIT_FAILED; - - family_id = device_handle->info.family_id; -+ vce_harvest_config = device_handle->info.vce_harvest_config; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) -@@ -440,14 +442,16 @@ static void amdgpu_cs_vce_encode(void) - check_result(&enc); - - /* two instances */ -- enc.two_instance = true; -- vce_taskinfo[2] = 0x83; -- vce_taskinfo[4] = 1; -- amdgpu_cs_vce_encode_idr(&enc); -- vce_taskinfo[2] = 0xffffffff; -- vce_taskinfo[4] = 2; -- amdgpu_cs_vce_encode_p(&enc); -- check_result(&enc); -+ if (vce_harvest_config == 0) { -+ enc.two_instance = true; -+ vce_taskinfo[2] = 0x83; -+ vce_taskinfo[4] = 1; -+ amdgpu_cs_vce_encode_idr(&enc); -+ vce_taskinfo[2] = 0xffffffff; -+ vce_taskinfo[4] = 2; -+ amdgpu_cs_vce_encode_p(&enc); -+ check_result(&enc); -+ } - } else { - vce_taskinfo[3] = 3; - vce_encode[16] = 0; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0052-amdgpu-hybrid-update-the-gpu-marketing-name-table.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0052-amdgpu-hybrid-update-the-gpu-marketing-name-table.patch deleted file mode 100644 index 889375a3..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0052-amdgpu-hybrid-update-the-gpu-marketing-name-table.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 398bbb4523b13a9752785dd527e530cb07026762 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Mon, 16 May 2016 09:33:27 +0800 -Subject: [PATCH 052/117] amdgpu: [hybrid] update the gpu marketing name table - -Change-Id: I4e680fa71714f886e233e1ccdbb3a4121e7c8bc2 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 4130de6..c29a27e 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -22,7 +22,7 @@ struct amdgpu_asic_id_table_t { - {0x6640, 0x0, "AMD Radeon HD 8950"}, - {0x6640, 0x80, "AMD Radeon (TM) R9 M380"}, - {0x6646, 0x0, "AMD Radeon R9 M280X"}, -- {0x6646, 0x80, "AMD Radeon (TM) R9 M385"}, -+ {0x6646, 0x80, "AMD Radeon (TM) R9 M470X"}, - {0x6647, 0x0, "AMD Radeon R9 M270X"}, - {0x6647, 0x80, "AMD Radeon (TM) R9 M380"}, - {0x6649, 0x0, "AMD FirePro W5100"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0053-Hybrid-Version-16.30.2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0053-Hybrid-Version-16.30.2.patch deleted file mode 100644 index e515dff4..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0053-Hybrid-Version-16.30.2.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 831fa03789a7a929b97ddbbe416b9cf96171c76a Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Tue, 17 May 2016 11:05:20 +0800 -Subject: [PATCH 053/117] Hybrid Version: 16.30.2 - -Change-Id: I554db242c9d58483fd197962d75e2d9512ff9390 ---- - .version.hybrid | 3 +++ - 1 file changed, 3 insertions(+) - create mode 100644 .version.hybrid - -diff --git a/.version.hybrid b/.version.hybrid -new file mode 100644 -index 0000000..1385b45 ---- /dev/null -+++ b/.version.hybrid -@@ -0,0 +1,3 @@ -+HYBRID_VERSION_MAJOR = 16 -+HYBRID_VERSION_MINOR = 30 -+HYBRID_VERSION_PATCH = 2 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0054-tests-amdgpu-add-interface-to-adapt-firmware-require.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0054-tests-amdgpu-add-interface-to-adapt-firmware-require.patch deleted file mode 100644 index d9a45179..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0054-tests-amdgpu-add-interface-to-adapt-firmware-require.patch +++ /dev/null @@ -1,41 +0,0 @@ -From f50daceb4d345174ed24a0320edf78fe738f7634 Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Thu, 17 Mar 2016 11:30:57 -0400 -Subject: [PATCH 054/117] tests/amdgpu: add interface to adapt firmware - requirement -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Leo Liu <leo.liu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> - -Conflicts: - tests/amdgpu/cs_tests.c - -Change-Id: I6cd8e626c9936a5ad41a971daa422142cb586b89 ---- - tests/amdgpu/cs_tests.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index dfbf5af..5b487a1 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -267,8 +267,11 @@ static void amdgpu_cs_uvd_decode(void) - CU_ASSERT_EQUAL(r, 0); - - memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg)); -- if (family_id >= AMDGPU_FAMILY_VI) -+ if (family_id >= AMDGPU_FAMILY_VI) { - ptr[0x10] = 7; -+ ptr[0x98] = 0xb0; -+ ptr[0x99] = 0x1; -+ } - - ptr += 4*1024; - memset(ptr, 0, 4*1024); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0055-tests-amdgpu-adapt-to-new-polaris10-11-uvd-fw.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0055-tests-amdgpu-adapt-to-new-polaris10-11-uvd-fw.patch deleted file mode 100644 index 34a6eabc..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0055-tests-amdgpu-adapt-to-new-polaris10-11-uvd-fw.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 08d04097cb45735384e9100c620e044b32779d75 Mon Sep 17 00:00:00 2001 -From: Sonny Jiang <sonny.jiang@amd.com> -Date: Thu, 12 May 2016 12:48:43 -0400 -Subject: [PATCH 055/117] tests/amdgpu: adapt to new polaris10/11 uvd fw - -Change-Id: Ibf5fc9c84f478aa038ba3b8b3a79448d7b03a196 -Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - tests/amdgpu/cs_tests.c | 48 ++++++++++++++++++++++++++++++++++++++++++------ - 1 file changed, 42 insertions(+), 6 deletions(-) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index 5b487a1..2c9c1ae 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -43,6 +43,8 @@ static amdgpu_device_handle device_handle; - static uint32_t major_version; - static uint32_t minor_version; - static uint32_t family_id; -+static uint32_t chip_rev; -+static uint32_t chip_id; - - static amdgpu_context_handle context_handle; - static amdgpu_bo_handle ib_handle; -@@ -78,6 +80,9 @@ int suite_cs_tests_init(void) - return CUE_SINIT_FAILED; - - family_id = device_handle->info.family_id; -+ /* VI asic POLARIS10/11 have specific external_rev_id */ -+ chip_rev = device_handle->info.chip_rev; -+ chip_id = device_handle->info.chip_external_rev; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) -@@ -200,8 +205,17 @@ static void amdgpu_cs_uvd_create(void) - CU_ASSERT_EQUAL(r, 0); - - memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg)); -- if (family_id >= AMDGPU_FAMILY_VI) -+ if (family_id >= AMDGPU_FAMILY_VI) { - ((uint8_t*)msg)[0x10] = 7; -+ /* chip polaris 10/11 */ -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { -+ /* dpb size */ -+ ((uint8_t*)msg)[0x28] = 0x00; -+ ((uint8_t*)msg)[0x29] = 0x94; -+ ((uint8_t*)msg)[0x2A] = 0x6B; -+ ((uint8_t*)msg)[0x2B] = 0x00; -+ } -+ } - - r = amdgpu_bo_cpu_unmap(buf_handle); - CU_ASSERT_EQUAL(r, 0); -@@ -230,8 +244,8 @@ static void amdgpu_cs_uvd_create(void) - - static void amdgpu_cs_uvd_decode(void) - { -- const unsigned dpb_size = 15923584, dt_size = 737280; -- uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, dt_addr, it_addr; -+ const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280; -+ uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr; - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; -@@ -269,8 +283,21 @@ static void amdgpu_cs_uvd_decode(void) - memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg)); - if (family_id >= AMDGPU_FAMILY_VI) { - ptr[0x10] = 7; -- ptr[0x98] = 0xb0; -- ptr[0x99] = 0x1; -+ ptr[0x98] = 0x00; -+ ptr[0x99] = 0x02; -+ /* chip polaris10/11 */ -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { -+ /*dpb size */ -+ ptr[0x24] = 0x00; -+ ptr[0x25] = 0x94; -+ ptr[0x26] = 0x6B; -+ ptr[0x27] = 0x00; -+ /*ctx size */ -+ ptr[0x2C] = 0x00; -+ ptr[0x2D] = 0xAF; -+ ptr[0x2E] = 0x50; -+ ptr[0x2F] = 0x00; -+ } - } - - ptr += 4*1024; -@@ -301,6 +328,12 @@ static void amdgpu_cs_uvd_decode(void) - } else - bs_addr = fb_addr + 4*1024; - dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); -+ -+ if ((family_id >= AMDGPU_FAMILY_VI) && -+ (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { -+ ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); -+ } -+ - dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); - - i = 0; -@@ -309,8 +342,11 @@ static void amdgpu_cs_uvd_decode(void) - uvd_cmd(dt_addr, 0x2, &i); - uvd_cmd(fb_addr, 0x3, &i); - uvd_cmd(bs_addr, 0x100, &i); -- if (family_id >= AMDGPU_FAMILY_VI) -+ if (family_id >= AMDGPU_FAMILY_VI) { - uvd_cmd(it_addr, 0x204, &i); -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) -+ uvd_cmd(ctx_addr, 0x206, &i); -+} - ib_cpu[i++] = 0x3BC6; - ib_cpu[i++] = 0x1; - for (; i % 16; ++i) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0056-amdgpu-change-max-allocation.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0056-amdgpu-change-max-allocation.patch deleted file mode 100644 index 03ca1e92..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0056-amdgpu-change-max-allocation.patch +++ /dev/null @@ -1,41 +0,0 @@ -From fca8e6d4d9638158770745d4da5870a131190b3e Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Wed, 23 Mar 2016 10:29:00 +0800 -Subject: [PATCH 056/117] amdgpu: change max allocation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I83f8f33140609d4d2c3e54954cc2dc96eeaec6ba -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - amdgpu/amdgpu_gpu_info.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 133952d..037df32 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -260,7 +260,7 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, - else /* query total vram heap */ - info->heap_size = vram_gtt_info.vram_size; - -- info->max_allocation = vram_gtt_info.vram_cpu_accessible_size; -+ info->max_allocation = vram_gtt_info.vram_size * 3 / 4; - - if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) - r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE, -@@ -275,7 +275,7 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, - break; - case AMDGPU_GEM_DOMAIN_GTT: - info->heap_size = vram_gtt_info.gtt_size; -- info->max_allocation = vram_gtt_info.vram_cpu_accessible_size; -+ info->max_allocation = vram_gtt_info.gtt_size * 3 / 4; - - r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE, - sizeof(info->heap_usage), --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0057-amdgpu-fix-print-format-error-V2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0057-amdgpu-fix-print-format-error-V2.patch deleted file mode 100644 index 251d7200..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0057-amdgpu-fix-print-format-error-V2.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 4dacb4b7d2f3ac211a485d088e7fcc1760af38db Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Mon, 28 Mar 2016 14:30:03 +0800 -Subject: [PATCH 057/117] amdgpu: fix print format error V2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -V2: use "PRIx64" instead of llx - -Change-Id: Idf79d58abe165f26dc6bc900e10fca30ea740509 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-By: Ken Wang <Qingqing.Wang@amd.com> (V1) -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (V2) - -Conflicts: - tests/amdgpu/basic_tests.c ---- - tests/amdgpu/basic_tests.c | 13 +++++++------ - 1 file changed, 7 insertions(+), 6 deletions(-) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index b7e6270..f308e9a 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -28,6 +28,7 @@ - #include <stdio.h> - #include <stdlib.h> - #include <unistd.h> -+#include <inttypes.h> - #ifdef HAVE_ALLOCA_H - # include <alloca.h> - #endif -@@ -273,17 +274,17 @@ static void amdgpu_query_heap_info_test(void) - amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &info); - amdgpu_vprintf("\n Visible VRAM info...\n"); -- amdgpu_vprintf(" size: 0x%x\n", info.heap_size); -- amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); -+ amdgpu_vprintf(" size: 0x%"PRIx64"\n", info.heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", info.heap_usage); - amdgpu_vprintf("\n Invisible VRAM info...\n"); -- amdgpu_vprintf(" size: 0x%x\n", total_vram - info.heap_size); -- amdgpu_vprintf(" usage: 0x%x\n", total_vram_used - info.heap_usage); -+ amdgpu_vprintf(" size: 0x%"PRIx64"\n", total_vram - info.heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", total_vram_used - info.heap_usage); - - amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, - 0, &info); - amdgpu_vprintf("\n GTT info...\n"); -- amdgpu_vprintf(" size: 0x%x\n", info.heap_size); -- amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); -+ amdgpu_vprintf(" size: 0x%"PRIx64"\n", info.heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", info.heap_usage); - } - - static void amdgpu_query_info_test(void) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0058-Hybrid-Version-16.30.3.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0058-Hybrid-Version-16.30.3.patch deleted file mode 100644 index ef974b1e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0058-Hybrid-Version-16.30.3.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 34ac5db6d3e1387de3e69ac3fb61e31c2e02b8f9 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Mon, 30 May 2016 11:13:54 +0800 -Subject: [PATCH 058/117] Hybrid Version: 16.30.3 - -Change-Id: I27ee52f2fa44edc3a4adfea79a0caed9560ed760 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 1385b45..4cabeed 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 30 --HYBRID_VERSION_PATCH = 2 -+HYBRID_VERSION_PATCH = 3 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0059-drm-fix-multi-GPU-drmGetDevices-only-return-one-devi.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0059-drm-fix-multi-GPU-drmGetDevices-only-return-one-devi.patch deleted file mode 100644 index 40ba2ded..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0059-drm-fix-multi-GPU-drmGetDevices-only-return-one-devi.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 9d50d529f35b5ec2e9300bcff55fca1da84f75ec Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Mon, 30 May 2016 21:45:47 +0800 -Subject: [PATCH 059/117] drm: fix multi GPU drmGetDevices only return one - device - -When multi GPU present, after drmFoldDuplicatedDevices -merge same busid deveces, two different devices may be -seperated by zero in local_devices[]. The for loop -should check all local_devices instead of exit when -meet a zero. - -Change-Id: I0b655f795727492bd7886cb60e07832bd9849d89 -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by Jim Qu <Jim.Qu@amd.com> ---- - xf86drm.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/xf86drm.c b/xf86drm.c -index 5f587d9..6689f7c 100644 ---- a/xf86drm.c -+++ b/xf86drm.c -@@ -3267,7 +3267,10 @@ int drmGetDevices(drmDevicePtr devices[], int max_devices) - drmFoldDuplicatedDevices(local_devices, node_count); - - device_count = 0; -- for (i = 0; i < node_count && local_devices[i]; i++) { -+ for (i = 0; i < node_count; i++) { -+ if (!local_devices[i]) -+ continue; -+ - if ((devices != NULL) && (device_count < max_devices)) - devices[device_count] = local_devices[i]; - else --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch deleted file mode 100644 index 42201f1f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch +++ /dev/null @@ -1,32 +0,0 @@ -From e5512b2e226abad4e1719b4de4a7427900bc9317 Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 3 Dec 2015 16:52:33 +0800 -Subject: [PATCH 061/117] amdgpu: add bo handle to hash table when cpu mapping -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: Id79d98877c61510a1986d65befec6ce6713edae7 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_bo.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index ff78039..aa0d001 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -463,7 +463,7 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) - pthread_mutex_unlock(&bo->cpu_access_mutex); - return -errno; - } -- -+ amdgpu_add_handle_to_table(bo); - bo->cpu_ptr = ptr; - bo->cpu_map_count = 1; - pthread_mutex_unlock(&bo->cpu_access_mutex); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch deleted file mode 100644 index 31a20bf2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 52bf3cba5dcb9064c6c174e6a69c0d40cd064594 Mon Sep 17 00:00:00 2001 -From: "monk.liu" <Monk.Liu@amd.com> -Date: Tue, 1 Dec 2015 17:48:18 +0800 -Subject: [PATCH 062/117] amdgpu: cs_wait_fences now can return the first - signaled fence index - -Change-Id: Idf3d3bf0f2d2396a77341f97174d0a173fdd8932 -Signed-off-by: monk.liu <Monk.Liu@amd.com> ---- - amdgpu/amdgpu.h | 3 ++- - amdgpu/amdgpu_cs.c | 12 +++++++++--- - include/drm/amdgpu_drm.h | 3 ++- - tests/amdgpu/basic_tests.c | 2 +- - 4 files changed, 14 insertions(+), 6 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 5415bd0..693d841 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -947,6 +947,7 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - * otherwise, wait at least one fence - * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds - * \param status - \c [out] '1' for signaled, '0' for timeout -+ * \param first - \c [out] the index of the first signaled fence from @fences - * - * \return 0 on success - * <0 - Negative POSIX Error code -@@ -958,7 +959,7 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, - uint32_t fence_count, - bool wait_all, - uint64_t timeout_ns, -- uint32_t *status); -+ uint32_t *status, uint32_t *first); - - /* - * Query / Info API -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 0c9bcc4..b29e8c9 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -447,7 +447,8 @@ static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, - uint32_t fence_count, - bool wait_all, - uint64_t timeout_ns, -- uint32_t *status) -+ uint32_t *status, -+ uint32_t *first) - { - struct drm_amdgpu_fence *drm_fences; - amdgpu_device_handle dev = fences[0].context->dev; -@@ -475,6 +476,10 @@ static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, - return -errno; - - *status = args.out.status; -+ -+ if (first) -+ *first = args.out.first_signaled; -+ - return 0; - } - -@@ -482,7 +487,8 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, - uint32_t fence_count, - bool wait_all, - uint64_t timeout_ns, -- uint32_t *status) -+ uint32_t *status, -+ uint32_t *first) - { - uint32_t ioctl_status = 0; - uint32_t i; -@@ -507,7 +513,7 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, - *status = 0; - - r = amdgpu_ioctl_wait_fences(fences, fence_count, wait_all, timeout_ns, -- &ioctl_status); -+ &ioctl_status, first); - - if (!r) - *status = ioctl_status; -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index e07904c..599c2e7 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -330,7 +330,8 @@ struct drm_amdgpu_wait_fences_in { - }; - - struct drm_amdgpu_wait_fences_out { -- uint64_t status; -+ uint32_t status; -+ uint32_t first_signaled; - }; - - union drm_amdgpu_wait_fences { -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index f308e9a..e1aaffc 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -1154,7 +1154,7 @@ static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) - - r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all, - AMDGPU_TIMEOUT_INFINITE, -- &expired); -+ &expired, NULL); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0065-Hybrid-Version-16.30.4.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0065-Hybrid-Version-16.30.4.patch deleted file mode 100644 index 130473a8..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0065-Hybrid-Version-16.30.4.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 2c13990aa362c397e95b71ce021a71c567fc1cb5 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 6 Jun 2016 13:42:15 +0800 -Subject: [PATCH 065/117] Hybrid Version: 16.30.4 - -Change-Id: Icca7fa5fcf2e3494102e69b6f1cca2ea558a3898 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 4cabeed..dfcfbd8 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 30 --HYBRID_VERSION_PATCH = 3 -+HYBRID_VERSION_PATCH = 4 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0066-amdgpu-add-marketing-name-for-RX480-RX470.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0066-amdgpu-add-marketing-name-for-RX480-RX470.patch deleted file mode 100644 index 1833e000..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0066-amdgpu-add-marketing-name-for-RX480-RX470.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 2b42a0e09532467dc69771e3c11b86cc97e7b588 Mon Sep 17 00:00:00 2001 -From: Ken Wang <Qingqing.Wang@amd.com> -Date: Tue, 7 Jun 2016 10:14:18 +0800 -Subject: [PATCH 066/117] amdgpu: add marketing name for RX480/RX470 - -Change-Id: I42fd363a31d423ca80e8fef91225cacaab7d7257 -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index c29a27e..229a516 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -53,6 +53,8 @@ struct amdgpu_asic_id_table_t { - {0x67B1, 0x0, "AMD Radeon R9 200 Series"}, - {0x67B1, 0x80, "AMD Radeon (TM) R9 390 Series"}, - {0x67B9, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x67DF, 0xC7, "AMD Radeon (TM) RX 480 Graphics"}, -+ {0x67DF, 0xCF, "AMD Radeon (TM) RX 470 Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, - {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, - {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0068-Hybrid-Version-16.40.1.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0068-Hybrid-Version-16.40.1.patch deleted file mode 100644 index d50216d9..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0068-Hybrid-Version-16.40.1.patch +++ /dev/null @@ -1,23 +0,0 @@ -From c9aff41c1564cbe2c8f10ed848108c4effc7f10b Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 13 Jun 2016 18:05:41 +0800 -Subject: [PATCH 068/117] Hybrid Version: 16.40.1 - -Change-Id: Ic4d7182c159ec77604e966a7153d361799cb0583 ---- - .version.hybrid | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/.version.hybrid b/.version.hybrid -index dfcfbd8..1c30410 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 --HYBRID_VERSION_MINOR = 30 --HYBRID_VERSION_PATCH = 4 -+HYBRID_VERSION_MINOR = 40 -+HYBRID_VERSION_PATCH = 1 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0069-Hybrid-Version-16.40.2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0069-Hybrid-Version-16.40.2.patch deleted file mode 100644 index 5f9f6088..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0069-Hybrid-Version-16.40.2.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 2009e1e770823632ca2b31e9db17b7b4a92d2324 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 20 Jun 2016 18:47:01 +0800 -Subject: [PATCH 069/117] Hybrid Version: 16.40.2 - -Change-Id: Ie6029626260838fe8f8cfa117f76ef6b4f6718f8 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 1c30410..5b8a2bc 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 1 -+HYBRID_VERSION_PATCH = 2 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch deleted file mode 100644 index de435e2f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 056084ac47a9b6aab3c3815758b31ef961c1297f Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Fri, 24 Jun 2016 12:05:22 +0800 -Subject: [PATCH 070/117] amdgpu: add amdgpu_bo_inc_ref() function. -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: Icdc00d3e22e48120ca6f4d73ffd05ba43551ad2c -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu.h | 13 +++++++++++++ - amdgpu/amdgpu_bo.c | 6 ++++++ - 2 files changed, 19 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 693d841..d8c436f 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -716,6 +716,19 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, - int amdgpu_bo_free(amdgpu_bo_handle buf_handle); - - /** -+ * Increase the reference count of a buffer object -+ * -+ * \param bo - \c [in] Buffer object handle to increase the reference count -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ * \sa amdgpu_bo_alloc(), amdgpu_bo_free() -+ * -+*/ -+int amdgpu_bo_inc_ref(amdgpu_bo_handle bo); -+ -+/** - * Request CPU access to GPU accessable memory - * - * \param buf_handle - \c [in] Buffer handle -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index aa0d001..c3f5fb9 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -424,6 +424,12 @@ int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - return 0; - } - -+int amdgpu_bo_inc_ref(amdgpu_bo_handle bo) -+{ -+ atomic_inc(&bo->refcount); -+ return 0; -+} -+ - int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) - { - union drm_amdgpu_gem_mmap args; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0071-Hybrid-Version-16.40.3.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0071-Hybrid-Version-16.40.3.patch deleted file mode 100644 index f4fd2fdf..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0071-Hybrid-Version-16.40.3.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 82760cd09721419720b3e091dd02f29ffcfb63c1 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 27 Jun 2016 19:21:03 +0800 -Subject: [PATCH 071/117] Hybrid Version: 16.40.3 - -Change-Id: I0358494494571d6e82cf005bc73d3f4d797f28b8 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 5b8a2bc..bd6f448 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 2 -+HYBRID_VERSION_PATCH = 3 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0072-amdgpu-add-marketing-name-for-RX460.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0072-amdgpu-add-marketing-name-for-RX460.patch deleted file mode 100644 index 485e097a..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0072-amdgpu-add-marketing-name-for-RX460.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0e43e7324f06369c3bef49a1263190b93b253fb7 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Tue, 28 Jun 2016 09:35:57 +0800 -Subject: [PATCH 072/117] amdgpu: add marketing name for RX460 - -Change-Id: I6d8406002bb1a4323b9de14b22aeebc5301faa19 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 229a516..8b270f5 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -55,6 +55,8 @@ struct amdgpu_asic_id_table_t { - {0x67B9, 0x0, "AMD Radeon R9 200 Series"}, - {0x67DF, 0xC7, "AMD Radeon (TM) RX 480 Graphics"}, - {0x67DF, 0xCF, "AMD Radeon (TM) RX 470 Graphics"}, -+ {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, - {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, - {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch deleted file mode 100644 index 45205c05..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 1f7873fb8c46e42b4b83110289ac1c9a40ed93dd Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Tue, 28 Jun 2016 17:38:05 +0800 -Subject: [PATCH 073/117] amdgpu: va allocation may fall to the range outside - of requested [min,max] - -Change-Id: I3e1db613bdc7495a8968914d8560d5ea3aa6d76c -Signed-off-by: David Mao <david.mao@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_vamgr.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 82653e9..f3e38f6 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -192,10 +192,16 @@ static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint - (hole->offset < range_min && range_min + size > hole->offset + hole->size) || - hole->size < size) - continue; -- offset = hole->offset; -+ /* -+ * it is possible that the hole covers more than one range, -+ * thus we need to respect the range_min -+ */ -+ offset = MAX2(hole->offset, range_min); - waste = offset % alignment; - waste = waste ? alignment - waste : 0; - offset += waste; -+ /* the gap between the range_min and hole->offset need to be covered as well */ -+ waste += offset - hole->offset; - if (offset >= (hole->offset + hole->size)) { - continue; - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0074-drm-fix-a-bug-in-va-range-allocation.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0074-drm-fix-a-bug-in-va-range-allocation.patch deleted file mode 100644 index 0d9c48a1..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0074-drm-fix-a-bug-in-va-range-allocation.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 7508b82630fc31ab2f02e3613747da3a64e05f60 Mon Sep 17 00:00:00 2001 -From: Ken Wang <Qingqing.Wang@amd.com> -Date: Thu, 30 Jun 2016 11:19:08 +0800 -Subject: [PATCH 074/117] drm: fix a bug in va range allocation - -Change-Id: Ic038990a14096ff12e3f309f68fd47d057d6bedd -Signed-off-by: David Mao <david.mao@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_vamgr.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index f3e38f6..1518b7a 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -201,11 +201,15 @@ static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint - waste = waste ? alignment - waste : 0; - offset += waste; - /* the gap between the range_min and hole->offset need to be covered as well */ -- waste += offset - hole->offset; -+ waste = offset - hole->offset; - if (offset >= (hole->offset + hole->size)) { - continue; - } - -+ if (offset + size > range_max) { -+ continue; -+ } -+ - if (!waste && hole->size == size) { - offset = hole->offset; - list_del(&hole->list); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch deleted file mode 100644 index 9af75693..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 56d1958975665c03e3b291e941402df9891d6a95 Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Tue, 5 Jul 2016 15:46:37 +0800 -Subject: [PATCH 077/117] amdgpu: Make amdgpu_get_auth to non-static - -The amdgpu_get_auth will be used by another two functions amdgpu_get_fb_id -and amdgpu_get_bo_from_fb_id, so make it to non-static, and -add definition to amdgpu_internal.h. - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> ---- - amdgpu/amdgpu_device.c | 2 +- - amdgpu/amdgpu_internal.h | 14 ++++++++++++++ - 2 files changed, 15 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index 8f1f781..e9ea39c 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -113,7 +113,7 @@ static int fd_compare(void *key1, void *key2) - * >0 - AMD specific error code\n - * <0 - Negative POSIX Error code - */ --static int amdgpu_get_auth(int fd, int *auth) -+int amdgpu_get_auth(int fd, int *auth) - { - int r = 0; - drm_client_t client = {}; -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 1160a12..f722ab5 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -159,6 +159,20 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); - drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); - - /** -+* Get the authenticated form fd, -+* -+* \param fd - \c [in] File descriptor for AMD GPU device -+* \param auth - \c [out] Pointer to output the fd is authenticated or not -+* A render node fd, output auth = 0 -+* A legacy fd, get the authenticated for compatibility root -+* -+* \return 0 on success\n -+* >0 - AMD specific error code\n -+* <0 - Negative POSIX Error code -+*/ -+int amdgpu_get_auth(int fd, int *auth); -+ -+/** - * Inline functions. - */ - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch deleted file mode 100644 index 5c4ad095..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 713485538f2f98590cd3e89ec10a8d9e77f304dc Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Tue, 5 Jul 2016 15:43:37 +0800 -Subject: [PATCH 078/117] amdgpu: Add interface amdgpu_get_fb_id - -The amdgpu_get_fb_id is used to export the crtc's -framebuffer's buffer id to OpenGL driver for capturing -desktop to OpenGL texture. This is for linux rapidfire server. - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> ---- - amdgpu/amdgpu-symbol-check | 1 + - amdgpu/amdgpu.h | 15 +++++++++++++++ - amdgpu/amdgpu_bo.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 64 insertions(+) - -diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index 648db9b..e26ffe2 100755 ---- a/amdgpu/amdgpu-symbol-check -+++ b/amdgpu/amdgpu-symbol-check -@@ -48,6 +48,7 @@ amdgpu_read_mm_registers - amdgpu_va_range_alloc - amdgpu_va_range_free - amdgpu_va_range_query -+amdgpu_get_fb_id - EOF - done) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index d8c436f..0f31100 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -637,6 +637,21 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - struct amdgpu_bo_import_result *output); - - /** -+ * Allow others to get access to crtc's framebuffer -+ * -+ * \param dev - \c [in] Device handle. -+ * See #amdgpu_device_initialize() -+ * \param fb_id - \c [out] the first crtc's framebuffer's buffer_id -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ * \sa amdgpu_get_fb_id() -+ * -+*/ -+int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id); -+ -+/** - * Request GPU access to user allocated memory e.g. via "malloc" - * - * \param dev - [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index c3f5fb9..49b951b 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -43,6 +43,7 @@ - #include "amdgpu_internal.h" - #include "util_hash_table.h" - #include "util_math.h" -+#include "xf86drmMode.h" - - static void amdgpu_close_kms_handle(amdgpu_device_handle dev, - uint32_t handle) -@@ -417,6 +418,53 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - return 0; - } - -+/* Get the first use crtc's frame buffer's buffer_id. */ -+int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) -+{ -+ drmModeResPtr mode_res; -+ int count_crtcs; -+ drmModeCrtcPtr mode_crtc; -+ int current_id = 0; -+ drmModeFBPtr fbcur; -+ struct drm_amdgpu_gem_create_in bo_info = {}; -+ struct drm_amdgpu_gem_op gem_op = {}; -+ int r = 0; -+ int i; -+ struct amdgpu_bo *bo = NULL; -+ int flag_auth = 0; -+ int fd = dev->fd; -+ -+ amdgpu_get_auth(dev->fd, &flag_auth); -+ if (flag_auth) { -+ fd = dev->fd; -+ } else { -+ amdgpu_get_auth(dev->flink_fd, &flag_auth); -+ if (flag_auth) { -+ fd = dev->flink_fd; -+ } else { -+ fprintf(stderr, "amdgpu: amdgpu_get_fb_id, couldn't get the auth fd\n"); -+ return EINVAL; -+ } -+ } -+ -+ mode_res = drmModeGetResources(fd); -+ if (!mode_res) -+ return EFAULT; -+ -+ count_crtcs = mode_res->count_crtcs; -+ for (i = 0; i < mode_res->count_crtcs; i++) { -+ mode_crtc = drmModeGetCrtc(fd, mode_res->crtcs[i]); -+ if (mode_crtc->buffer_id) { -+ current_id = mode_crtc->buffer_id; -+ if (current_id != NULL) -+ break; -+ } -+ } -+ *fb_id = current_id; -+ -+ return r; -+} -+ - int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - { - /* Just drop the reference. */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch deleted file mode 100644 index 31fac2c5..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch +++ /dev/null @@ -1,163 +0,0 @@ -From 562a5585d1c46a99b192c6cf080eb2aad582fa25 Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Tue, 5 Jul 2016 15:44:51 +0800 -Subject: [PATCH 079/117] amdgpu: Add interface amdgpu_get_bo_from_fb_id - -The amdgpu_get_bo_from_fb_id is used to export the -crtc's framebuffer's buffer object to OpenGL driver for capturing desktop to -OpenGL texture.This is alse used by linux rapidfire server. - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> ---- - amdgpu/amdgpu-symbol-check | 1 + - amdgpu/amdgpu.h | 17 +++++++++ - amdgpu/amdgpu_bo.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 110 insertions(+) - -diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index e26ffe2..028ff78 100755 ---- a/amdgpu/amdgpu-symbol-check -+++ b/amdgpu/amdgpu-symbol-check -@@ -49,6 +49,7 @@ amdgpu_va_range_alloc - amdgpu_va_range_free - amdgpu_va_range_query - amdgpu_get_fb_id -+amdgpu_get_bo_from_fb_id - EOF - done) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 0f31100..08593ca 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -652,6 +652,23 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id); - - /** -+ * Get the framebuffer's bo by fb_id -+ * -+ * \param dev - \c [in] Device handle. -+ * See #amdgpu_device_initialize() -+ * \param fb_id - \c [in] the framebuffer's buffer_id -+ * -+ * \param output - \c [output] the bo of fb_id -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ * \sa amdgpu_get_bo_from_fb_id() -+ * -+*/ -+int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struct amdgpu_bo_import_result *output); -+ -+/** - * Request GPU access to user allocated memory e.g. via "malloc" - * - * \param dev - [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 49b951b..f311b94 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -465,6 +465,98 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) - return r; - } - -+/* Get the frame buffer's gem object handle by the fb_id. */ -+int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struct amdgpu_bo_import_result *output) -+{ -+ drmModeFBPtr fbcur; -+ struct drm_amdgpu_gem_create_in bo_info = {}; -+ struct drm_amdgpu_gem_op gem_op = {}; -+ int r = 0; -+ int i; -+ struct amdgpu_bo *bo = NULL; -+ int dma_fd; -+ int flag_auth = 0; -+ int fd = dev->fd; -+ -+ amdgpu_get_auth(dev->fd, &flag_auth); -+ if (flag_auth) { -+ fd = dev->fd; -+ } else { -+ amdgpu_get_auth(dev->flink_fd, &flag_auth); -+ if (flag_auth) { -+ fd = dev->flink_fd; -+ } else { -+ fprintf(stderr, "amdgpu: amdgpu_get_bo_from_fb_id, couldn't get the auth fd\n"); -+ return EINVAL; -+ } -+ } -+ -+ fbcur = drmModeGetFB(fd, fb_id); -+ -+ pthread_mutex_lock(&dev->bo_table_mutex); -+ if (fd != dev->fd) { -+ r = drmPrimeHandleToFD(fd, fbcur->handle, DRM_CLOEXEC, &dma_fd); -+ if (r) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ return r; -+ } -+ r = drmPrimeFDToHandle(dev->fd, dma_fd, &fbcur->handle ); -+ -+ close(dma_fd); -+ -+ if (r) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ return r; -+ } -+ } -+ bo = util_hash_table_get(dev->bo_handles, -+ (void*)(uintptr_t)fbcur->handle); -+ -+ if (bo) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ -+ /* The buffer already exists, just bump the refcount. */ -+ atomic_inc(&bo->refcount); -+ -+ output->buf_handle = bo; -+ output->alloc_size = bo->alloc_size; -+ return 0; -+ } -+ -+ bo = calloc(1, sizeof(struct amdgpu_bo)); -+ if (!bo) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ return -ENOMEM; -+ } -+ -+ /* Query buffer info. */ -+ gem_op.handle = fbcur->handle; -+ gem_op.op = AMDGPU_GEM_OP_GET_GEM_CREATE_INFO; -+ gem_op.value = (uintptr_t)&bo_info; -+ -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_OP, -+ &gem_op, sizeof(gem_op)); -+ if (r) { -+ free(bo); -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ return r; -+ } -+ -+ /* Initialize it. */ -+ atomic_set(&bo->refcount, 1); -+ bo->handle = fbcur->handle; -+ bo->dev = dev; -+ bo->alloc_size = bo_info.bo_size; -+ output->buf_handle = bo; -+ pthread_mutex_init(&bo->cpu_access_mutex, NULL); -+ -+ util_hash_table_set(dev->bo_handles, (void*)(uintptr_t)bo->handle, bo); -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ -+ output->alloc_size = bo->alloc_size; -+ return r; -+} -+ - int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - { - /* Just drop the reference. */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch deleted file mode 100644 index 933f9ea6..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch +++ /dev/null @@ -1,55 +0,0 @@ -From da3e76d7d0dacc732927990344dbe40e69abb8f0 Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Tue, 5 Jul 2016 15:45:33 +0800 -Subject: [PATCH 080/117] amdgpu/tests: Add the test case for amdgpu_get_fb_id - and amdgpu_get_bo_from_fb_id. - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> ---- - tests/amdgpu/bo_tests.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 993895d..195667f 100644 ---- a/tests/amdgpu/bo_tests.c -+++ b/tests/amdgpu/bo_tests.c -@@ -46,6 +46,8 @@ static amdgpu_va_handle va_handle; - static void amdgpu_bo_export_import(void); - static void amdgpu_bo_metadata(void); - static void amdgpu_bo_map_unmap(void); -+static void amdgpu_get_fb_id_and_handle(void); -+ - - CU_TestInfo bo_tests[] = { - { "Export/Import", amdgpu_bo_export_import }, -@@ -53,6 +55,7 @@ CU_TestInfo bo_tests[] = { - { "Metadata", amdgpu_bo_metadata }, - #endif - { "CPU map/unmap", amdgpu_bo_map_unmap }, -+ { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, - CU_TEST_INFO_NULL, - }; - -@@ -184,3 +187,18 @@ static void amdgpu_bo_map_unmap(void) - r = amdgpu_bo_cpu_unmap(buffer_handle); - CU_ASSERT_EQUAL(r, 0); - } -+ -+static void amdgpu_get_fb_id_and_handle(void) -+{ -+ uint32_t *ptr; -+ int i, r; -+ unsigned int fb_id; -+ struct amdgpu_bo_import_result output; -+ -+ r = amdgpu_get_fb_id(device_handle, &fb_id); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_NOT_EQUAL(fb_id, 0); -+ r = amdgpu_get_bo_from_fb_id(device_handle, fb_id, &output); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0081-Hybrid-Version-16.40.4.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0081-Hybrid-Version-16.40.4.patch deleted file mode 100644 index 198ab353..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0081-Hybrid-Version-16.40.4.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 38a6d82d6b796de64885d2a37b1ff9e130e62737 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Wed, 6 Jul 2016 18:43:24 +0800 -Subject: [PATCH 081/117] Hybrid Version: 16.40.4 - -Change-Id: I8ece2169f2a06f6dba83a6642e4c67a4124d0e57 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index bd6f448..f895f5b 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 3 -+HYBRID_VERSION_PATCH = 4 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch deleted file mode 100644 index 48a1856c..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 3edba3d8135eb76e45d6cac2681414a2af790b0c Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Thu, 14 Jul 2016 17:33:13 +0800 -Subject: [PATCH 082/117] amdgpu: Fix memory leak in amdgpu_get_fb_id - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Jim Qu <Jim.Qu@amd.com> ---- - amdgpu/amdgpu_bo.c | 10 +++++++--- - 1 file changed, 7 insertions(+), 3 deletions(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index f311b94..ebfb7cf 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -454,13 +454,17 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) - count_crtcs = mode_res->count_crtcs; - for (i = 0; i < mode_res->count_crtcs; i++) { - mode_crtc = drmModeGetCrtc(fd, mode_res->crtcs[i]); -- if (mode_crtc->buffer_id) { -- current_id = mode_crtc->buffer_id; -- if (current_id != NULL) -+ if (mode_crtc) { -+ if (mode_crtc->buffer_id) { -+ current_id = mode_crtc->buffer_id; -+ drmModeFreeCrtc(mode_crtc); - break; -+ } -+ drmModeFreeCrtc(mode_crtc); - } - } - *fb_id = current_id; -+ drmModeFreeResources(mode_res); - - return r; - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch deleted file mode 100644 index 5be20c43..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 2f5986c7208a9b8534f2fb0981fc5d5fd7c65e30 Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Thu, 14 Jul 2016 17:32:27 +0800 -Subject: [PATCH 083/117] amdgpu: Fix memory leak in amdgpu_get_bo_from_fb_id - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Jim Qu <Jim.Qu@amd.com> ---- - amdgpu/amdgpu_bo.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index ebfb7cf..a07d0b5 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -497,11 +497,15 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - - fbcur = drmModeGetFB(fd, fb_id); - -+ if (fbcur == NULL) -+ return EFAULT; -+ - pthread_mutex_lock(&dev->bo_table_mutex); - if (fd != dev->fd) { - r = drmPrimeHandleToFD(fd, fbcur->handle, DRM_CLOEXEC, &dma_fd); - if (r) { - pthread_mutex_unlock(&dev->bo_table_mutex); -+ drmModeFreeFB(fbcur); - return r; - } - r = drmPrimeFDToHandle(dev->fd, dma_fd, &fbcur->handle ); -@@ -510,6 +514,7 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - - if (r) { - pthread_mutex_unlock(&dev->bo_table_mutex); -+ drmModeFreeFB(fbcur); - return r; - } - } -@@ -524,12 +529,14 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - - output->buf_handle = bo; - output->alloc_size = bo->alloc_size; -+ drmModeFreeFB(fbcur); - return 0; - } - - bo = calloc(1, sizeof(struct amdgpu_bo)); - if (!bo) { - pthread_mutex_unlock(&dev->bo_table_mutex); -+ drmModeFreeFB(fbcur); - return -ENOMEM; - } - -@@ -543,6 +550,7 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - if (r) { - free(bo); - pthread_mutex_unlock(&dev->bo_table_mutex); -+ drmModeFreeFB(fbcur); - return r; - } - -@@ -558,6 +566,7 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - pthread_mutex_unlock(&dev->bo_table_mutex); - - output->alloc_size = bo->alloc_size; -+ drmModeFreeFB(fbcur); - return r; - } - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0084-drm-Fix-multi-GPU-drmGetDevice-return-wrong-device.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0084-drm-Fix-multi-GPU-drmGetDevice-return-wrong-device.patch deleted file mode 100644 index 7f8d9f7d..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0084-drm-Fix-multi-GPU-drmGetDevice-return-wrong-device.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 77886f605b2ea3db8c807a9e955c554f01ca831a Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Sat, 9 Jul 2016 12:00:41 +0800 -Subject: [PATCH 084/117] drm: Fix multi GPU drmGetDevice return wrong device - -drmGetDevice will always return the first device it find -under /dev/dri/. This is not true for multi GPU situation. - -Change-Id: I2a85a8a4feba8a5cc517ad75c6afb532fa07c53d -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - xf86drm.c | 17 +++++++++++++---- - 1 file changed, 13 insertions(+), 4 deletions(-) - -diff --git a/xf86drm.c b/xf86drm.c -index 6689f7c..19001db 100644 ---- a/xf86drm.c -+++ b/xf86drm.c -@@ -3087,6 +3087,7 @@ int drmGetDevice(int fd, drmDevicePtr *device) - int maj, min; - int ret, i, node_count; - int max_count = 16; -+ dev_t find_rdev; - - if (fd == -1 || device == NULL) - return -EINVAL; -@@ -3094,6 +3095,7 @@ int drmGetDevice(int fd, drmDevicePtr *device) - if (fstat(fd, &sbuf)) - return -errno; - -+ find_rdev = sbuf.st_rdev; - maj = major(sbuf.st_rdev); - min = minor(sbuf.st_rdev); - -@@ -3154,17 +3156,24 @@ int drmGetDevice(int fd, drmDevicePtr *device) - local_devices = temp; - } - -- local_devices[i] = d; -+ /* store target at local_devices[0] for ease to use below */ -+ if (find_rdev == sbuf.st_rdev && i) { -+ local_devices[i] = local_devices[0]; -+ local_devices[0] = d; -+ } -+ else -+ local_devices[i] = d; - i++; - } - node_count = i; - -- /* Fold nodes into a single device if they share the same bus info */ -+ /* Fold nodes into a single device if they share the same bus info -+ * and nodes with same bus info will be merged into the first node -+ * position in local_devices */ - drmFoldDuplicatedDevices(local_devices, node_count); - - *device = local_devices[0]; -- for (i = 1; i < node_count && local_devices[i]; i++) -- drmFreeDevice(&local_devices[i]); -+ drmFreeDevices(&local_devices[1], node_count - 1); - - closedir(sysdir); - free(local_devices); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0085-drm-fix-multi-GPU-drmFreeDevices-memory-leak.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0085-drm-fix-multi-GPU-drmFreeDevices-memory-leak.patch deleted file mode 100644 index a7e8721f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0085-drm-fix-multi-GPU-drmFreeDevices-memory-leak.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 9fbef91c92df8da1732bfc8584d6937fcab63bf8 Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Thu, 14 Jul 2016 11:39:42 +0800 -Subject: [PATCH 085/117] drm: fix multi GPU drmFreeDevices memory leak - -When in multi GPU case, devices array may have some -NULL "hole" in between two devices. So check all -array elements and free non-NULL device. - -Change-Id: Ifc32d240f895059bc4b19138cb81de38d99fb88a -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - xf86drm.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/xf86drm.c b/xf86drm.c -index 19001db..32bedeb 100644 ---- a/xf86drm.c -+++ b/xf86drm.c -@@ -2992,8 +2992,9 @@ void drmFreeDevices(drmDevicePtr devices[], int count) - if (devices == NULL) - return; - -- for (i = 0; i < count && devices[i] != NULL; i++) -- drmFreeDevice(&devices[i]); -+ for (i = 0; i < count; i++) -+ if (devices[i]) -+ drmFreeDevice(&devices[i]); - } - - static int drmProcessPciDevice(drmDevicePtr *device, const char *d_name, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0086-drm-add-marketing-names.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0086-drm-add-marketing-names.patch deleted file mode 100644 index 2516c27e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0086-drm-add-marketing-names.patch +++ /dev/null @@ -1,33 +0,0 @@ -From c9b023766d554e9325788b6dbeaaba578e413d14 Mon Sep 17 00:00:00 2001 -From: Ken Wang <Qingqing.Wang@amd.com> -Date: Fri, 15 Jul 2016 16:48:02 +0800 -Subject: [PATCH 086/117] drm: add marketing names - -Change-Id: I6f9b61bde22d9795bda93a7df72dfe2c561bb39a -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> -Reviewed-by : JimQu <Jim.Qu@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 8b270f5..dada012 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -53,8 +53,13 @@ struct amdgpu_asic_id_table_t { - {0x67B1, 0x0, "AMD Radeon R9 200 Series"}, - {0x67B1, 0x80, "AMD Radeon (TM) R9 390 Series"}, - {0x67B9, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x67DF, 0xC4, "AMD Radeon (TM) RX 480 Graphics"}, -+ {0x67DF, 0xC5, "AMD Radeon (TM) RX 470 Graphics"}, - {0x67DF, 0xC7, "AMD Radeon (TM) RX 480 Graphics"}, - {0x67DF, 0xCF, "AMD Radeon (TM) RX 470 Graphics"}, -+ {0x67C4, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, -+ {0x67C7, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67C0, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0087-Hybrid-Version-16.40.5.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0087-Hybrid-Version-16.40.5.patch deleted file mode 100644 index 4e4b0315..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0087-Hybrid-Version-16.40.5.patch +++ /dev/null @@ -1,22 +0,0 @@ -From fed82247d220c1e58b8e9ee9cd1540cb53916997 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 18 Jul 2016 21:59:29 +0800 -Subject: [PATCH 087/117] Hybrid Version: 16.40.5 - -Change-Id: I9c6c41ff3f249f37fb664d9dbba73918ebd0ce7a ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index f895f5b..742801d 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 4 -+HYBRID_VERSION_PATCH = 5 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0088-drm-add-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0088-drm-add-marketing-name.patch deleted file mode 100644 index e4bfa080..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0088-drm-add-marketing-name.patch +++ /dev/null @@ -1,39 +0,0 @@ -From d6ffb1aad9eb34f52e9497967c66f345261ce343 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Thu, 21 Jul 2016 23:22:24 +0800 -Subject: [PATCH 088/117] drm: add marketing name - -Change-Id: Id98873392c171ab3381b8991774a7e667866a527 -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index dada012..b163486 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -60,8 +60,19 @@ struct amdgpu_asic_id_table_t { - {0x67C4, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, - {0x67C7, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67C0, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, -+ {0x67E0, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E8, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E8, 0x01, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67EF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xC5, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xC7, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xEF, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67FF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67FF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, - {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, - {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0089-Hybrid-Version-16.40.6.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0089-Hybrid-Version-16.40.6.patch deleted file mode 100644 index 550191d5..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0089-Hybrid-Version-16.40.6.patch +++ /dev/null @@ -1,22 +0,0 @@ -From d0eaf4ef0e9741cebac7e10fbaf3ade164ad00d2 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Fri, 22 Jul 2016 18:41:45 +0800 -Subject: [PATCH 089/117] Hybrid Version: 16.40.6 - -Change-Id: Icb6c016f122355d0bb38b9c28f64dad31b54d5b1 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 742801d..1b1ec19 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 5 -+HYBRID_VERSION_PATCH = 6 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0090-amdgpu-change-AMDGPU_GEM_CREATE_NO_EVICT-flag-defini.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0090-amdgpu-change-AMDGPU_GEM_CREATE_NO_EVICT-flag-defini.patch deleted file mode 100644 index 72dd11b2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0090-amdgpu-change-AMDGPU_GEM_CREATE_NO_EVICT-flag-defini.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7914d4696e9e94fabe816cba3445a013b43f671 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Tue, 19 Jul 2016 17:04:56 +0800 -Subject: [PATCH 090/117] amdgpu: change AMDGPU_GEM_CREATE_NO_EVICT flag - definition - -to avoid conflict with upstream flags. - -Change-Id: I1ec4aa23c94b7711dea4d75936c94b2655b2a100 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> ---- - include/drm/amdgpu_drm.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 599c2e7..46a3c40 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -78,7 +78,7 @@ - /* Flag that USWC attributes should be used for GTT */ - #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) - /* Flag that the memory allocation should be pinned */ --#define AMDGPU_GEM_CREATE_NO_EVICT (1 << 3) -+#define AMDGPU_GEM_CREATE_NO_EVICT (1 << 31) - - struct drm_amdgpu_gem_create_in { - /** the requested memory size */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0092-drm-add-marketing-names.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0092-drm-add-marketing-names.patch deleted file mode 100644 index 3d3c0c42..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0092-drm-add-marketing-names.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 6834d5e286f239063e6c9a4d4c283ead43fddaf5 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Sat, 23 Jul 2016 02:31:22 +0800 -Subject: [PATCH 092/117] drm: add marketing names - -Change-Id: Ib6c19ad8b473119de8ef531eafe91c90d1840f6b -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index b163486..11c25f5 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -61,10 +61,15 @@ struct amdgpu_asic_id_table_t { - {0x67C7, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67C0, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, - {0x67E0, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E0, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, -+ {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 4100 Graphics"}, - {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E8, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E8, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E8, 0x01, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xC5, "AMD Radeon (TM) RX 460 Graphics"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0095-drm-update-marketing-names.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0095-drm-update-marketing-names.patch deleted file mode 100644 index e521eff6..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0095-drm-update-marketing-names.patch +++ /dev/null @@ -1,40 +0,0 @@ -From ab292275c8d18a9a97d95fab5737c7c9a6817008 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Sat, 23 Jul 2016 03:53:12 +0800 -Subject: [PATCH 095/117] drm: update marketing names - -Change-Id: Ic9f1f32305d0661b38d2d9b206e51ab749c8e31b -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 11c25f5..5585bc8 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -70,14 +70,14 @@ struct amdgpu_asic_id_table_t { - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, -- {0x67EF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xC0, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67EF, 0xC5, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67EF, 0xC7, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xC5, "AMD Radeon (TM) RX Graphics"}, -+ {0x67EF, 0xC7, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67EF, 0xEF, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67FF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67FF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xEF, "AMD Radeon (TM) RX Graphics"}, -+ {0x67FF, 0xC0, "AMD Radeon (TM) RX Graphics"}, -+ {0x67FF, 0xC1, "AMD Radeon (TM) RX Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, - {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, - {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0097-drm-add-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0097-drm-add-marketing-name.patch deleted file mode 100644 index a45d1883..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0097-drm-add-marketing-name.patch +++ /dev/null @@ -1,27 +0,0 @@ -From a2066a7bdc9b36299f58339e73c6af56847e74d1 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Sat, 23 Jul 2016 04:12:44 +0800 -Subject: [PATCH 097/117] drm: add marketing name - -Change-Id: I13142a7605c56586313a9837ad23cdd29805a143 -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 5585bc8..00815bd 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -68,6 +68,7 @@ struct amdgpu_asic_id_table_t { - {0x67E8, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX Series Graphics"}, -+ {0x67E8, 0x80, "AMD Radeon (TM) E9260 Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EF, 0xC0, "AMD Radeon (TM) RX Graphics"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0099-amdgpu-add-the-copyright-and-macros-for-the-asic-id-.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0099-amdgpu-add-the-copyright-and-macros-for-the-asic-id-.patch deleted file mode 100644 index 410aaf70..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0099-amdgpu-add-the-copyright-and-macros-for-the-asic-id-.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 0f7d07aacc6e4221dd79517b5465066650e7fc43 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Mon, 25 Jul 2016 13:53:45 +0800 -Subject: [PATCH 099/117] amdgpu: add the copyright and macros for the asic id - header file - -Change-Id: I83b2f0bb3828cc91b950a826bbfd2fcd5a6965ac -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 00815bd..d521175 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -1,3 +1,30 @@ -+/* -+ * Copyright © 2016 Advanced Micro Devices, Inc. -+ * All Rights Reserved. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+ */ -+ -+#ifndef __AMDGPU_ASIC_ID_H__ -+#define __AMDGPU_ASIC_ID_H__ -+ - struct amdgpu_asic_id_table_t { - uint32_t did; - uint32_t rid; -@@ -140,3 +167,4 @@ struct amdgpu_asic_id_table_t { - - {0x0000, 0x0, "\0"}, - }; -+#endif --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0100-Hybrid-Version-16.40.7.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0100-Hybrid-Version-16.40.7.patch deleted file mode 100644 index c0f623b7..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0100-Hybrid-Version-16.40.7.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 360c7e9414bc61a7240b6703a0ab7c92fdeeb107 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Wed, 27 Jul 2016 19:17:38 +0800 -Subject: [PATCH 100/117] Hybrid Version: 16.40.7 - -Change-Id: Ib919f980255ad2df04dcc7a52c716d35c550e275 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 1b1ec19..2f1b84f 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 6 -+HYBRID_VERSION_PATCH = 7 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0101-drm-change-the-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0101-drm-change-the-marketing-name.patch deleted file mode 100644 index e78eacdc..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0101-drm-change-the-marketing-name.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d0ff0115ebfa74bb00aef28aee2b8532e4d96f4f Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Fri, 29 Jul 2016 21:14:24 +0800 -Subject: [PATCH 101/117] drm: change the marketing name - -Change-Id: I9573cee6cd3aca25c2c639f39ab210069c09f48b -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Junwei Zhang Jerry.Zhang@amd.com ---- - amdgpu/amdgpu_asic_id.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index d521175..041ebe3 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -100,7 +100,7 @@ struct amdgpu_asic_id_table_t { - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EF, 0xC0, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67EF, 0xC5, "AMD Radeon (TM) RX Graphics"}, -+ {0x67EF, 0xC5, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xC7, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xEF, "AMD Radeon (TM) RX Graphics"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0103-amdgpu-expose-the-AMDGPU_GEM_CREATE_VRAM_CLEARED-fla.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0103-amdgpu-expose-the-AMDGPU_GEM_CREATE_VRAM_CLEARED-fla.patch deleted file mode 100644 index 1b61a838..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0103-amdgpu-expose-the-AMDGPU_GEM_CREATE_VRAM_CLEARED-fla.patch +++ /dev/null @@ -1,32 +0,0 @@ -From fad00706737fb2593523dbf799d7c6889a0edd73 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Fri, 22 Jul 2016 11:56:52 +0800 -Subject: [PATCH 103/117] amdgpu: expose the AMDGPU_GEM_CREATE_VRAM_CLEARED - flag - -With this flag specified, VRAM buffer will be cleared at -allocation time. - -Change-Id: Ic587ed7e524a3bfc3862a57b42aa95ff458fe880 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Alexandre Demers <alexandre.f.demers@gmail.com> ---- - include/drm/amdgpu_drm.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 46a3c40..9aa0420 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -77,6 +77,8 @@ - #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) - /* Flag that USWC attributes should be used for GTT */ - #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) -+/* Flag that the memory should be in VRAM and cleared */ -+#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) - /* Flag that the memory allocation should be pinned */ - #define AMDGPU_GEM_CREATE_NO_EVICT (1 << 31) - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0104-drm-amdgpu-add-freesync-ioctl-defines.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0104-drm-amdgpu-add-freesync-ioctl-defines.patch deleted file mode 100644 index a62f2258..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0104-drm-amdgpu-add-freesync-ioctl-defines.patch +++ /dev/null @@ -1,53 +0,0 @@ -From bd51d57069011aef5372d68942cee32a13013108 Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Thu, 4 Aug 2016 14:26:51 +0800 -Subject: [PATCH 104/117] drm/amdgpu: add freesync ioctl defines - -Change-Id: Id5d607fee4ae119015ca685a508a2ee140a8e331 -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - include/drm/amdgpu_drm.h | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 9aa0420..7ffd26b 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -48,6 +48,7 @@ - #define DRM_AMDGPU_GEM_USERPTR 0x11 - #define DRM_AMDGPU_WAIT_FENCES 0x12 - #define DRM_AMDGPU_GEM_FIND_BO 0x13 -+#define DRM_AMDGPU_FREESYNC 0x14 - - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) - #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -63,6 +64,7 @@ - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -+#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -708,4 +710,17 @@ struct drm_amdgpu_virtual_range { - uint64_t start; - uint64_t end; - }; -+ -+/* -+ * Definition of free sync enter and exit signals -+ * We may have more options in the future -+ */ -+#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 -+#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 -+ -+struct drm_amdgpu_freesync { -+ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ -+ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ -+ __u32 spare[7]; -+}; - #endif --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0106-amdgpu-move-hybrid-specific-ioctl-to-the-end.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0106-amdgpu-move-hybrid-specific-ioctl-to-the-end.patch deleted file mode 100644 index 0859114e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0106-amdgpu-move-hybrid-specific-ioctl-to-the-end.patch +++ /dev/null @@ -1,48 +0,0 @@ -From abd3f05b15245951daf6e6aa4228e176e433ae5c Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Tue, 9 Aug 2016 15:47:51 +0800 -Subject: [PATCH 106/117] amdgpu: move hybrid specific ioctl to the end - -To avoid conflicts - -Change-Id: I41a3b62363b2d653e6e8726073c2e9c816604030 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> ---- - include/drm/amdgpu_drm.h | 12 +++++++----- - 1 file changed, 7 insertions(+), 5 deletions(-) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 7ffd26b..6ccad71 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -46,9 +46,10 @@ - #define DRM_AMDGPU_WAIT_CS 0x09 - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 --#define DRM_AMDGPU_WAIT_FENCES 0x12 --#define DRM_AMDGPU_GEM_FIND_BO 0x13 --#define DRM_AMDGPU_FREESYNC 0x14 -+#define DRM_AMDGPU_FREESYNC 0x14 -+/* hybrid specific ioctls */ -+#define DRM_AMDGPU_WAIT_FENCES 0x5e -+#define DRM_AMDGPU_GEM_FIND_BO 0x5f - - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) - #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -62,9 +63,10 @@ - #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) --#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) --#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) -+/* hybrid specific ioctls */ -+#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) -+#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch deleted file mode 100644 index ec35f992..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 38ff3dfb8dee467e37c1416a5c6d1cd9891426fc Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 10 Aug 2016 13:49:04 +0800 -Subject: [PATCH 108/117] amdgpu/tests: add Polaris12 support for cs test - -Change-Id: Ida31ea85ad851dbe41599a4d791ad2cbd0a14ee5 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - tests/amdgpu/cs_tests.c | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index 2c9c1ae..6c4a915 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -208,8 +208,10 @@ static void amdgpu_cs_uvd_create(void) - if (family_id >= AMDGPU_FAMILY_VI) { - ((uint8_t*)msg)[0x10] = 7; - /* chip polaris 10/11 */ -- if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A -+ || chip_id == chip_rev+0x64) { - /* dpb size */ -+ printf("===> chip_rev = %d, chip_id = 0x%x\n", chip_rev, chip_id); - ((uint8_t*)msg)[0x28] = 0x00; - ((uint8_t*)msg)[0x29] = 0x94; - ((uint8_t*)msg)[0x2A] = 0x6B; -@@ -286,7 +288,8 @@ static void amdgpu_cs_uvd_decode(void) - ptr[0x98] = 0x00; - ptr[0x99] = 0x02; - /* chip polaris10/11 */ -- if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A -+ || chip_id == chip_rev+0x64) { - /*dpb size */ - ptr[0x24] = 0x00; - ptr[0x25] = 0x94; -@@ -330,7 +333,8 @@ static void amdgpu_cs_uvd_decode(void) - dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); - - if ((family_id >= AMDGPU_FAMILY_VI) && -- (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { -+ (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A -+ || chip_id == chip_rev+0x64)) { - ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); - } - -@@ -344,7 +348,8 @@ static void amdgpu_cs_uvd_decode(void) - uvd_cmd(bs_addr, 0x100, &i); - if (family_id >= AMDGPU_FAMILY_VI) { - uvd_cmd(it_addr, 0x204, &i); -- if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || -+ chip_id == chip_rev+0x64) - uvd_cmd(ctx_addr, 0x206, &i); - } - ib_cpu[i++] = 0x3BC6; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0109-amdgpu-tests-remove-debug-info-in-cs-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0109-amdgpu-tests-remove-debug-info-in-cs-test.patch deleted file mode 100644 index 06245ca4..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0109-amdgpu-tests-remove-debug-info-in-cs-test.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 51f97fee7269b84d498899fac0a1649131c3d5cc Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 10 Aug 2016 15:16:43 +0800 -Subject: [PATCH 109/117] amdgpu/tests: remove debug info in cs test -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: Ic11256fe3f8fd6d80f4eefc85b9ea0ba665dc4fe -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/cs_tests.c | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index 6c4a915..ca741b7 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -211,7 +211,6 @@ static void amdgpu_cs_uvd_create(void) - if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A - || chip_id == chip_rev+0x64) { - /* dpb size */ -- printf("===> chip_rev = %d, chip_id = 0x%x\n", chip_rev, chip_id); - ((uint8_t*)msg)[0x28] = 0x00; - ((uint8_t*)msg)[0x29] = 0x94; - ((uint8_t*)msg)[0x2A] = 0x6B; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0110-drm-amdgpu-move-freesync-ioctl-to-hybrid-specific-ra.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0110-drm-amdgpu-move-freesync-ioctl-to-hybrid-specific-ra.patch deleted file mode 100644 index 56430290..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0110-drm-amdgpu-move-freesync-ioctl-to-hybrid-specific-ra.patch +++ /dev/null @@ -1,40 +0,0 @@ -From fdcfc33fadaf63e01061fc41e113c0ed777cc137 Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Fri, 12 Aug 2016 14:49:53 +0800 -Subject: [PATCH 110/117] drm/amdgpu: move freesync ioctl to hybrid specific - range - -Change-Id: If324e05ac71107d00c24567a0d2f3380b2084a4f -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - include/drm/amdgpu_drm.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 6ccad71..cda8f36 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -46,8 +46,8 @@ - #define DRM_AMDGPU_WAIT_CS 0x09 - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 --#define DRM_AMDGPU_FREESYNC 0x14 - /* hybrid specific ioctls */ -+#define DRM_AMDGPU_FREESYNC 0x5d - #define DRM_AMDGPU_WAIT_FENCES 0x5e - #define DRM_AMDGPU_GEM_FIND_BO 0x5f - -@@ -63,8 +63,8 @@ - #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) --#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - /* hybrid specific ioctls */ -+#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0112-Hybrid-Version-16.50.0.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0112-Hybrid-Version-16.50.0.patch deleted file mode 100644 index cbf015ba..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0112-Hybrid-Version-16.50.0.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 8ccbd3cb964285c222d946dbbc399eb2f5c61f44 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 15 Aug 2016 19:11:27 +0800 -Subject: [PATCH 112/117] Hybrid Version: 16.50.0 - -Change-Id: I8982d7b72c53032d611ce1b73cb22a28c43b12b5 ---- - .version.hybrid | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 2f1b84f..7c63056 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 --HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 7 -+HYBRID_VERSION_MINOR = 50 -+HYBRID_VERSION_PATCH = 0 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0113-Hybrid-Version-16.50.1.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0113-Hybrid-Version-16.50.1.patch deleted file mode 100644 index 1ce4a7a9..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0113-Hybrid-Version-16.50.1.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 86bb93c61134fcd9c6993916c3b15135ea14966d Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Thu, 18 Aug 2016 18:48:05 +0800 -Subject: [PATCH 113/117] Hybrid Version: 16.50.1 - -Change-Id: I0c3a8d70098ae332245bff754c51371f6c4c5810 -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 7c63056..0cc63be 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 50 --HYBRID_VERSION_PATCH = 0 -+HYBRID_VERSION_PATCH = 1 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0114-amdgpu-add-more-capability-query.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0114-amdgpu-add-more-capability-query.patch deleted file mode 100644 index 7889fbea..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0114-amdgpu-add-more-capability-query.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 7e00543c422f00a68edb4227eeb56ba48175b399 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 11 Aug 2016 15:23:35 +0800 -Subject: [PATCH 114/117] amdgpu: add more capability query - -Change-Id: Ia77feea215a4eb7d0e41684fa5c9e44eedf7feb8 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu.h | 4 +++- - amdgpu/amdgpu_gpu_info.c | 5 +++-- - include/drm/amdgpu_drm.h | 12 ++++++++++-- - 3 files changed, 16 insertions(+), 5 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 08593ca..763a3a6 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -38,6 +38,7 @@ - #include <stdbool.h> - - struct drm_amdgpu_info_hw_ip; -+struct drm_amdgpu_capability; - - /*--------------------------------------------------------------------------*/ - /* --------------------------- Defines ------------------------------------ */ -@@ -1155,7 +1156,8 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, - * <0 - Negative POSIX error code - * - */ --int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value); -+int amdgpu_query_capability(amdgpu_device_handle dev, -+ struct drm_amdgpu_capability *cap); - - /** - * Query information about GDS -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 037df32..406baf2 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -48,10 +48,11 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, - sizeof(struct drm_amdgpu_info)); - } - --int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value) -+int amdgpu_query_capability(amdgpu_device_handle dev, -+ struct drm_amdgpu_capability *cap) - { - return amdgpu_query_info(dev, AMDGPU_INFO_CAPABILITY, -- sizeof(uint64_t), value); -+ sizeof(struct drm_amdgpu_capability), cap); - } - - int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index cda8f36..14d800e 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -530,8 +530,6 @@ struct drm_amdgpu_cs_chunk_data { - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 --/* query pin memory capability */ --#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -@@ -713,6 +711,16 @@ struct drm_amdgpu_virtual_range { - uint64_t end; - }; - -+/* query pin memory capability */ -+#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) -+/* query direct gma capability */ -+#define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1) -+ -+struct drm_amdgpu_capability { -+ uint32_t flag; -+ uint32_t direct_gma_size; -+}; -+ - /* - * Definition of free sync enter and exit signals - * We may have more options in the future --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0115-amdgpu-implement-direct-gma.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0115-amdgpu-implement-direct-gma.patch deleted file mode 100644 index bb19c3a2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0115-amdgpu-implement-direct-gma.patch +++ /dev/null @@ -1,187 +0,0 @@ -From 1474cc7321f29b223249f9f7c09797534aa67288 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 11 Aug 2016 15:25:14 +0800 -Subject: [PATCH 115/117] amdgpu: implement direct gma - -Change-Id: I37a6a0f79a91b8e793fc90eb3955045bebf24848 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu.h | 43 +++++++++++++++++++++++++++++++++++++ - amdgpu/amdgpu_bo.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++- - include/drm/amdgpu_drm.h | 12 +++++++++++ - 3 files changed, 109 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 763a3a6..525bf8e 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -727,6 +727,49 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, - amdgpu_bo_handle *buf_handle, - uint64_t *offset_in_bo); - -+/** -+ * Request GPU access to physical memory from 3rd party device. -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param phys_address - [in] Physical address from 3rd party device which -+ * we want to map to GPU address space (make GPU accessible) -+ * (This address must be correctly aligned). -+ * \param size - [in] Size of allocation (must be correctly aligned) -+ * \param buf_handle - [out] Buffer handle for the userptr memory -+ * resource on submission and be used in other operations. -+ * -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ * \note -+ * This call should guarantee that such memory will be persistently -+ * "locked" / make non-pageable. The purpose of this call is to provide -+ * opportunity for GPU get access to this resource during submission. -+ * -+ * -+ * Supported (theoretical) max. size of mapping is restricted only by -+ * capability.direct_gma_size. See #amdgpu_query_capability() -+ * -+ * It is responsibility of caller to correctly specify physical_address -+*/ -+int amdgpu_create_bo_from_phys_mem(amdgpu_device_handle dev, -+ uint64_t phys_address, uint64_t size, -+ amdgpu_bo_handle *buf_handle); -+ -+/** -+ * Get physical address from BO -+ * -+ * \param buf_handle - [in] Buffer handle for the physical address. -+ * \param phys_address - [out] Physical address of this BO. -+ * -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_bo_get_phys_address(amdgpu_bo_handle buf_handle, -+ uint64_t *phys_address); - - /** - * Free previosuly allocated memory -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index a07d0b5..6abc5e3 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -87,7 +87,8 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev, - int r = 0; - - /* It's an error if the heap is not specified */ -- if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM))) -+ if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM -+ | AMDGPU_GEM_DOMAIN_DGMA))) - return -EINVAL; - - bo = calloc(1, sizeof(struct amdgpu_bo)); -@@ -570,6 +571,58 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - return r; - } - -+int amdgpu_create_bo_from_phys_mem(amdgpu_device_handle dev, -+ uint64_t phys_address, uint64_t size, -+ amdgpu_bo_handle *buf_handle) -+{ -+ struct drm_amdgpu_gem_dgma args; -+ amdgpu_bo_handle bo; -+ int r; -+ -+ if (phys_address == 0 || phys_address & 4095 || -+ size == 0 || size & 4095) -+ return -EINVAL; -+ -+ args.addr = phys_address; -+ args.size = size; -+ args.op = AMDGPU_GEM_DGMA_IMPORT; -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_DGMA, -+ &args, sizeof(args)); -+ if (r) -+ return r; -+ -+ bo = calloc(1, sizeof(struct amdgpu_bo)); -+ if (!bo) -+ return -ENOMEM; -+ -+ atomic_set(&bo->refcount, 1); -+ pthread_mutex_init(&bo->cpu_access_mutex, NULL); -+ bo->dev = dev; -+ bo->alloc_size = size; -+ bo->handle = args.handle; -+ -+ *buf_handle = bo; -+ -+ return 0; -+} -+ -+int amdgpu_bo_get_phys_address(amdgpu_bo_handle buf_handle, -+ uint64_t *phys_address) -+{ -+ struct drm_amdgpu_gem_dgma args; -+ int r; -+ -+ args.op = AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR; -+ args.handle = buf_handle->handle; -+ r = drmCommandWriteRead(buf_handle->dev->fd, DRM_AMDGPU_GEM_DGMA, -+ &args, sizeof(args)); -+ if (r) -+ return r; -+ -+ *phys_address = args.addr; -+ return 0; -+} -+ - int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - { - /* Just drop the reference. */ -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 14d800e..413a9dc 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -47,6 +47,7 @@ - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 - /* hybrid specific ioctls */ -+#define DRM_AMDGPU_GEM_DGMA 0x5c - #define DRM_AMDGPU_FREESYNC 0x5d - #define DRM_AMDGPU_WAIT_FENCES 0x5e - #define DRM_AMDGPU_GEM_FIND_BO 0x5f -@@ -64,6 +65,7 @@ - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) - /* hybrid specific ioctls */ -+#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -@@ -74,6 +76,7 @@ - #define AMDGPU_GEM_DOMAIN_GDS 0x8 - #define AMDGPU_GEM_DOMAIN_GWS 0x10 - #define AMDGPU_GEM_DOMAIN_OA 0x20 -+#define AMDGPU_GEM_DOMAIN_DGMA 0x40 - - /* Flag that CPU access will be required for the case of VRAM domain */ - #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) -@@ -209,6 +212,15 @@ struct drm_amdgpu_gem_userptr { - uint32_t handle; - }; - -+#define AMDGPU_GEM_DGMA_IMPORT 0 -+#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 -+struct drm_amdgpu_gem_dgma { -+ uint64_t addr; -+ uint64_t size; -+ uint32_t op; -+ uint32_t handle; -+}; -+ - struct drm_amdgpu_gem_find_bo { - uint64_t addr; - uint64_t size; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0116-tests-amdgpu-add-direct-gma-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0116-tests-amdgpu-add-direct-gma-test.patch deleted file mode 100644 index 4b6766bb..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0116-tests-amdgpu-add-direct-gma-test.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 331577c5a8736f15fdf55a7606414efcf78a5dff Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 11 Aug 2016 15:26:16 +0800 -Subject: [PATCH 116/117] tests/amdgpu: add direct gma test - -Change-Id: Ib00252eff16a84f16f01039ff39f957bff903bae -Signed-off-by: Flora Cui <Flora.Cui@amd.com> ---- - tests/amdgpu/bo_tests.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 63 insertions(+), 1 deletion(-) - -diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 195667f..5d1f67b 100644 ---- a/tests/amdgpu/bo_tests.c -+++ b/tests/amdgpu/bo_tests.c -@@ -26,6 +26,7 @@ - #endif - - #include <stdio.h> -+#include <inttypes.h> - - #include "CUnit/Basic.h" - -@@ -47,7 +48,7 @@ static void amdgpu_bo_export_import(void); - static void amdgpu_bo_metadata(void); - static void amdgpu_bo_map_unmap(void); - static void amdgpu_get_fb_id_and_handle(void); -- -+static void amdgpu_bo_direct_gma(void); - - CU_TestInfo bo_tests[] = { - { "Export/Import", amdgpu_bo_export_import }, -@@ -56,6 +57,7 @@ CU_TestInfo bo_tests[] = { - #endif - { "CPU map/unmap", amdgpu_bo_map_unmap }, - { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, -+ { "Direct GMA", amdgpu_bo_direct_gma }, - CU_TEST_INFO_NULL, - }; - -@@ -202,3 +204,63 @@ static void amdgpu_get_fb_id_and_handle(void) - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); - } -+ -+#define TEST_LOOP 20 -+static void amdgpu_bo_direct_gma(void) -+{ -+ amdgpu_bo_handle buf_handle[TEST_LOOP] = {0}; -+ amdgpu_bo_handle buf_handle_import[TEST_LOOP] = {0}; -+ uint32_t *ptr[TEST_LOOP] = {0}; -+ struct amdgpu_bo_alloc_request req = {0}; -+ struct drm_amdgpu_capability cap; -+ uint64_t size=4096, phys_addr, remain; -+ int i, j, r; -+ -+ amdgpu_query_capability(device_handle, &cap); -+ if(!(cap.flag & AMDGPU_CAPABILITY_DIRECT_GMA_FLAG)) -+ return; -+ -+ amdgpu_vprintf("direct_gma_size is %d MB\n", cap.direct_gma_size); -+ remain = cap.direct_gma_size << 20; -+ -+ req.preferred_heap = AMDGPU_GEM_DOMAIN_DGMA; -+ for (i = 0; i < TEST_LOOP; i++) { -+ req.alloc_size = size; -+ r = amdgpu_bo_alloc(device_handle, &req, &buf_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_get_phys_address(buf_handle[i], &phys_addr); -+ CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf("bo_size %"PRIx64" phys_addr %"PRIx64"\n", size, phys_addr); -+ r = amdgpu_create_bo_from_phys_mem(device_handle, phys_addr, size, &buf_handle_import[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_bo_cpu_map(buf_handle_import[i], (void **)&ptr[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ for (j = 0; j < (size / 4); ++j) -+ ptr[i][j] = 0xdeadbeef; -+ remain -= size; -+ size <<= 1; -+ amdgpu_vprintf("test loop %d finished, remain %"PRIx64", try to alloc %"PRIx64"\n", i, remain, size); -+ if (remain < size) -+ break; -+ -+ } -+ -+ for (i = 0; i < TEST_LOOP; i++) { -+ if (ptr[i]) { -+ r = amdgpu_bo_cpu_unmap(buf_handle_import[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ if (buf_handle_import[i]) { -+ r = amdgpu_bo_free(buf_handle_import[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ if (buf_handle[i]) { -+ r = amdgpu_bo_free(buf_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ } -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0117-Hybrid-Version-16.50.2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0117-Hybrid-Version-16.50.2.patch deleted file mode 100644 index da54475e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0117-Hybrid-Version-16.50.2.patch +++ /dev/null @@ -1,23 +0,0 @@ -From a2a9ff1f0617d3be4d6eea18e3f089f4c6a985cf Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 12 Sep 2016 19:07:53 +0800 -Subject: [PATCH 117/117] Hybrid Version: 16.50.2 - -Change-Id: I06971cc46278b68cf80ca39e67fb5f361d8f7cf5 -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 0cc63be..0f578c1 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 50 --HYBRID_VERSION_PATCH = 1 -+HYBRID_VERSION_PATCH = 2 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0118-amdgpu-add-SI-support.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0118-amdgpu-add-SI-support.patch deleted file mode 100644 index 0444cd55..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0118-amdgpu-add-SI-support.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 9a0070dbf6669f3374787667fa6a6df9d5acb2ea Mon Sep 17 00:00:00 2001 -From: Ronie Salgado <roniesalg@gmail.com> -Date: Wed, 13 Apr 2016 21:56:15 +0200 -Subject: [PATCH 01/10] amdgpu: add SI support - ---- - amdgpu/amdgpu_gpu_info.c | 18 +++++++++++------- - include/drm/amdgpu_drm.h | 1 + - 2 files changed, 12 insertions(+), 7 deletions(-) - -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 406baf2..d801b86 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -194,10 +194,12 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) - if (r) - return r; - -- r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0, -+ if (dev->info.family_id >= AMDGPU_FAMILY_CI) { -+ r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0, - &dev->info.pa_sc_raster_cfg1[i]); -- if (r) -- return r; -+ if (r) -+ return r; -+ } - } - - r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0, -@@ -205,10 +207,12 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) - if (r) - return r; - -- r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0, -- dev->info.gb_macro_tile_mode); -- if (r) -- return r; -+ if (dev->info.family_id >= AMDGPU_FAMILY_CI) { -+ r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0, -+ dev->info.gb_macro_tile_mode); -+ if (r) -+ return r; -+ } - - r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0, - &dev->info.gb_addr_cfg); -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 413a9dc..29a2393 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -708,6 +708,7 @@ struct drm_amdgpu_info_hw_ip { - * Supported GPU families - */ - #define AMDGPU_FAMILY_UNKNOWN 0 -+#define AMDGPU_FAMILY_SI 100 /* Tahiti, Pitcairn, CapeVerde, Oland, Hainan */ - #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ - #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ - #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0119-amdgpu-add-vram-memory-info.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0119-amdgpu-add-vram-memory-info.patch deleted file mode 100644 index a52e792d..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0119-amdgpu-add-vram-memory-info.patch +++ /dev/null @@ -1,155 +0,0 @@ -From 4bbad6a36ed6416d254a8c0e4bbab07fe29a7acf Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 21 Sep 2016 10:43:40 +0800 -Subject: [PATCH 02/10] amdgpu: add vram memory info -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: Ic73eb5ad601496530be5e8c84a6c2b18aa43f0f1 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu.h | 50 ++++++++++++++++++++++++++++++++++++++++++ - amdgpu/amdgpu_gpu_info.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 107 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 8b87990..7b466dd 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -415,6 +415,40 @@ struct amdgpu_heap_info { - uint64_t max_allocation; - }; - -+struct amdgpu_heap_info2 { -+ /** max. physical memory */ -+ uint64_t total_heap_size; -+ -+ /** Theoretical max. available memory in the given heap */ -+ uint64_t usable_heap_size; -+ -+ /** -+ * Number of bytes allocated in the heap. This includes all processes -+ * and private allocations in the kernel. It changes when new buffers -+ * are allocated, freed, and moved. It cannot be larger than -+ * heap_size. -+ */ -+ uint64_t heap_usage; -+ -+ /** -+ * Theoretical possible max. size of buffer which -+ * could be allocated in the given heap -+ */ -+ uint64_t max_allocation; -+}; -+ -+/** -+ * Structure which provide information about heap -+ * -+ * \sa amdgpu_query_memory_info() -+ * -+ */ -+struct amdgpu_memory_info { -+ struct amdgpu_heap_info2 vram; -+ struct amdgpu_heap_info2 cpu_accessible_vram; -+ struct amdgpu_heap_info2 gtt; -+}; -+ - /** - * Describe GPU h/w info needed for UMD correct initialization - * -@@ -1141,6 +1175,22 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, - uint32_t flags, struct amdgpu_heap_info *info); - - /** -+ * Query memory information -+ * -+ * This query allows UMD to query potentially available memory resources -+ * and total memory size. -+ * -+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -+ * \param mem - \c [out] Pointer to structure to get memory information -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_query_memory_info(amdgpu_device_handle dev, -+ struct amdgpu_memory_info *mem); -+ -+/** - * Get the CRTC ID from the mode object ID - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index d801b86..d3796ac 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -243,6 +243,63 @@ int amdgpu_query_gpu_info(amdgpu_device_handle dev, - return 0; - } - -+int amdgpu_query_memory_info(amdgpu_device_handle dev, -+ struct amdgpu_memory_info *mem) -+{ -+ struct drm_amdgpu_info_vram_gtt vram_gtt_info = {}; -+ struct drm_amdgpu_info_vram_gtt_total vram_gtt_total_info = {}; -+ struct drm_amdgpu_info_vram_gtt_max vram_gtt_max_info = {}; -+ int r; -+ -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT, -+ sizeof(vram_gtt_info), &vram_gtt_info); -+ if (r) -+ return r; -+ -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT_TOTAL, -+ sizeof(vram_gtt_total_info), &vram_gtt_total_info); -+ if (r) -+ return r; -+ -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT_MAX, -+ sizeof(vram_gtt_max_info), &vram_gtt_max_info); -+ if (r) -+ return r; -+ -+ /* vram info */ -+ mem->vram.total_heap_size = vram_gtt_total_info.vram_total_size; -+ mem->vram.usable_heap_size = vram_gtt_info.vram_size; -+ mem->vram.max_allocation = vram_gtt_max_info.vram_max_size; -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_USAGE, -+ sizeof(mem->vram.heap_usage), -+ &mem->vram.heap_usage); -+ if (r) -+ return r; -+ -+ /* visible vram info */ -+ mem->cpu_accessible_vram.total_heap_size = vram_gtt_total_info.vram_cpu_accessible_total_size; -+ mem->cpu_accessible_vram.usable_heap_size = vram_gtt_info.vram_cpu_accessible_size; -+ mem->cpu_accessible_vram.max_allocation = vram_gtt_max_info.vram_cpu_accessible_max_size; -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE, -+ sizeof(mem->cpu_accessible_vram.heap_usage), -+ &mem->cpu_accessible_vram.heap_usage); -+ if (r) -+ return r; -+ -+ /* gtt info */ -+ mem->gtt.total_heap_size = vram_gtt_total_info.gtt_total_size; -+ mem->gtt.usable_heap_size = vram_gtt_info.gtt_size; -+ mem->gtt.max_allocation = vram_gtt_max_info.gtt_max_size; -+ -+ r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE, -+ sizeof(mem->gtt.heap_usage), -+ &mem->gtt.heap_usage); -+ if (r) -+ return r; -+ -+ return 0; -+} -+ - int amdgpu_query_heap_info(amdgpu_device_handle dev, - uint32_t heap, - uint32_t flags, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0120-tests-amdgpu-add-vram-memory-info-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0120-tests-amdgpu-add-vram-memory-info-test.patch deleted file mode 100644 index 03f6087b..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0120-tests-amdgpu-add-vram-memory-info-test.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 15f3ca07aaf1a5836e79b7fe9324559689e3b57a Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Tue, 20 Sep 2016 14:15:59 +0800 -Subject: [PATCH 03/10] tests/amdgpu: add vram memory info test -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: If8f26c99f408fa2706ffc2f62ad17720d83e254c -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/basic_tests.c | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 3817d27..ce14786 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -402,6 +402,31 @@ static void amdgpu_query_heap_info_test(void) - amdgpu_vprintf(" usage: 0x%"PRIx64"\n", info.heap_usage); - } - -+static void amdgpu_query_memory_info_test(void) -+{ -+ struct amdgpu_memory_info mem; -+ -+ amdgpu_query_memory_info(device_handle, &mem); -+ -+ amdgpu_vprintf("\n VRAM memory info...\n"); -+ amdgpu_vprintf(" total: 0x%"PRIx64"\n", mem.vram.total_heap_size); -+ amdgpu_vprintf(" usable: 0x%"PRIx64"\n", mem.vram.usable_heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", mem.vram.heap_usage); -+ amdgpu_vprintf(" max: 0x%"PRIx64"\n", mem.vram.max_allocation); -+ -+ amdgpu_vprintf("\n Visible VRAM memory info...\n"); -+ amdgpu_vprintf(" total: 0x%"PRIx64"\n", mem.cpu_accessible_vram.total_heap_size); -+ amdgpu_vprintf(" usable: 0x%"PRIx64"\n", mem.cpu_accessible_vram.usable_heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", mem.cpu_accessible_vram.heap_usage); -+ amdgpu_vprintf(" max: 0x%"PRIx64"\n", mem.cpu_accessible_vram.max_allocation); -+ -+ amdgpu_vprintf("\n GTT memory info...\n"); -+ amdgpu_vprintf(" total: 0x%"PRIx64"\n", mem.gtt.total_heap_size); -+ amdgpu_vprintf(" usable: 0x%"PRIx64"\n", mem.gtt.usable_heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", mem.gtt.heap_usage); -+ amdgpu_vprintf(" max: 0x%"PRIx64"\n", mem.gtt.max_allocation); -+} -+ - static void amdgpu_query_info_test(void) - { - amdgpu_query_gpu_info_test(); -@@ -412,6 +437,7 @@ static void amdgpu_query_info_test(void) - amdgpu_query_hw_info_test(AMDGPU_HW_IP_UVD); - amdgpu_query_hw_info_test(AMDGPU_HW_IP_VCE); - amdgpu_query_heap_info_test(); -+ amdgpu_query_memory_info_test(); - } - - static void amdgpu_memory_alloc(void) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0121-amdgpu-add-info-about-vram-and-gtt-total-size.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0121-amdgpu-add-info-about-vram-and-gtt-total-size.patch deleted file mode 100644 index 145b698e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0121-amdgpu-add-info-about-vram-and-gtt-total-size.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 5ccf817adb7c0c97423be0fa5250de412657c35a Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 21 Sep 2016 10:45:21 +0800 -Subject: [PATCH 04/10] amdgpu: add info about vram and gtt total size -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I2bafe801770831c615d9c610fc32609b404b69ac -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - include/drm/amdgpu_drm.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 29a2393..bf5f849 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -539,6 +539,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 - /* virtual range */ - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 -+/* Query the total size of VRAM and GTT domains */ -+#define AMDGPU_INFO_VRAM_GTT_TOTAL 0x19 - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -@@ -631,6 +633,12 @@ struct drm_amdgpu_info_vram_gtt { - uint64_t gtt_size; - }; - -+struct drm_amdgpu_info_vram_gtt_total { -+ uint64_t vram_total_size; -+ uint64_t vram_cpu_accessible_total_size; -+ uint64_t gtt_total_size; -+}; -+ - struct drm_amdgpu_info_firmware { - uint32_t ver; - uint32_t feature; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0122-amdgpu-add-info-about-vram-and-gtt-max-allocation-si.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0122-amdgpu-add-info-about-vram-and-gtt-max-allocation-si.patch deleted file mode 100644 index ca6f16c5..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0122-amdgpu-add-info-about-vram-and-gtt-max-allocation-si.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 25b333c8535f53a7763655332e6dd6fc61e6407c Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 21 Sep 2016 10:47:04 +0800 -Subject: [PATCH 05/10] amdgpu: add info about vram and gtt max allocation size -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I40d3be59d10e6c6a199b53b8d9e2d432943762dc -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - include/drm/amdgpu_drm.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index bf5f849..81a82c7 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -541,6 +541,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 - /* Query the total size of VRAM and GTT domains */ - #define AMDGPU_INFO_VRAM_GTT_TOTAL 0x19 -+/* Query the max allocation size of VRAM and GTT domains */ -+#define AMDGPU_INFO_VRAM_GTT_MAX 0x1a - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -@@ -639,6 +641,12 @@ struct drm_amdgpu_info_vram_gtt_total { - uint64_t gtt_total_size; - }; - -+struct drm_amdgpu_info_vram_gtt_max { -+ uint64_t vram_max_size; -+ uint64_t vram_cpu_accessible_max_size; -+ uint64_t gtt_max_size; -+}; -+ - struct drm_amdgpu_info_firmware { - uint32_t ver; - uint32_t feature; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0123-amdgpu-unify-memory-query-info-interface.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0123-amdgpu-unify-memory-query-info-interface.patch deleted file mode 100644 index 2a1a2ad8..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0123-amdgpu-unify-memory-query-info-interface.patch +++ /dev/null @@ -1,231 +0,0 @@ -From 87a889d35949d75e8cea19af8cc14e6ad75ac975 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Thu, 29 Sep 2016 09:36:16 +0800 -Subject: [PATCH 06/10] amdgpu: unify memory query info interface -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I683f52309bb5e821bd49105064a9fb7ba0c9d970 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Marek Olšák <marek.olsak@amd.com> ---- - amdgpu/amdgpu.h | 50 ---------------------------------------- - amdgpu/amdgpu_gpu_info.c | 57 ---------------------------------------------- - include/drm/amdgpu_drm.h | 38 +++++++++++++++++++++---------- - tests/amdgpu/basic_tests.c | 4 ++-- - 4 files changed, 28 insertions(+), 121 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 7b466dd..8b87990 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -415,40 +415,6 @@ struct amdgpu_heap_info { - uint64_t max_allocation; - }; - --struct amdgpu_heap_info2 { -- /** max. physical memory */ -- uint64_t total_heap_size; -- -- /** Theoretical max. available memory in the given heap */ -- uint64_t usable_heap_size; -- -- /** -- * Number of bytes allocated in the heap. This includes all processes -- * and private allocations in the kernel. It changes when new buffers -- * are allocated, freed, and moved. It cannot be larger than -- * heap_size. -- */ -- uint64_t heap_usage; -- -- /** -- * Theoretical possible max. size of buffer which -- * could be allocated in the given heap -- */ -- uint64_t max_allocation; --}; -- --/** -- * Structure which provide information about heap -- * -- * \sa amdgpu_query_memory_info() -- * -- */ --struct amdgpu_memory_info { -- struct amdgpu_heap_info2 vram; -- struct amdgpu_heap_info2 cpu_accessible_vram; -- struct amdgpu_heap_info2 gtt; --}; -- - /** - * Describe GPU h/w info needed for UMD correct initialization - * -@@ -1175,22 +1141,6 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, - uint32_t flags, struct amdgpu_heap_info *info); - - /** -- * Query memory information -- * -- * This query allows UMD to query potentially available memory resources -- * and total memory size. -- * -- * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -- * \param mem - \c [out] Pointer to structure to get memory information -- * -- * \return 0 on success\n -- * <0 - Negative POSIX Error code -- * --*/ --int amdgpu_query_memory_info(amdgpu_device_handle dev, -- struct amdgpu_memory_info *mem); -- --/** - * Get the CRTC ID from the mode object ID - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index d3796ac..d801b86 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -243,63 +243,6 @@ int amdgpu_query_gpu_info(amdgpu_device_handle dev, - return 0; - } - --int amdgpu_query_memory_info(amdgpu_device_handle dev, -- struct amdgpu_memory_info *mem) --{ -- struct drm_amdgpu_info_vram_gtt vram_gtt_info = {}; -- struct drm_amdgpu_info_vram_gtt_total vram_gtt_total_info = {}; -- struct drm_amdgpu_info_vram_gtt_max vram_gtt_max_info = {}; -- int r; -- -- r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT, -- sizeof(vram_gtt_info), &vram_gtt_info); -- if (r) -- return r; -- -- r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT_TOTAL, -- sizeof(vram_gtt_total_info), &vram_gtt_total_info); -- if (r) -- return r; -- -- r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT_MAX, -- sizeof(vram_gtt_max_info), &vram_gtt_max_info); -- if (r) -- return r; -- -- /* vram info */ -- mem->vram.total_heap_size = vram_gtt_total_info.vram_total_size; -- mem->vram.usable_heap_size = vram_gtt_info.vram_size; -- mem->vram.max_allocation = vram_gtt_max_info.vram_max_size; -- r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_USAGE, -- sizeof(mem->vram.heap_usage), -- &mem->vram.heap_usage); -- if (r) -- return r; -- -- /* visible vram info */ -- mem->cpu_accessible_vram.total_heap_size = vram_gtt_total_info.vram_cpu_accessible_total_size; -- mem->cpu_accessible_vram.usable_heap_size = vram_gtt_info.vram_cpu_accessible_size; -- mem->cpu_accessible_vram.max_allocation = vram_gtt_max_info.vram_cpu_accessible_max_size; -- r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE, -- sizeof(mem->cpu_accessible_vram.heap_usage), -- &mem->cpu_accessible_vram.heap_usage); -- if (r) -- return r; -- -- /* gtt info */ -- mem->gtt.total_heap_size = vram_gtt_total_info.gtt_total_size; -- mem->gtt.usable_heap_size = vram_gtt_info.gtt_size; -- mem->gtt.max_allocation = vram_gtt_max_info.gtt_max_size; -- -- r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE, -- sizeof(mem->gtt.heap_usage), -- &mem->gtt.heap_usage); -- if (r) -- return r; -- -- return 0; --} -- - int amdgpu_query_heap_info(amdgpu_device_handle dev, - uint32_t heap, - uint32_t flags, -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 81a82c7..430f239 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -539,10 +539,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 - /* virtual range */ - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 --/* Query the total size of VRAM and GTT domains */ --#define AMDGPU_INFO_VRAM_GTT_TOTAL 0x19 --/* Query the max allocation size of VRAM and GTT domains */ --#define AMDGPU_INFO_VRAM_GTT_MAX 0x1a -+/* Query memory about VRAM and GTT domains */ -+#define AMDGPU_INFO_MEMORY 0x19 - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -@@ -635,16 +633,32 @@ struct drm_amdgpu_info_vram_gtt { - uint64_t gtt_size; - }; - --struct drm_amdgpu_info_vram_gtt_total { -- uint64_t vram_total_size; -- uint64_t vram_cpu_accessible_total_size; -- uint64_t gtt_total_size; -+struct drm_amdgpu_heap_info { -+ /** max. physical memory */ -+ __u64 total_heap_size; -+ -+ /** Theoretical max. available memory in the given heap */ -+ __u64 usable_heap_size; -+ -+ /** -+ * Number of bytes allocated in the heap. This includes all processes -+ * and private allocations in the kernel. It changes when new buffers -+ * are allocated, freed, and moved. It cannot be larger than -+ * heap_size. -+ */ -+ __u64 heap_usage; -+ -+ /** -+ * Theoretical possible max. size of buffer which -+ * could be allocated in the given heap -+ */ -+ __u64 max_allocation; - }; - --struct drm_amdgpu_info_vram_gtt_max { -- uint64_t vram_max_size; -- uint64_t vram_cpu_accessible_max_size; -- uint64_t gtt_max_size; -+struct drm_amdgpu_memory_info { -+ struct drm_amdgpu_heap_info vram; -+ struct drm_amdgpu_heap_info cpu_accessible_vram; -+ struct drm_amdgpu_heap_info gtt; - }; - - struct drm_amdgpu_info_firmware { -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index ce14786..094e9d0 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -404,9 +404,9 @@ static void amdgpu_query_heap_info_test(void) - - static void amdgpu_query_memory_info_test(void) - { -- struct amdgpu_memory_info mem; -+ struct drm_amdgpu_memory_info mem; - -- amdgpu_query_memory_info(device_handle, &mem); -+ amdgpu_query_info(device_handle, AMDGPU_INFO_MEMORY, sizeof(mem), &mem); - - amdgpu_vprintf("\n VRAM memory info...\n"); - amdgpu_vprintf(" total: 0x%"PRIx64"\n", mem.vram.total_heap_size); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0124-amdgpu-remove-redundant-wrong-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0124-amdgpu-remove-redundant-wrong-marketing-name.patch deleted file mode 100644 index 37503f06..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0124-amdgpu-remove-redundant-wrong-marketing-name.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 57f3ea2f6643a477a3f932b1fb5bd41ed50b9d58 Mon Sep 17 00:00:00 2001 -From: Evan Quan <evan.quan@amd.com> -Date: Wed, 28 Sep 2016 17:49:40 +0800 -Subject: [PATCH 07/10] amdgpu: remove redundant wrong marketing name - -Change-Id: I85df90e3bf5ac50335cb848cfa0ae9283e3f4ba4 -Signed-off-by: Evan Quan <evan.quan@amd.com> -Reviewed-by: Junwei Zhange <Jerry.Zhang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 5 ----- - 1 file changed, 5 deletions(-) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 041ebe3..27e2acd 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -87,16 +87,11 @@ struct amdgpu_asic_id_table_t { - {0x67C4, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, - {0x67C7, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67C0, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, -- {0x67E0, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E0, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 4100 Graphics"}, -- {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -- {0x67E8, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E8, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, -- {0x67E8, 0x01, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67E8, 0x80, "AMD Radeon (TM) E9260 Graphics"}, -- {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EF, 0xC0, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0125-amdgpu-add-new-semaphore-support.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0125-amdgpu-add-new-semaphore-support.patch deleted file mode 100644 index 92ebad65..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0125-amdgpu-add-new-semaphore-support.patch +++ /dev/null @@ -1,268 +0,0 @@ -From ce0b923b29ebb4d9b66bc864667308ec0969bf5b Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 22 Sep 2016 14:50:16 +0800 -Subject: [PATCH 08/10] amdgpu: add new semaphore support - -Change-Id: Iae7e4157d6184dab1cd4a944ae9cb803f9b11670 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Monk Liu <monk.liu@amd.com> ---- - amdgpu/amdgpu.h | 74 +++++++++++++++++++++++++++++++++++++++ - amdgpu/amdgpu_cs.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 29 ++++++++++++++++ - 3 files changed, 193 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 8b87990..7185bec 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -137,6 +137,12 @@ typedef struct amdgpu_va *amdgpu_va_handle; - */ - typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; - -+/** -+ * Define handle for sem file -+ */ -+typedef int amdgpu_sem_handle; -+ -+ - /*--------------------------------------------------------------------------*/ - /* -------------------------- Structures ---------------------------------- */ - /*--------------------------------------------------------------------------*/ -@@ -1529,6 +1535,74 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, - int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); - - /** -+ * create sem -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param sem - \c [out] sem handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_create_sem(amdgpu_device_handle dev, -+ amdgpu_sem_handle *sem); -+ -+/** -+ * signal sem -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param context - \c [in] GPU Context -+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* -+ * \param ip_instance - \c [in] Index of the IP block of the same type -+ * \param ring - \c [in] Specify ring index of the IP -+ * \param sem - \c [out] sem handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ */ -+int amdgpu_cs_signal_sem(amdgpu_device_handle dev, -+ amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_sem_handle sem); -+ -+/** -+ * wait sem -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param context - \c [in] GPU Context -+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* -+ * \param ip_instance - \c [in] Index of the IP block of the same type -+ * \param ring - \c [in] Specify ring index of the IP -+ * \param sem - \c [out] sem handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_wait_sem(amdgpu_device_handle dev, -+ amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_sem_handle sem); -+ -+/** -+ * destroy sem -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param sem - \c [out] sem handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ */ -+int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, -+ amdgpu_sem_handle sem); -+ -+/** - * Get the ASIC marketing name - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index b29e8c9..893f934 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -25,6 +25,8 @@ - #include "config.h" - #endif - -+#include <sys/stat.h> -+#include <unistd.h> - #include <stdlib.h> - #include <stdio.h> - #include <string.h> -@@ -620,3 +622,91 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) - { - return amdgpu_cs_unreference_sem(sem); - } -+ -+int amdgpu_cs_create_sem(amdgpu_device_handle dev, -+ amdgpu_sem_handle *sem) -+{ -+ union drm_amdgpu_sem args; -+ int r; -+ -+ if (NULL == dev) -+ return -EINVAL; -+ -+ /* Create the context */ -+ memset(&args, 0, sizeof(args)); -+ args.in.op = AMDGPU_SEM_OP_CREATE_SEM; -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); -+ if (r) -+ return r; -+ -+ *sem = args.out.fd; -+ -+ return 0; -+} -+ -+int amdgpu_cs_signal_sem(amdgpu_device_handle dev, -+ amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_sem_handle sem) -+{ -+ union drm_amdgpu_sem args; -+ -+ if (NULL == dev) -+ return -EINVAL; -+ -+ /* Create the context */ -+ memset(&args, 0, sizeof(args)); -+ args.in.op = AMDGPU_SEM_OP_SIGNAL_SEM; -+ args.in.ctx_id = ctx->id; -+ args.in.ip_type = ip_type; -+ args.in.ip_instance = ip_instance; -+ args.in.ring = ring; -+ args.in.fd = sem; -+ return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); -+} -+ -+int amdgpu_cs_wait_sem(amdgpu_device_handle dev, -+ amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_sem_handle sem) -+{ -+ union drm_amdgpu_sem args; -+ -+ if (NULL == dev) -+ return -EINVAL; -+ -+ /* Create the context */ -+ memset(&args, 0, sizeof(args)); -+ args.in.op = AMDGPU_SEM_OP_WAIT_SEM; -+ args.in.ctx_id = ctx->id; -+ args.in.ip_type = ip_type; -+ args.in.ip_instance = ip_instance; -+ args.in.ring = ring; -+ args.in.fd = sem; -+ args.in.seq = 0; -+ return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); -+} -+ -+int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, -+ amdgpu_sem_handle sem) -+{ -+ union drm_amdgpu_sem args; -+ int r; -+ -+ if (NULL == dev) -+ return -EINVAL; -+ -+ /* Create the context */ -+ memset(&args, 0, sizeof(args)); -+ args.in.op = AMDGPU_SEM_OP_DESTROY_SEM; -+ args.in.fd = sem; -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); -+ if (r) -+ return r; -+ close(sem); -+ return 0; -+} -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 430f239..dfde605 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -47,6 +47,7 @@ - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 - /* hybrid specific ioctls */ -+#define DRM_AMDGPU_SEM 0x5b - #define DRM_AMDGPU_GEM_DGMA 0x5c - #define DRM_AMDGPU_FREESYNC 0x5d - #define DRM_AMDGPU_WAIT_FENCES 0x5e -@@ -69,6 +70,7 @@ - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -+#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -193,6 +195,33 @@ union drm_amdgpu_ctx { - union drm_amdgpu_ctx_out out; - }; - -+/* sync file related */ -+#define AMDGPU_SEM_OP_CREATE_SEM 1 -+#define AMDGPU_SEM_OP_WAIT_SEM 2 -+#define AMDGPU_SEM_OP_SIGNAL_SEM 3 -+#define AMDGPU_SEM_OP_DESTROY_SEM 4 -+ -+struct drm_amdgpu_sem_in { -+ /** AMDGPU_SEM_OP_* */ -+ uint32_t op; -+ int fd; -+ uint32_t ctx_id; -+ uint32_t ip_type; -+ uint32_t ip_instance; -+ uint32_t ring; -+ uint64_t seq; -+}; -+ -+union drm_amdgpu_sem_out { -+ int fd; -+ uint32_t _pad; -+}; -+ -+union drm_amdgpu_sem { -+ struct drm_amdgpu_sem_in in; -+ union drm_amdgpu_sem_out out; -+}; -+ - /* - * This is not a reliable API and you should expect it to fail for any - * number of reasons and have fallback path that do not use userptr to --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0126-amdgpu-new-ids-flag-for-preempt.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0126-amdgpu-new-ids-flag-for-preempt.patch deleted file mode 100644 index 1acd368d..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0126-amdgpu-new-ids-flag-for-preempt.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 6ecbb275511558539eb3126effd61f0ba21b9513 Mon Sep 17 00:00:00 2001 -From: Monk Liu <Monk.Liu@amd.com> -Date: Mon, 24 Oct 2016 11:36:35 +0800 -Subject: [PATCH 09/10] amdgpu:new ids flag for preempt - -Change-Id: I59ffac9728c0e83bc7fd61aa371126dd30691bcb -Signed-off-by: Monk Liu <Monk.Liu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - include/drm/amdgpu_drm.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index dfde605..d40742e 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -517,6 +517,7 @@ struct drm_amdgpu_cs_chunk_data { - * - */ - #define AMDGPU_IDS_FLAGS_FUSION 0x1 -+#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 - - /* indicate if acceleration can be working */ - #define AMDGPU_INFO_ACCEL_WORKING 0x00 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0127-amdgpu-sync-amdgpu_drm.h-with-the-kernel.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0127-amdgpu-sync-amdgpu_drm.h-with-the-kernel.patch deleted file mode 100644 index eb62bd42..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0127-amdgpu-sync-amdgpu_drm.h-with-the-kernel.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 3002e9518ee9b3660f4bd676c546785364885f3c Mon Sep 17 00:00:00 2001 -From: Arindam Nath <arindam.nath@amd.com> -Date: Mon, 9 Jan 2017 14:56:25 +0530 -Subject: [PATCH 10/10] amdgpu: sync amdgpu_drm.h with the kernel -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -v1: -* User might want to query the maximum number of UVD - instances supported by firmware. In addition to that, - if there are multiple applications using UVD handles - at the same time, he might also want to query the - currently used number of handles. - - For this we add a new query AMDGPU_INFO_NUM_HANDLES - and a new struct drm_amdgpu_info_num_handles to - get these values. - -v2: -* Generated using make headers_install. -* Generated from linux-stable/master commit - a121103c922847ba5010819a3f250f1f7fc84ab8 - -Suggested-by: Emil Velikov <emil.l.velikov@gmail.com> -Signed-off-by: Arindam Nath <arindam.nath@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by:Raveendra Talabattula <raveendra.talabattula@amd.com> ---- - include/drm/amdgpu_drm.h | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index d40742e..8272f93 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -571,6 +571,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 - /* Query memory about VRAM and GTT domains */ - #define AMDGPU_INFO_MEMORY 0x19 -+/* Query UVD handles */ -+#define AMDGPU_INFO_NUM_HANDLES 0x1C - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -@@ -764,6 +766,13 @@ struct drm_amdgpu_info_hw_ip { - uint32_t _pad; - }; - -+struct drm_amdgpu_info_num_handles { -+ /** Max handles as supported by firmware for UVD */ -+ uint32_t uvd_max_handles; -+ /** Handles currently in use for UVD */ -+ uint32_t uvd_used_handles; -+}; -+ - /* - * Supported GPU families - */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm_2.4.66.bb b/common/recipes-graphics/drm/libdrm_2.4.66.bb deleted file mode 100644 index c4c3bd61..00000000 --- a/common/recipes-graphics/drm/libdrm_2.4.66.bb +++ /dev/null @@ -1,160 +0,0 @@ -SUMMARY = "Userspace interface to the kernel DRM services" -DESCRIPTION = "The runtime library for accessing the kernel DRM services. DRM \ -stands for \"Direct Rendering Manager\", which is the kernel portion of the \ -\"Direct Rendering Infrastructure\" (DRI). DRI is required for many hardware \ -accelerated OpenGL drivers." -HOMEPAGE = "http://dri.freedesktop.org" -SECTION = "x11/base" -LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://xf86drm.c;beginline=9;endline=32;md5=c8a3b961af7667c530816761e949dc71" -PROVIDES = "drm" -DEPENDS = "libpthread-stubs udev libpciaccess freetype libxext cairo fontconfig libxrender libpng pixman" - -SRC_URI_amd = "http://dri.freedesktop.org/libdrm/${BP}.tar.bz2 \ - file://0001-tests-also-install-tests-app.patch \ - file://0004-amdgpu-drop-address-patching-logics.patch \ - file://0005-amdgpu-validate-user-memory-for-userptr.patch \ - file://0006-amdgpu-add-semaphore-support.patch \ - file://0008-amdgpu-list-each-entry-safely-for-sw-semaphore-when-.patch \ - file://0046-amdgpu-fix-for-submition-with-no-ibs.patch \ - file://0001-intel-kbl-Add-Kabylake-PCI-ids.patch \ - file://0002-Fix-memory-leak-with-drmModeGetConnectorCurrent.patch \ - file://0003-configure.ac-disable-annoying-warning-Wmissing-field.patch \ - file://0007-tests-amdgpu-add-semaphore-test.patch \ - file://0009-amdgpu-Add-new-symbols-to-amdgpu-symbols-check.patch \ - file://0010-radeon-Pass-radeon_bo_open-flags-to-the-DRM_RADEON_G.patch \ - file://0011-xf86drm-Bound-strstr-to-the-allocated-data.patch \ - file://0012-configure.ac-don-t-detect-disabled-options-dependenc.patch \ - file://0013-kmstest-Use-util_open.patch \ - file://0014-tests-add-fsl-dcu-drm-to-modules.patch \ - file://0015-tests-util-Fixup-util_open-parameter-order.patch \ - file://0016-tests-Include-sys-select.h.patch \ - file://0017-tests-Include-poll.h-rather-than-sys-poll.h.patch \ - file://0018-tests-kmstest-inverse-the-order-of-LDADD-libraries.patch \ - file://0019-vc4-Add-the-DRM-header-file.patch \ - file://0020-util-Add-support-for-vc4.patch \ - file://0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch \ - file://0022-amdgpu-add-libdrm-as-private-requirement-dependency.patch \ - file://0023-radeon-add-libdrm-to-Requires.private.patch \ - file://0024-libkms-add-libdrm-to-Requires.private.patch \ - file://0025-android-enable-building-static-version-of-libdrm.patch \ - file://0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch \ - file://0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch \ - file://0028-amdgpu-add-query-for-aperture-va-range.patch \ - file://0029-amdgpu-Implement-SVM-v2.patch \ - file://0030-amdgpu-SVM-test-v2.patch \ - file://0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch \ - file://0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch \ - file://0033-tests-amdgpu-Add-verbose-outputs-v2.patch \ - file://0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch \ - file://0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch \ - file://0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch \ - file://0037-tests-amdgpu-add-the-heap-info-for-query.patch \ - file://0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch \ - file://0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch \ - file://0040-amdgpu-add-query-amdgpu-capability-defination.patch \ - file://0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch \ - file://0042-amdgpu-add-amdgpu_query_capability-interface.patch \ - file://0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch \ - file://0044-amdgpu-support-alloc-va-from-range.patch \ - file://0045-tests-amdgpu-add-alloc-va-from-range-test.patch \ - file://0047-tests-amdgpu-move-va_range_test-above-svm_test.patch \ - file://0048-amdgpu-add-the-function-to-get-the-marketing-name.patch \ - file://0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch \ - file://0050-amdgpu-tests-Fiji-VCE-is-one-instance.patch \ - file://0052-amdgpu-hybrid-update-the-gpu-marketing-name-table.patch \ - file://0053-Hybrid-Version-16.30.2.patch \ - file://0054-tests-amdgpu-add-interface-to-adapt-firmware-require.patch \ - file://0055-tests-amdgpu-adapt-to-new-polaris10-11-uvd-fw.patch \ - file://0056-amdgpu-change-max-allocation.patch \ - file://0057-amdgpu-fix-print-format-error-V2.patch \ - file://0058-Hybrid-Version-16.30.3.patch \ - file://0059-drm-fix-multi-GPU-drmGetDevices-only-return-one-devi.patch \ - file://0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch \ - file://0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch \ - file://0065-Hybrid-Version-16.30.4.patch \ - file://0066-amdgpu-add-marketing-name-for-RX480-RX470.patch \ - file://0068-Hybrid-Version-16.40.1.patch \ - file://0069-Hybrid-Version-16.40.2.patch \ - file://0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch \ - file://0071-Hybrid-Version-16.40.3.patch \ - file://0072-amdgpu-add-marketing-name-for-RX460.patch \ - file://0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch \ - file://0074-drm-fix-a-bug-in-va-range-allocation.patch \ - file://0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch \ - file://0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch \ - file://0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch \ - file://0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch \ - file://0081-Hybrid-Version-16.40.4.patch \ - file://0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch \ - file://0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch \ - file://0084-drm-Fix-multi-GPU-drmGetDevice-return-wrong-device.patch \ - file://0085-drm-fix-multi-GPU-drmFreeDevices-memory-leak.patch \ - file://0086-drm-add-marketing-names.patch \ - file://0087-Hybrid-Version-16.40.5.patch \ - file://0088-drm-add-marketing-name.patch \ - file://0089-Hybrid-Version-16.40.6.patch \ - file://0090-amdgpu-change-AMDGPU_GEM_CREATE_NO_EVICT-flag-defini.patch \ - file://0092-drm-add-marketing-names.patch \ - file://0095-drm-update-marketing-names.patch \ - file://0097-drm-add-marketing-name.patch \ - file://0099-amdgpu-add-the-copyright-and-macros-for-the-asic-id-.patch \ - file://0100-Hybrid-Version-16.40.7.patch \ - file://0101-drm-change-the-marketing-name.patch \ - file://0103-amdgpu-expose-the-AMDGPU_GEM_CREATE_VRAM_CLEARED-fla.patch \ - file://0104-drm-amdgpu-add-freesync-ioctl-defines.patch \ - file://0106-amdgpu-move-hybrid-specific-ioctl-to-the-end.patch \ - file://0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch \ - file://0109-amdgpu-tests-remove-debug-info-in-cs-test.patch \ - file://0110-drm-amdgpu-move-freesync-ioctl-to-hybrid-specific-ra.patch \ - file://0112-Hybrid-Version-16.50.0.patch \ - file://0113-Hybrid-Version-16.50.1.patch \ - file://0114-amdgpu-add-more-capability-query.patch \ - file://0115-amdgpu-implement-direct-gma.patch \ - file://0116-tests-amdgpu-add-direct-gma-test.patch \ - file://0117-Hybrid-Version-16.50.2.patch \ - file://0118-amdgpu-add-SI-support.patch \ - file://0119-amdgpu-add-vram-memory-info.patch \ - file://0120-tests-amdgpu-add-vram-memory-info-test.patch \ - file://0121-amdgpu-add-info-about-vram-and-gtt-total-size.patch \ - file://0122-amdgpu-add-info-about-vram-and-gtt-max-allocation-si.patch \ - file://0123-amdgpu-unify-memory-query-info-interface.patch \ - file://0124-amdgpu-remove-redundant-wrong-marketing-name.patch \ - file://0125-amdgpu-add-new-semaphore-support.patch \ - file://0126-amdgpu-new-ids-flag-for-preempt.patch \ - file://0127-amdgpu-sync-amdgpu_drm.h-with-the-kernel.patch \ -" -SRC_URI[md5sum] = "c6809c48538d6e5999588832045ff014" -SRC_URI[sha256sum] = "79cb8e988749794edfb2d777b298d5292eff353bbbb71ed813589e61d2bc2d76" - -inherit autotools pkgconfig - -EXTRA_OECONF += "--disable-cairo-tests \ - --enable-omap-experimental-api \ - --enable-install-test-programs \ - --disable-manpages \ - --disable-valgrind \ - --enable-amdgpu \ - --enable-radeon \ - " - -ALLOW_EMPTY_${PN}-drivers = "1" -PACKAGES =+ "${PN}-tests ${PN}-drivers ${PN}-radeon ${PN}-nouveau ${PN}-omap \ - ${PN}-intel ${PN}-exynos ${PN}-kms ${PN}-freedreno ${PN}-amdgpu" - -RRECOMMENDS_${PN}-drivers = "${PN}-radeon ${PN}-nouveau ${PN}-omap ${PN}-intel \ - ${PN}-exynos ${PN}-freedreno ${PN}-amdgpu" - -FILES_${PN}-tests = "${bindir}/dr* ${bindir}/mode* ${bindir}/*test" -FILES_${PN}-radeon = "${libdir}/libdrm_radeon.so.*" -FILES_${PN}-nouveau = "${libdir}/libdrm_nouveau.so.*" -FILES_${PN}-omap = "${libdir}/libdrm_omap.so.*" -FILES_${PN}-intel = "${libdir}/libdrm_intel.so.*" -FILES_${PN}-exynos = "${libdir}/libdrm_exynos.so.*" -FILES_${PN}-kms = "${libdir}/libkms*.so.*" -FILES_${PN}-freedreno = "${libdir}/libdrm_freedreno.so.*" -FILES_${PN}-amdgpu = "${libdir}/libdrm_amdgpu.so.*" - -do_install_append_amd() { - cp ${S}/include/drm/amdgpu_drm.h ${D}/usr/include/libdrm -} diff --git a/common/recipes-graphics/fontconfig/fontconfig/0001-Avoid-conflicts-with-integer-width-macros-from-TS-18.patch b/common/recipes-graphics/fontconfig/fontconfig/0001-Avoid-conflicts-with-integer-width-macros-from-TS-18.patch deleted file mode 100644 index cad71707..00000000 --- a/common/recipes-graphics/fontconfig/fontconfig/0001-Avoid-conflicts-with-integer-width-macros-from-TS-18.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 20cddc824c6501c2082cac41b162c34cd5fcc530 Mon Sep 17 00:00:00 2001 -From: Khem Raj <raj.khem@gmail.com> -Date: Sun, 11 Dec 2016 14:32:00 -0800 -Subject: [PATCH] Avoid conflicts with integer width macros from TS - 18661-1:2014 - -glibc 2.25+ has now defined these macros in <limits.h> -https://sourceware.org/git/?p=glibc.git;a=commit;h=5b17fd0da62bf923cb61d1bb7b08cf2e1f1f9c1a - -Signed-off-by: Khem Raj <raj.khem@gmail.com> ---- -Upstream-Status: Submitted - - fontconfig/fontconfig.h | 2 +- - src/fcobjs.h | 2 +- - src/fcobjshash.gperf | 2 +- - src/fcobjshash.h | 2 +- - 4 files changed, 4 insertions(+), 4 deletions(-) - -Index: fontconfig-2.12.1/fontconfig/fontconfig.h -=================================================================== ---- fontconfig-2.12.1.orig/fontconfig/fontconfig.h -+++ fontconfig-2.12.1/fontconfig/fontconfig.h -@@ -128,7 +128,8 @@ typedef int FcBool; - #define FC_USER_CACHE_FILE ".fonts.cache-" FC_CACHE_VERSION - - /* Adjust outline rasterizer */ --#define FC_CHAR_WIDTH "charwidth" /* Int */ -+#define FC_CHARWIDTH "charwidth" /* Int */ -+#define FC_CHAR_WIDTH FC_CHARWIDTH - #define FC_CHAR_HEIGHT "charheight"/* Int */ - #define FC_MATRIX "matrix" /* FcMatrix */ - -Index: fontconfig-2.12.1/src/fcobjs.h -=================================================================== ---- fontconfig-2.12.1.orig/src/fcobjs.h -+++ fontconfig-2.12.1/src/fcobjs.h -@@ -51,7 +51,7 @@ FC_OBJECT (DPI, FcTypeDouble, NULL) - FC_OBJECT (RGBA, FcTypeInteger, NULL) - FC_OBJECT (SCALE, FcTypeDouble, NULL) - FC_OBJECT (MINSPACE, FcTypeBool, NULL) --FC_OBJECT (CHAR_WIDTH, FcTypeInteger, NULL) -+FC_OBJECT (CHARWIDTH, FcTypeInteger, NULL) - FC_OBJECT (CHAR_HEIGHT, FcTypeInteger, NULL) - FC_OBJECT (MATRIX, FcTypeMatrix, NULL) - FC_OBJECT (CHARSET, FcTypeCharSet, FcCompareCharSet) -Index: fontconfig-2.12.1/src/fcobjshash.gperf -=================================================================== ---- fontconfig-2.12.1.orig/src/fcobjshash.gperf -+++ fontconfig-2.12.1/src/fcobjshash.gperf -@@ -44,7 +44,7 @@ int id; - "rgba",FC_RGBA_OBJECT - "scale",FC_SCALE_OBJECT - "minspace",FC_MINSPACE_OBJECT --"charwidth",FC_CHAR_WIDTH_OBJECT -+"charwidth",FC_CHARWIDTH_OBJECT - "charheight",FC_CHAR_HEIGHT_OBJECT - "matrix",FC_MATRIX_OBJECT - "charset",FC_CHARSET_OBJECT -Index: fontconfig-2.12.1/src/fcobjshash.h -=================================================================== ---- fontconfig-2.12.1.orig/src/fcobjshash.h -+++ fontconfig-2.12.1/src/fcobjshash.h -@@ -284,7 +284,7 @@ FcObjectTypeLookup (register const char - {(int)(long)&((struct FcObjectTypeNamePool_t *)0)->FcObjectTypeNamePool_str43,FC_CHARSET_OBJECT}, - {-1}, - #line 47 "fcobjshash.gperf" -- {(int)(long)&((struct FcObjectTypeNamePool_t *)0)->FcObjectTypeNamePool_str45,FC_CHAR_WIDTH_OBJECT}, -+ {(int)(long)&((struct FcObjectTypeNamePool_t *)0)->FcObjectTypeNamePool_str45,FC_CHARWIDTH_OBJECT}, - #line 48 "fcobjshash.gperf" - {(int)(long)&((struct FcObjectTypeNamePool_t *)0)->FcObjectTypeNamePool_str46,FC_CHAR_HEIGHT_OBJECT}, - #line 55 "fcobjshash.gperf" diff --git a/common/recipes-graphics/fontconfig/fontconfig_2.12.1.bbappend b/common/recipes-graphics/fontconfig/fontconfig_2.12.1.bbappend deleted file mode 100644 index 91c1fa0a..00000000 --- a/common/recipes-graphics/fontconfig/fontconfig_2.12.1.bbappend +++ /dev/null @@ -1,2 +0,0 @@ -FILESEXTRAPATHS_prepend_amd := "${THISDIR}/${PN}:" -SRC_URI_append_amd = "${@bb.utils.contains_any("DISTRO", "mel mel-lite", " file://0001-Avoid-conflicts-with-integer-width-macros-from-TS-18.patch", "", d)}" diff --git a/common/recipes-graphics/mesa/mesa/0001-configure.ac-for-llvm-config-to-report-correct-libdi.patch b/common/recipes-graphics/mesa/mesa/0001-configure.ac-for-llvm-config-to-report-correct-libdi.patch new file mode 100644 index 00000000..bdfa0788 --- /dev/null +++ b/common/recipes-graphics/mesa/mesa/0001-configure.ac-for-llvm-config-to-report-correct-libdi.patch @@ -0,0 +1,56 @@ +From d40eff53e2aa8897f5df2b9549761cf7af322085 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Thu, 11 Jan 2018 12:33:29 +0500 +Subject: [PATCH] configure.ac: for llvm-config to report correct libdir + +In cross compiling environments llvm-config messes up +as it reports native environment because it is built +for the host system. Hence if the target system and +host system have different baselibs the llvm-config +fails to find libraries for the target system +appropriately. +This now forces llvm-config to use the target specific +libdir. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + configure.ac | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/configure.ac b/configure.ac +index 2561956..f7f65d6 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -998,7 +998,7 @@ llvm_set_environment_variables() { + LLVM_VERSION=`$LLVM_CONFIG --version | cut -c1-5` + LLVM_CPPFLAGS=`strip_unwanted_llvm_flags "$LLVM_CONFIG --cppflags"` + LLVM_INCLUDEDIR=`$LLVM_CONFIG --includedir` +- LLVM_LIBDIR=`$LLVM_CONFIG --libdir` ++ LLVM_LIBDIR=${llvm_prefix} + + # We need to respect LLVM_CPPFLAGS when compiling LLVM headers. + save_CFLAGS="$CFLAGS" +@@ -2684,17 +2684,17 @@ if test "x$enable_llvm" = xyes; then + + if test $LLVM_VERSION_MAJOR -ge 4 -o $LLVM_VERSION_MAJOR -eq 3 -a $LLVM_VERSION_MINOR -ge 9; then + if test "x$enable_llvm_shared_libs" = xyes; then +- LLVM_LIBS="`$LLVM_CONFIG --link-shared --libs ${LLVM_COMPONENTS}`" ++ LLVM_LIBS="`$LLVM_CONFIG --link-shared --tgtlibdir ${llvm_prefix} --libs ${LLVM_COMPONENTS}`" + else + dnl Invoking llvm-config with both -libs and --system-libs produces the + dnl two separate lines - each for the set of libraries. + dnl Call the program twice, effectively folding them into a single line. +- LLVM_LIBS="`$LLVM_CONFIG --link-static --libs ${LLVM_COMPONENTS}`" ++ LLVM_LIBS="`$LLVM_CONFIG --link-static --tgtlibdir ${llvm_prefix} --libs ${LLVM_COMPONENTS}`" + dnl We need to link to llvm system libs when using static libs + LLVM_LIBS="$LLVM_LIBS `$LLVM_CONFIG --link-static --system-libs`" + fi + else +- LLVM_LIBS="`$LLVM_CONFIG --libs ${LLVM_COMPONENTS}`" ++ LLVM_LIBS="`$LLVM_CONFIG --tgtlibdir ${llvm_prefix} --libs ${LLVM_COMPONENTS}`" + if test "x$enable_llvm_shared_libs" = xyes; then + detect_old_buggy_llvm + else +-- +2.11.1 + diff --git a/common/recipes-graphics/mesa/mesa/0001-fix-building-with-flex-2.6.2.patch b/common/recipes-graphics/mesa/mesa/0001-fix-building-with-flex-2.6.2.patch new file mode 100644 index 00000000..87e7a1d6 --- /dev/null +++ b/common/recipes-graphics/mesa/mesa/0001-fix-building-with-flex-2.6.2.patch @@ -0,0 +1,72 @@ +From: Emil Velikov <emil.velikov@collabora.com> + +Flex version 2.6.2 does not expand (define) the yy version of some +function, thus we fail to compile. + +Strictly speaking this might be a flex bug, although expanding the few +instances is perfectly trivial and works with 2.6.2 and earlier versions +of flex. + +Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org> +Cc: Mike Lothian <mike@fireburn.co.uk> +Repored-by: Mike Lothian <mike@fireburn.co.uk> +Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> + src/compiler/glsl/glsl_lexer.ll | 6 +++--- + src/mesa/program/program_lexer.l | 6 +++--- + src/compiler/glsl/glcpp/glcpp-lex.l | 2 +- + 3 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/src/compiler/glsl/glsl_lexer.ll b/src/compiler/glsl/glsl_lexer.ll +index d5e5d4c..e5492bf 100644 +--- a/src/compiler/glsl/glsl_lexer.ll ++++ b/src/compiler/glsl/glsl_lexer.ll +@@ -627,12 +627,12 @@ classify_identifier(struct _mesa_glsl_parse_state *state, const char *name) + void + _mesa_glsl_lexer_ctor(struct _mesa_glsl_parse_state *state, const char *string) + { +- yylex_init_extra(state, & state->scanner); +- yy_scan_string(string, state->scanner); ++ _mesa_glsl_lexer_lex_init_extra(state, & state->scanner); ++ _mesa_glsl_lexer__scan_string(string, state->scanner); + } + + void + _mesa_glsl_lexer_dtor(struct _mesa_glsl_parse_state *state) + { +- yylex_destroy(state->scanner); ++ _mesa_glsl_lexer_lex_destroy(state->scanner); + } + +diff --git a/src/mesa/program/program_lexer.l b/src/mesa/program/program_lexer.l +index dee66cb..0196635 100644 +--- a/src/mesa/program/program_lexer.l ++++ b/src/mesa/program/program_lexer.l +@@ -474,12 +474,12 @@ void + _mesa_program_lexer_ctor(void **scanner, struct asm_parser_state *state, + const char *string, size_t len) + { +- yylex_init_extra(state, scanner); +- yy_scan_bytes(string, len, *scanner); ++ _mesa_program_lexer_lex_init_extra(state, scanner); ++ _mesa_program_lexer__scan_bytes(string, len, *scanner); + } + + void + _mesa_program_lexer_dtor(void *scanner) + { +- yylex_destroy(scanner); ++ _mesa_program_lexer_lex_destroy(scanner); + } + +diff --git a/src/compiler/glsl/glcpp/glcpp-lex.l b/src/compiler/glsl/glcpp/glcpp-lex.l +index d09441a..41459cd 100644 +--- a/src/compiler/glsl/glcpp/glcpp-lex.l ++++ b/src/compiler/glsl/glcpp/glcpp-lex.l +@@ -584,5 +584,5 @@ HEXADECIMAL_INTEGER 0[xX][0-9a-fA-F]+[uU]? + void + glcpp_lex_set_source_string(glcpp_parser_t *parser, const char *shader) + { +- yy_scan_string(shader, parser->scanner); ++ glcpp__scan_string(shader, parser->scanner); + } + diff --git a/common/recipes-graphics/mesa/mesa/0001-radeonsi-always-set-all-blend-registers.patch b/common/recipes-graphics/mesa/mesa/0001-radeonsi-always-set-all-blend-registers.patch deleted file mode 100644 index ed2e91e1..00000000 --- a/common/recipes-graphics/mesa/mesa/0001-radeonsi-always-set-all-blend-registers.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 39bdbca891a49b51273268de62e8a4db1009cbe5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> -Date: Sat, 26 Nov 2016 15:39:06 +0100 -Subject: [PATCH 1/3] radeonsi: always set all blend registers - -Signed-off-by: Avinash M N <avimn@amd.com> ---- - src/gallium/drivers/radeonsi/si_state.c | 9 ++++----- - 1 file changed, 4 insertions(+), 5 deletions(-) - -diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c -index 2cef615..d71be56 100644 ---- a/src/gallium/drivers/radeonsi/si_state.c -+++ b/src/gallium/drivers/radeonsi/si_state.c -@@ -461,16 +461,15 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx, - S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); - - /* Only set dual source blending for MRT0 to avoid a hang. */ -- if (i >= 1 && blend->dual_src_blend) -- continue; -- -- if (!state->rt[j].colormask) -+ if (i >= 1 && blend->dual_src_blend) { -+ si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); - continue; -+ } - - /* cb_render_state will disable unused ones */ - blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i); - -- if (!state->rt[j].blend_enable) { -+ if (!state->rt[j].colormask || !state->rt[j].blend_enable) { - si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); - continue; - } --- -2.7.4 - diff --git a/common/recipes-graphics/mesa/mesa/0001-reverse-the-patch-radeonsi-rework-clear_buffer-flags.patch b/common/recipes-graphics/mesa/mesa/0001-reverse-the-patch-radeonsi-rework-clear_buffer-flags.patch deleted file mode 100644 index 7f92ffb6..00000000 --- a/common/recipes-graphics/mesa/mesa/0001-reverse-the-patch-radeonsi-rework-clear_buffer-flags.patch +++ /dev/null @@ -1,281 +0,0 @@ -From 3f58e21b9bcd15eda2f4939a90e98172bd00d5c9 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <Sanju.Mehta@amd.com> -Date: Mon, 13 Mar 2017 17:55:10 +0530 -Subject: [PATCH] reverse the patch radeonsi: rework clear_buffer flags -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -don't flush DB for fast color clears -don't flush any caches for initial clears -remove the flag from si_copy_buffer, always assume shader coherency - -Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - src/gallium/drivers/r600/r600_blit.c | 2 +- - src/gallium/drivers/radeon/r600_pipe_common.c | 4 +-- - src/gallium/drivers/radeon/r600_pipe_common.h | 10 ++----- - src/gallium/drivers/radeon/r600_texture.c | 11 ++++---- - src/gallium/drivers/radeon/radeon_video.c | 2 +- - src/gallium/drivers/radeonsi/si_blit.c | 5 ++-- - src/gallium/drivers/radeonsi/si_cp_dma.c | 38 +++++++++++---------------- - src/gallium/drivers/radeonsi/si_pipe.c | 3 +-- - src/gallium/drivers/radeonsi/si_pipe.h | 3 ++- - 9 files changed, 32 insertions(+), 46 deletions(-) - -diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c -index 9230b40..b1bb0cd 100644 ---- a/src/gallium/drivers/r600/r600_blit.c -+++ b/src/gallium/drivers/r600/r600_blit.c -@@ -582,7 +582,7 @@ static void r600_copy_global_buffer(struct pipe_context *ctx, - - static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value, -- enum r600_coherency coher) -+ bool is_framebuffer) - { - struct r600_context *rctx = (struct r600_context*)ctx; - -diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c -index c00e584..61799a5 100644 ---- a/src/gallium/drivers/radeon/r600_pipe_common.c -+++ b/src/gallium/drivers/radeon/r600_pipe_common.c -@@ -1069,12 +1069,12 @@ bool r600_can_dump_shader(struct r600_common_screen *rscreen, - - void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value, -- enum r600_coherency coher) -+ bool is_framebuffer) - { - struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context; - - pipe_mutex_lock(rscreen->aux_context_lock); -- rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher); -+ rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer); - rscreen->aux_context->flush(rscreen->aux_context, NULL, 0); - pipe_mutex_unlock(rscreen->aux_context_lock); - } -diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h -index 3e54534..90227e8 100644 ---- a/src/gallium/drivers/radeon/r600_pipe_common.h -+++ b/src/gallium/drivers/radeon/r600_pipe_common.h -@@ -102,12 +102,6 @@ - #define R600_MAP_BUFFER_ALIGNMENT 64 - #define R600_MAX_VIEWPORTS 16 - --enum r600_coherency { -- R600_COHERENCY_NONE, /* no cache flushes needed */ -- R600_COHERENCY_SHADER, -- R600_COHERENCY_CB_META, --}; -- - #ifdef PIPE_ARCH_BIG_ENDIAN - #define R600_BIG_ENDIAN 1 - #else -@@ -522,7 +516,7 @@ struct r600_common_context { - - void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value, -- enum r600_coherency coher); -+ bool is_framebuffer); - - void (*blit_decompress_depth)(struct pipe_context *ctx, - struct r600_texture *texture, -@@ -593,7 +587,7 @@ bool r600_can_dump_shader(struct r600_common_screen *rscreen, - unsigned processor); - void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value, -- enum r600_coherency coher); -+ bool is_framebuffer); - struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen, - const struct pipe_resource *templ); - const char *r600_get_llvm_processor_name(enum radeon_family family); -diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c -index 23ddff4..c7bd4ff 100644 ---- a/src/gallium/drivers/radeon/r600_texture.c -+++ b/src/gallium/drivers/radeon/r600_texture.c -@@ -815,7 +815,7 @@ static void r600_texture_allocate_htile(struct r600_common_screen *rscreen, - R600_ERR("Failed to create buffer object for htile buffer.\n"); - } else { - r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0, -- htile_size, 0, R600_COHERENCY_NONE); -+ htile_size, 0, true); - } - } - -@@ -990,13 +990,13 @@ r600_texture_create_object(struct pipe_screen *screen, - /* Initialize the cmask to 0xCC (= compressed state). */ - r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b, - rtex->cmask.offset, rtex->cmask.size, -- 0xCCCCCCCC, R600_COHERENCY_NONE); -+ 0xCCCCCCCC, true); - } - if (rtex->dcc_offset) { - r600_screen_clear_buffer(rscreen, &rtex->resource.b.b, - rtex->dcc_offset, - rtex->surface.dcc_size, -- 0xFFFFFFFF, R600_COHERENCY_NONE); -+ 0xFFFFFFFF, true); - } - - /* Initialize the CMASK base register value. */ -@@ -1704,7 +1704,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx, - - rctx->clear_buffer(&rctx->b, &tex->resource.b.b, - tex->dcc_offset, tex->surface.dcc_size, -- reset_value, R600_COHERENCY_CB_META); -+ reset_value, true); - - if (clear_words_needed) - tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level; -@@ -1721,8 +1721,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx, - - /* Do the fast clear. */ - rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b, -- tex->cmask.offset, tex->cmask.size, 0, -- R600_COHERENCY_CB_META); -+ tex->cmask.offset, tex->cmask.size, 0, true); - - tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level; - } -diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c -index aba1404..5d4e096 100644 ---- a/src/gallium/drivers/radeon/radeon_video.c -+++ b/src/gallium/drivers/radeon/radeon_video.c -@@ -122,7 +122,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer) - struct r600_common_context *rctx = (struct r600_common_context*)context; - - rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size, -- 0, R600_COHERENCY_NONE); -+ 0, false); - context->flush(context, NULL, 0); - } - -diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c -index 716a522..d4dc33a 100644 ---- a/src/gallium/drivers/radeonsi/si_blit.c -+++ b/src/gallium/drivers/radeonsi/si_blit.c -@@ -630,7 +630,7 @@ void si_resource_copy_region(struct pipe_context *ctx, - - /* Handle buffers first. */ - if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { -- si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width); -+ si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, false); - return; - } - -@@ -950,8 +950,7 @@ static void si_pipe_clear_buffer(struct pipe_context *ctx, - dword_value = *(uint32_t*)clear_value_ptr; - } - -- sctx->b.clear_buffer(ctx, dst, offset, size, dword_value, -- R600_COHERENCY_SHADER); -+ sctx->b.clear_buffer(ctx, dst, offset, size, dword_value, false); - } - - void si_init_blit_functions(struct si_context *sctx) -diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c -index cbb84b0..bca9cc5 100644 ---- a/src/gallium/drivers/radeonsi/si_cp_dma.c -+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c -@@ -107,26 +107,19 @@ static void si_emit_cp_dma_clear_buffer(struct si_context *sctx, - } - } - --static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coher) -+static unsigned get_flush_flags(struct si_context *sctx, bool is_framebuffer) - { -- switch (coher) { -- default: -- case R600_COHERENCY_NONE: -- return 0; -- case R600_COHERENCY_SHADER: -- return SI_CONTEXT_INV_SMEM_L1 | -- SI_CONTEXT_INV_VMEM_L1 | -- (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0); -- case R600_COHERENCY_CB_META: -- return SI_CONTEXT_FLUSH_AND_INV_CB | -- SI_CONTEXT_FLUSH_AND_INV_CB_META; -- } -+ if (is_framebuffer) -+ return SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER; -+ -+ return SI_CONTEXT_INV_SMEM_L1 | -+ SI_CONTEXT_INV_VMEM_L1 | -+ (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0); - } - --static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency coher) -+static unsigned get_tc_l2_flag(struct si_context *sctx, bool is_framebuffer) - { -- return coher == R600_COHERENCY_SHADER && -- sctx->b.chip_class >= CIK ? CIK_CP_DMA_USE_L2 : 0; -+ return is_framebuffer || sctx->b.chip_class == SI ? 0 : CIK_CP_DMA_USE_L2; - } - - static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst, -@@ -166,11 +159,11 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst - - static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value, -- enum r600_coherency coher) -+ bool is_framebuffer) - { - struct si_context *sctx = (struct si_context*)ctx; -- unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher); -- unsigned flush_flags = get_flush_flags(sctx, coher); -+ unsigned tc_l2_flag = get_tc_l2_flag(sctx, is_framebuffer); -+ unsigned flush_flags = get_flush_flags(sctx, is_framebuffer); - - if (!size) - return; -@@ -256,13 +249,14 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size) - - void si_copy_buffer(struct si_context *sctx, - struct pipe_resource *dst, struct pipe_resource *src, -- uint64_t dst_offset, uint64_t src_offset, unsigned size) -+ uint64_t dst_offset, uint64_t src_offset, unsigned size, -+ bool is_framebuffer) - { - uint64_t main_dst_offset, main_src_offset; - unsigned skipped_size = 0; - unsigned realign_size = 0; -- unsigned tc_l2_flag = get_tc_l2_flag(sctx, R600_COHERENCY_SHADER); -- unsigned flush_flags = get_flush_flags(sctx, R600_COHERENCY_SHADER); -+ unsigned tc_l2_flag = get_tc_l2_flag(sctx, is_framebuffer); -+ unsigned flush_flags = get_flush_flags(sctx, is_framebuffer); - - if (!size) - return; -diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c -index 9dd9ef5..0feee5b 100644 ---- a/src/gallium/drivers/radeonsi/si_pipe.c -+++ b/src/gallium/drivers/radeonsi/si_pipe.c -@@ -239,8 +239,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, - - /* Clear the NULL constant buffer, because loads should return zeros. */ - sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0, -- sctx->null_const_buf.buffer->width0, 0, -- R600_COHERENCY_SHADER); -+ sctx->null_const_buf.buffer->width0, 0, false); - } - - /* XXX: This is the maximum value allowed. I'm not sure how to compute -diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h -index 2661972..1d4b7ee 100644 ---- a/src/gallium/drivers/radeonsi/si_pipe.h -+++ b/src/gallium/drivers/radeonsi/si_pipe.h -@@ -349,7 +349,8 @@ void si_resource_copy_region(struct pipe_context *ctx, - /* si_cp_dma.c */ - void si_copy_buffer(struct si_context *sctx, - struct pipe_resource *dst, struct pipe_resource *src, -- uint64_t dst_offset, uint64_t src_offset, unsigned size); -+ uint64_t dst_offset, uint64_t src_offset, unsigned size, -+ bool is_framebuffer); - void si_init_cp_dma_functions(struct si_context *sctx); - - /* si_debug.c */ --- -2.7.4 - diff --git a/common/recipes-graphics/mesa/mesa/0002-configure.ac-fix-the-llvm-version-correctly.patch b/common/recipes-graphics/mesa/mesa/0002-configure.ac-fix-the-llvm-version-correctly.patch new file mode 100644 index 00000000..33beeedb --- /dev/null +++ b/common/recipes-graphics/mesa/mesa/0002-configure.ac-fix-the-llvm-version-correctly.patch @@ -0,0 +1,38 @@ +From 52ff1aa4e30c15c2eaedc0529bcc04184b3debeb Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Thu, 11 Jan 2018 12:41:18 +0500 +Subject: [PATCH] configure.ac: fix the llvm version correctly + +We do not use the LLVM patch version in OE so +drop that from the version string as well. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + configure.ac | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/configure.ac b/configure.ac +index f7f65d6..9b67ffd 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -995,7 +995,7 @@ strip_unwanted_llvm_flags() { + + llvm_set_environment_variables() { + if test "x$LLVM_CONFIG" != xno; then +- LLVM_VERSION=`$LLVM_CONFIG --version | cut -c1-5` ++ LLVM_VERSION=`$LLVM_CONFIG --version | cut -c1-3` + LLVM_CPPFLAGS=`strip_unwanted_llvm_flags "$LLVM_CONFIG --cppflags"` + LLVM_INCLUDEDIR=`$LLVM_CONFIG --includedir` + LLVM_LIBDIR=${llvm_prefix} +@@ -2639,7 +2639,7 @@ detect_old_buggy_llvm() { + dnl ourselves. + dnl (See https://llvm.org/bugs/show_bug.cgi?id=6823) + dnl We can't use $LLVM_VERSION because it has 'svn' stripped out, +- LLVM_SO_NAME=LLVM-`$LLVM_CONFIG --version | cut -c1-5` ++ LLVM_SO_NAME=LLVM-`$LLVM_CONFIG --version | cut -c1-3` + AS_IF([test -f "$LLVM_LIBDIR/lib$LLVM_SO_NAME.$IMP_LIB_EXT"], [llvm_have_one_so=yes]) + + if test "x$llvm_have_one_so" = xyes; then +-- +2.11.1 + diff --git a/common/recipes-graphics/mesa/mesa/0002-radeonsi-set-CB_BLEND1_CONTROL.ENABLE-for-dual-sourc.patch b/common/recipes-graphics/mesa/mesa/0002-radeonsi-set-CB_BLEND1_CONTROL.ENABLE-for-dual-sourc.patch deleted file mode 100644 index 4b7ecc1c..00000000 --- a/common/recipes-graphics/mesa/mesa/0002-radeonsi-set-CB_BLEND1_CONTROL.ENABLE-for-dual-sourc.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 3f6039e2e1fd5504ec4971f68b0ec09b3b7899f8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> -Date: Sat, 26 Nov 2016 15:43:39 +0100 -Subject: [PATCH 2/3] radeonsi: set CB_BLEND1_CONTROL.ENABLE for dual source - blending - -Signed-off-by: Avinash M N <avimn@amd.com> ---- - src/gallium/drivers/radeonsi/si_state.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c -index d71be56..349bcaa 100644 ---- a/src/gallium/drivers/radeonsi/si_state.c -+++ b/src/gallium/drivers/radeonsi/si_state.c -@@ -462,6 +462,10 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx, - - /* Only set dual source blending for MRT0 to avoid a hang. */ - if (i >= 1 && blend->dual_src_blend) { -+ /* Vulkan does this for dual source blending. */ -+ if (i == 1) -+ blend_cntl |= S_028780_ENABLE(1); -+ - si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); - continue; - } --- -2.7.4 - diff --git a/common/recipes-graphics/mesa/mesa/0002-radeonsi-silence-runtime-warnings-with-LLVM-3.9.patch b/common/recipes-graphics/mesa/mesa/0002-radeonsi-silence-runtime-warnings-with-LLVM-3.9.patch deleted file mode 100644 index 4a0a801c..00000000 --- a/common/recipes-graphics/mesa/mesa/0002-radeonsi-silence-runtime-warnings-with-LLVM-3.9.patch +++ /dev/null @@ -1,30 +0,0 @@ -From a53a20683da3b3bda0647a9859de66a839b4bebf Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> -Date: Tue, 31 Jan 2017 15:13:35 +0530 -Subject: [PATCH 2/4] radeonsi: silence runtime warnings with LLVM 3.9 - -Such as: -Warning: LLVM emitted unknown config register: 0x4 - -This is a non-intrusive back port of commit 0f7a6ea5e7b. ---- - src/gallium/drivers/radeonsi/si_shader.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c -index aad7dd0..9cfecb9 100644 ---- a/src/gallium/drivers/radeonsi/si_shader.c -+++ b/src/gallium/drivers/radeonsi/si_shader.c -@@ -5862,6 +5862,9 @@ void si_shader_binary_read_config(struct radeon_shader_binary *binary, - conf->scratch_bytes_per_wave = - G_00B860_WAVESIZE(value) * 256 * 4 * 1; - break; -+ case 0x4: -+ case 0x8: -+ break; /* just spilling stats, not important */ - default: - { - static bool printed; --- -2.7.4 - diff --git a/common/recipes-graphics/mesa/mesa/0003-radeonsi-disable-RB-blend-optimizations-for-dual-sou.patch b/common/recipes-graphics/mesa/mesa/0003-radeonsi-disable-RB-blend-optimizations-for-dual-sou.patch deleted file mode 100644 index b06091f7..00000000 --- a/common/recipes-graphics/mesa/mesa/0003-radeonsi-disable-RB-blend-optimizations-for-dual-sou.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e130c192cb70df096aef57b2a308ccafe3228ceb Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> -Date: Sat, 26 Nov 2016 15:52:05 +0100 -Subject: [PATCH 3/3] radeonsi: disable RB+ blend optimizations for dual source - blending - -Signed-off-by: Avinash M N <avimn@amd.com> ---- - src/gallium/drivers/radeonsi/si_state.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c -index 349bcaa..b51c74d 100644 ---- a/src/gallium/drivers/radeonsi/si_state.c -+++ b/src/gallium/drivers/radeonsi/si_state.c -@@ -554,6 +554,17 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx, - } - - if (sctx->b.family == CHIP_STONEY) { -+ /* Disable RB+ blend optimizations for dual source blending. -+ * Vulkan does this. -+ */ -+ if (blend->dual_src_blend) { -+ for (int i = 0; i < 8; i++) { -+ sx_mrt_blend_opt[i] = -+ S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) | -+ S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE); -+ } -+ } -+ - for (int i = 0; i < 8; i++) - si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, - sx_mrt_blend_opt[i]); --- -2.7.4 - diff --git a/common/recipes-graphics/mesa/mesa/0003-st-mesa-Revert-patches-solves-perf-issues-with-mesa-.patch b/common/recipes-graphics/mesa/mesa/0003-st-mesa-Revert-patches-solves-perf-issues-with-mesa-.patch deleted file mode 100644 index 338a3fee..00000000 --- a/common/recipes-graphics/mesa/mesa/0003-st-mesa-Revert-patches-solves-perf-issues-with-mesa-.patch +++ /dev/null @@ -1,312 +0,0 @@ -From f8bd168265881419af9dd407d0ec005b8ff9512d Mon Sep 17 00:00:00 2001 -From: christian koenig <christian.koenig@amd.com> -Date: Thu, 14 Jan 2016 16:46:57 +0100 -Subject: [PATCH 3/4] st/mesa: Revert patches solves perf issues with mesa - 12.0.3 - -This patch reverts below patches to solve performance issue observed with -upgrade to mesa 12.0.3 - -patch1: This patch needs to be applied -Revert "st/vdpau: use linear layout for output surfaces" - -patch2: -Subject: st/mesa: directly compute level=0 texture size in st_finalize_texture - -patch3: -Subject: st/mesa: Replace GLvoid with void - -patch4: -Subject: st/mesa: fix reference counting bug in st_vdpau - -Signed-off-by: Tamil Velan <Tamil-Velan.Jayakumar@amd.com> ---- - src/gallium/state_trackers/vdpau/output.c | 2 +- - src/mesa/state_tracker/st_texture.h | 6 + - src/mesa/state_tracker/st_vdpau.c | 194 +++++++++--------------------- - 3 files changed, 62 insertions(+), 140 deletions(-) - -diff --git a/src/gallium/state_trackers/vdpau/output.c b/src/gallium/state_trackers/vdpau/output.c -index c644cc8..5175da4 100644 ---- a/src/gallium/state_trackers/vdpau/output.c -+++ b/src/gallium/state_trackers/vdpau/output.c -@@ -82,7 +82,7 @@ vlVdpOutputSurfaceCreate(VdpDevice device, - res_tmpl.depth0 = 1; - res_tmpl.array_size = 1; - res_tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET | -- PIPE_BIND_LINEAR | PIPE_BIND_SHARED; -+ PIPE_BIND_SHARED; - res_tmpl.usage = PIPE_USAGE_DEFAULT; - - pipe_mutex_lock(dev->mutex); -diff --git a/src/mesa/state_tracker/st_texture.h b/src/mesa/state_tracker/st_texture.h -index ae9e2b4..d8cd7c7 100644 ---- a/src/mesa/state_tracker/st_texture.h -+++ b/src/mesa/state_tracker/st_texture.h -@@ -79,6 +79,12 @@ struct st_texture_object - */ - GLuint lastLevel; - -+ /** The size of the level=0 mipmap image. -+ * Note that the number of 1D array layers will be in height0 and the -+ * number of 2D array layers will be in depth0, as in GL. -+ */ -+ GLuint width0, height0, depth0; -+ - /* On validation any active images held in main memory or in other - * textures will be copied to this texture and the old storage freed. - */ -diff --git a/src/mesa/state_tracker/st_vdpau.c b/src/mesa/state_tracker/st_vdpau.c -index 4f599dd..807eebd 100644 ---- a/src/mesa/state_tracker/st_vdpau.c -+++ b/src/mesa/state_tracker/st_vdpau.c -@@ -39,6 +39,8 @@ - #include "pipe/p_state.h" - #include "pipe/p_video_codec.h" - -+#include "state_tracker/vdpau_interop.h" -+ - #include "util/u_inlines.h" - - #include "st_vdpau.h" -@@ -49,140 +51,15 @@ - - #ifdef HAVE_ST_VDPAU - --#include "state_tracker/vdpau_interop.h" --#include "state_tracker/vdpau_dmabuf.h" --#include "state_tracker/vdpau_funcs.h" --#include "state_tracker/drm_driver.h" -- --static struct pipe_resource * --st_vdpau_video_surface_gallium(struct gl_context *ctx, const void *vdpSurface, -- GLuint index) --{ -- int (*getProcAddr)(uint32_t device, uint32_t id, void **ptr); -- uint32_t device = (uintptr_t)ctx->vdpDevice; -- struct pipe_sampler_view *sv; -- VdpVideoSurfaceGallium *f; -- -- struct pipe_video_buffer *buffer; -- struct pipe_sampler_view **samplers; -- struct pipe_resource *res = NULL; -- -- getProcAddr = (void *)ctx->vdpGetProcAddress; -- if (getProcAddr(device, VDP_FUNC_ID_VIDEO_SURFACE_GALLIUM, (void**)&f)) -- return NULL; -- -- buffer = f((uintptr_t)vdpSurface); -- if (!buffer) -- return NULL; -- -- samplers = buffer->get_sampler_view_planes(buffer); -- if (!samplers) -- return NULL; -- -- sv = samplers[index >> 1]; -- if (!sv) -- return NULL; -- -- pipe_resource_reference(&res, sv->texture); -- return res; --} -- --static struct pipe_resource * --st_vdpau_output_surface_gallium(struct gl_context *ctx, const void *vdpSurface) --{ -- int (*getProcAddr)(uint32_t device, uint32_t id, void **ptr); -- uint32_t device = (uintptr_t)ctx->vdpDevice; -- struct pipe_resource *res = NULL; -- VdpOutputSurfaceGallium *f; -- -- getProcAddr = (void *)ctx->vdpGetProcAddress; -- if (getProcAddr(device, VDP_FUNC_ID_OUTPUT_SURFACE_GALLIUM, (void**)&f)) -- return NULL; -- -- pipe_resource_reference(&res, f((uintptr_t)vdpSurface)); -- return res; --} -- --static struct pipe_resource * --st_vdpau_resource_from_description(struct gl_context *ctx, -- const struct VdpSurfaceDMABufDesc *desc) --{ -- struct st_context *st = st_context(ctx); -- struct pipe_resource templ, *res; -- struct winsys_handle whandle; -- -- if (desc->handle == -1) -- return NULL; -- -- memset(&templ, 0, sizeof(templ)); -- templ.target = PIPE_TEXTURE_2D; -- templ.last_level = 0; -- templ.depth0 = 1; -- templ.array_size = 1; -- templ.width0 = desc->width; -- templ.height0 = desc->height; -- templ.format = VdpFormatRGBAToPipe(desc->format); -- templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; -- templ.usage = PIPE_USAGE_DEFAULT; -- -- memset(&whandle, 0, sizeof(whandle)); -- whandle.type = DRM_API_HANDLE_TYPE_FD; -- whandle.handle = desc->handle; -- whandle.offset = desc->offset; -- whandle.stride = desc->stride; -- -- res = st->pipe->screen->resource_from_handle(st->pipe->screen, &templ, &whandle, -- PIPE_HANDLE_USAGE_READ_WRITE); -- close(desc->handle); -- -- return res; --} -- --static struct pipe_resource * --st_vdpau_output_surface_dma_buf(struct gl_context *ctx, const void *vdpSurface) --{ -- int (*getProcAddr)(uint32_t device, uint32_t id, void **ptr); -- uint32_t device = (uintptr_t)ctx->vdpDevice; -- -- struct VdpSurfaceDMABufDesc desc; -- VdpOutputSurfaceDMABuf *f; -- -- getProcAddr = (void *)ctx->vdpGetProcAddress; -- if (getProcAddr(device, VDP_FUNC_ID_OUTPUT_SURFACE_DMA_BUF, (void**)&f)) -- return NULL; -- -- if (f((uintptr_t)vdpSurface, &desc) != VDP_STATUS_OK) -- return NULL; -- -- return st_vdpau_resource_from_description(ctx, &desc); --} -- --static struct pipe_resource * --st_vdpau_video_surface_dma_buf(struct gl_context *ctx, const void *vdpSurface, -- GLuint index) --{ -- int (*getProcAddr)(uint32_t device, uint32_t id, void **ptr); -- uint32_t device = (uintptr_t)ctx->vdpDevice; -- -- struct VdpSurfaceDMABufDesc desc; -- VdpVideoSurfaceDMABuf *f; -- -- getProcAddr = (void *)ctx->vdpGetProcAddress; -- if (getProcAddr(device, VDP_FUNC_ID_VIDEO_SURFACE_DMA_BUF, (void**)&f)) -- return NULL; -- -- if (f((uintptr_t)vdpSurface, index, &desc) != VDP_STATUS_OK) -- return NULL; -- -- return st_vdpau_resource_from_description(ctx, &desc); --} -- - static void - st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, - GLboolean output, struct gl_texture_object *texObj, - struct gl_texture_image *texImage, -- const void *vdpSurface, GLuint index) -+ const GLvoid *vdpSurface, GLuint index) - { -+ int (*getProcAddr)(uint32_t device, uint32_t id, void **ptr); -+ uint32_t device = (uintptr_t)ctx->vdpDevice; -+ - struct st_context *st = st_context(ctx); - struct st_texture_object *stObj = st_texture_object(texObj); - struct st_texture_image *stImage = st_texture_image(texImage); -@@ -191,17 +68,53 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, - struct pipe_sampler_view templ, **sampler_view; - mesa_format texFormat; - -+ getProcAddr = (void *)ctx->vdpGetProcAddress; - if (output) { -- res = st_vdpau_output_surface_dma_buf(ctx, vdpSurface); -+ VdpOutputSurfaceGallium *f; - -- if (!res) -- res = st_vdpau_output_surface_gallium(ctx, vdpSurface); -+ if (getProcAddr(device, VDP_FUNC_ID_OUTPUT_SURFACE_GALLIUM, (void**)&f)) { -+ _mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUMapSurfacesNV"); -+ return; -+ } - -- } else { -- res = st_vdpau_video_surface_dma_buf(ctx, vdpSurface, index); -+ res = f((uintptr_t)vdpSurface); -+ -+ if (!res) { -+ _mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUMapSurfacesNV"); -+ return; -+ } - -- if (!res) -- res = st_vdpau_video_surface_gallium(ctx, vdpSurface, index); -+ } else { -+ struct pipe_sampler_view *sv; -+ VdpVideoSurfaceGallium *f; -+ -+ struct pipe_video_buffer *buffer; -+ struct pipe_sampler_view **samplers; -+ -+ if (getProcAddr(device, VDP_FUNC_ID_VIDEO_SURFACE_GALLIUM, (void**)&f)) { -+ _mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUMapSurfacesNV"); -+ return; -+ } -+ -+ buffer = f((uintptr_t)vdpSurface); -+ if (!buffer) { -+ _mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUMapSurfacesNV"); -+ return; -+ } -+ -+ samplers = buffer->get_sampler_view_planes(buffer); -+ if (!samplers) { -+ _mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUMapSurfacesNV"); -+ return; -+ } -+ -+ sv = samplers[index >> 1]; -+ if (!sv) { -+ _mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUMapSurfacesNV"); -+ return; -+ } -+ -+ res = sv->texture; - } - - if (!res) { -@@ -212,7 +125,6 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, - /* do we have different screen objects ? */ - if (res->screen != st->pipe->screen) { - _mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUMapSurfacesNV"); -- pipe_resource_reference(&res, NULL); - return; - } - -@@ -243,17 +155,21 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, - sampler_view = st_texture_get_sampler_view(st, stObj); - *sampler_view = st->pipe->create_sampler_view(st->pipe, res, &templ); - -+ stObj->width0 = res->width0; -+ stObj->height0 = res->height0; -+ stObj->depth0 = 1; -+ -+ - stObj->surface_format = res->format; - - _mesa_dirty_texobj(ctx, texObj); -- pipe_resource_reference(&res, NULL); - } - - static void - st_vdpau_unmap_surface(struct gl_context *ctx, GLenum target, GLenum access, - GLboolean output, struct gl_texture_object *texObj, - struct gl_texture_image *texImage, -- const void *vdpSurface, GLuint index) -+ const GLvoid *vdpSurface, GLuint index) - { - struct st_context *st = st_context(ctx); - struct st_texture_object *stObj = st_texture_object(texObj); --- -2.7.4 - diff --git a/common/recipes-graphics/mesa/mesa/0003-strip-llvm-ldflags.patch b/common/recipes-graphics/mesa/mesa/0003-strip-llvm-ldflags.patch new file mode 100644 index 00000000..e080b920 --- /dev/null +++ b/common/recipes-graphics/mesa/mesa/0003-strip-llvm-ldflags.patch @@ -0,0 +1,33 @@ +diff --git a/configure.ac.orig b/configure.ac +index 12dedd6..0776938 100644 +--- a/configure.ac.orig ++++ b/configure.ac +@@ -1012,6 +1012,19 @@ llvm_add_target() { + fi + } + ++# Strip all the native bits from ldflags ++strip_unwanted_llvm_ldflags() { ++ flags="" ++ for flag in `$1`; do ++ case "$flag" in ++ *native*) ;; ++ *) flags="$flags $flag" ++ ;; ++ esac ++ done ++ echo $flags ++} ++ + # Call this inside ` ` to get the return value. + # $1 is the llvm-config command with arguments. + strip_unwanted_llvm_flags() { +@@ -2661,7 +2674,7 @@ dnl + if test "x$enable_llvm" = xyes; then + DEFINES="${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT -DMESA_LLVM_VERSION_PATCH=$LLVM_VERSION_PATCH" + +- LLVM_LDFLAGS=`$LLVM_CONFIG --ldflags` ++ LLVM_LDFLAGS=`strip_unwanted_llvm_ldflags "$LLVM_CONFIG --ldflags"` + LLVM_CFLAGS=$LLVM_CPPFLAGS # CPPFLAGS seem to be sufficient + LLVM_CXXFLAGS=`strip_unwanted_llvm_flags "$LLVM_CONFIG --cxxflags"` + diff --git a/common/recipes-graphics/mesa/mesa/0004-egd_tables.py-fix-compatibility-with-python-versions.patch b/common/recipes-graphics/mesa/mesa/0004-egd_tables.py-fix-compatibility-with-python-versions.patch new file mode 100644 index 00000000..78a114b2 --- /dev/null +++ b/common/recipes-graphics/mesa/mesa/0004-egd_tables.py-fix-compatibility-with-python-versions.patch @@ -0,0 +1,141 @@ +From 2c644a3fff4cb3dd813041a23228f324cebfc1ee Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Thu, 11 Jan 2018 15:12:01 +0500 +Subject: [PATCH] egd_tables.py: fix compatibility with python versions + +There are differences in the print function between +py2 and py3 that render the definition incompatible +between the two. This updates the egd_tables.py so +it is workable on both py2 and py3. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + src/gallium/drivers/r600/egd_tables.py | 56 +++++++++++++++++----------------- + 1 file changed, 28 insertions(+), 28 deletions(-) + +diff --git a/src/gallium/drivers/r600/egd_tables.py b/src/gallium/drivers/r600/egd_tables.py +index d7b78c7..b812105 100644 +--- a/src/gallium/drivers/r600/egd_tables.py ++++ b/src/gallium/drivers/r600/egd_tables.py +@@ -47,7 +47,7 @@ class StringTable: + return idx + + idx = self.length +- self.table.append((string, idx, set((idx,)))) ++ self.table.append((string, idx, {idx})) + self.length += len(string) + 1 + + return idx +@@ -60,7 +60,7 @@ class StringTable: + """ + fragments = [ + '"%s\\0" /* %s */' % ( +- te[0].encode('string_escape'), ++ te[0], + ', '.join(str(idx) for idx in te[2]) + ) + for te in self.table +@@ -181,7 +181,7 @@ def parse(filename, regs, packets): + name = split[0] + value = int(split[1], 0) + +- for (n,v) in field.values: ++ for (n, v) in field.values: + if n == name: + if v != value: + sys.exit('Value mismatch: name = ' + name) +@@ -217,10 +217,10 @@ def write_tables(regs, packets): + strings = StringTable() + strings_offsets = IntTable("int") + +- print '/* This file is autogenerated by egd_tables.py from evergreend.h. Do not edit directly. */' +- print +- print CopyRight.strip() +- print ''' ++ print('/* This file is autogenerated by egd_tables.py from evergreend.h. Do not edit directly. */') ++ print() ++ print((CopyRight.strip())) ++ print(''' + #ifndef EG_TABLES_H + #define EG_TABLES_H + +@@ -242,20 +242,20 @@ struct eg_packet3 { + unsigned name_offset; + unsigned op; + }; +-''' ++''') + +- print 'static const struct eg_packet3 packet3_table[] = {' ++ print('static const struct eg_packet3 packet3_table[] = {') + for pkt in packets: +- print '\t{%s, %s},' % (strings.add(pkt[5:]), pkt) +- print '};' +- print ++ print(('\t{%s, %s},' % (strings.add(pkt[5:]), pkt))) ++ print('};') ++ print() + +- print 'static const struct eg_field egd_fields_table[] = {' ++ print('static const struct eg_field egd_fields_table[] = {') + + fields_idx = 0 + for reg in regs: + if len(reg.fields) and reg.own_fields: +- print '\t/* %s */' % (fields_idx) ++ print(('\t/* %s */' % (fields_idx))) + + reg.fields_idx = fields_idx + +@@ -266,34 +266,34 @@ struct eg_packet3 { + while value[1] >= len(values_offsets): + values_offsets.append(-1) + values_offsets[value[1]] = strings.add(strip_prefix(value[0])) +- print '\t{%s, %s(~0u), %s, %s},' % ( ++ print(('\t{%s, %s(~0u), %s, %s},' % ( + strings.add(field.name), field.s_name, +- len(values_offsets), strings_offsets.add(values_offsets)) ++ len(values_offsets), strings_offsets.add(values_offsets)))) + else: +- print '\t{%s, %s(~0u)},' % (strings.add(field.name), field.s_name) ++ print(('\t{%s, %s(~0u)},' % (strings.add(field.name), field.s_name))) + fields_idx += 1 + +- print '};' +- print ++ print('};') ++ print() + +- print 'static const struct eg_reg egd_reg_table[] = {' ++ print('static const struct eg_reg egd_reg_table[] = {') + for reg in regs: + if len(reg.fields): +- print '\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name, +- len(reg.fields), reg.fields_idx if reg.own_fields else reg.fields_owner.fields_idx) ++ print(('\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name, ++ len(reg.fields), reg.fields_idx if reg.own_fields else reg.fields_owner.fields_idx))) + else: +- print '\t{%s, %s},' % (strings.add(reg.name), reg.r_name) +- print '};' +- print ++ print(('\t{%s, %s},' % (strings.add(reg.name), reg.r_name))) ++ print('};') ++ print() + + strings.emit(sys.stdout, "egd_strings") + +- print ++ print() + + strings_offsets.emit(sys.stdout, "egd_strings_offsets") + +- print +- print '#endif' ++ print() ++ print('#endif') + + + def main(): +-- +2.11.1 + diff --git a/common/recipes-graphics/mesa/mesa/0004-st-mesa-fix-swizzle-issue-in-st_create_sampler_view_.patch b/common/recipes-graphics/mesa/mesa/0004-st-mesa-fix-swizzle-issue-in-st_create_sampler_view_.patch deleted file mode 100644 index 49d86284..00000000 --- a/common/recipes-graphics/mesa/mesa/0004-st-mesa-fix-swizzle-issue-in-st_create_sampler_view_.patch +++ /dev/null @@ -1,60 +0,0 @@ -From ad54beec2c5a8774b0db77116bc7061b46e97cda Mon Sep 17 00:00:00 2001 -From: Brian Paul <brianp@vmware.com> -Date: Thu, 22 Sep 2016 16:03:40 -0600 -Subject: [PATCH 4/4] st/mesa: fix swizzle issue in - st_create_sampler_view_from_stobj() - -Some demos, like Heaven, were creating and destroying a large number -of sampler views because of a swizzle issue. - -Basically, we compute the sampler view's swizzle by examining the -texture format, user swizzle, depth mode, etc. Later, during validation -we recompute that swizzle (in case something like depth mode changes) -and see if it matches the view's swizzle. - -In the case of PIPE_FORMAT_RGTC2_UNORM, get_texture_format_swizzle -returned SWIZZLE_XYZW but the u_sampler_view_default_template() function -was setting the sampler view's swizzle to SWIZZLE_XY01. This mismatch -caused the validation step to always "fail" so we'd destroy the old -sampler view and create a new one. - -By removing the conditional, the sampler view's swizzle and the computed -texture swizzle match and validation "passes". When creating a new sampler -view, we always want to use the texture swizzle which we just computed. - -Fixes VMware issue 1733389. - -Cc: mesa-stable@lists.freedesktop.org - -Reviewed-by: Charmaine Lee <charmainel@vmware.com> -(cherry picked from commit 1cdc232e1ae683a7c45f81b44818cf8656480df8) - -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - src/mesa/state_tracker/st_atom_texture.c | 10 ++++------ - 1 file changed, 4 insertions(+), 6 deletions(-) - -diff --git a/src/mesa/state_tracker/st_atom_texture.c b/src/mesa/state_tracker/st_atom_texture.c -index 4b7ad77..3d409a6 100644 ---- a/src/mesa/state_tracker/st_atom_texture.c -+++ b/src/mesa/state_tracker/st_atom_texture.c -@@ -304,12 +304,10 @@ st_create_texture_sampler_view_from_stobj(struct st_context *st, - templ.target = gl_target_to_pipe(stObj->base.Target); - } - -- if (swizzle != SWIZZLE_NOOP) { -- templ.swizzle_r = GET_SWZ(swizzle, 0); -- templ.swizzle_g = GET_SWZ(swizzle, 1); -- templ.swizzle_b = GET_SWZ(swizzle, 2); -- templ.swizzle_a = GET_SWZ(swizzle, 3); -- } -+ templ.swizzle_r = GET_SWZ(swizzle, 0); -+ templ.swizzle_g = GET_SWZ(swizzle, 1); -+ templ.swizzle_b = GET_SWZ(swizzle, 2); -+ templ.swizzle_a = GET_SWZ(swizzle, 3); - - return st->pipe->create_sampler_view(st->pipe, stObj->pt, &templ); - } --- -2.7.4 - diff --git a/common/recipes-graphics/mesa/mesa/0005-Revert-winsys-amdgpu-add-back-multithreaded-command-.patch b/common/recipes-graphics/mesa/mesa/0005-Revert-winsys-amdgpu-add-back-multithreaded-command-.patch deleted file mode 100644 index f1fea9d4..00000000 --- a/common/recipes-graphics/mesa/mesa/0005-Revert-winsys-amdgpu-add-back-multithreaded-command-.patch +++ /dev/null @@ -1,886 +0,0 @@ -From 71a23f2be79ed306d622701518d28b99ce21669e Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <Sanju.Mehta@amd.com> -Date: Thu, 23 Mar 2017 13:29:15 +0530 -Subject: [PATCH] Revert "winsys/amdgpu: add back multithreaded command - submission" - -This reverts commit 53f33619a47b014b9ba7cc88310611081c5916db. ---- - src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 30 +-- - src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 4 - - src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 313 +++++++++----------------- - src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 52 ++--- - src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 63 ------ - src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 10 - - 6 files changed, 131 insertions(+), 341 deletions(-) - -diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c -index 2555d57..bd69790 100644 ---- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c -+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c -@@ -43,21 +43,8 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t timeout, - { - struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); - struct amdgpu_winsys *ws = bo->ws; -- int64_t abs_timeout; - int i; - -- if (timeout == 0) { -- if (p_atomic_read(&bo->num_active_ioctls)) -- return false; -- -- } else { -- abs_timeout = os_time_get_absolute_timeout(timeout); -- -- /* Wait if any ioctl is being submitted with this buffer. */ -- if (!os_wait_until_zero_abs_timeout(&bo->num_active_ioctls, abs_timeout)) -- return false; -- } -- - if (bo->is_shared) { - /* We can't use user fences for shared buffers, because user fences - * are local to this process only. If we want to wait for all buffer -@@ -74,6 +61,7 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t timeout, - } - - if (timeout == 0) { -+ /* Timeout == 0 is quite simple. */ - pipe_mutex_lock(ws->bo_fence_lock); - for (i = 0; i < RING_LAST; i++) - if (bo->fence[i]) { -@@ -92,6 +80,7 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t timeout, - struct pipe_fence_handle *fence[RING_LAST] = {}; - bool fence_idle[RING_LAST] = {}; - bool buffer_idle = true; -+ int64_t abs_timeout = os_time_get_absolute_timeout(timeout); - - /* Take references to all fences, so that we can wait for them - * without the lock. */ -@@ -220,24 +209,13 @@ static void *amdgpu_bo_map(struct pb_buffer *buf, - if (cs && amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, - RADEON_USAGE_WRITE)) { - cs->flush_cs(cs->flush_data, 0, NULL); -- } else { -- /* Try to avoid busy-waiting in amdgpu_bo_wait. */ -- if (p_atomic_read(&bo->num_active_ioctls)) -- amdgpu_cs_sync_flush(rcs); - } - amdgpu_bo_wait((struct pb_buffer*)bo, PIPE_TIMEOUT_INFINITE, - RADEON_USAGE_WRITE); - } else { - /* Mapping for write. */ -- if (cs) { -- if (amdgpu_bo_is_referenced_by_cs(cs, bo)) { -- cs->flush_cs(cs->flush_data, 0, NULL); -- } else { -- /* Try to avoid busy-waiting in amdgpu_bo_wait. */ -- if (p_atomic_read(&bo->num_active_ioctls)) -- amdgpu_cs_sync_flush(rcs); -- } -- } -+ if (cs && amdgpu_bo_is_referenced_by_cs(cs, bo)) -+ cs->flush_cs(cs->flush_data, 0, NULL); - - amdgpu_bo_wait((struct pb_buffer*)bo, PIPE_TIMEOUT_INFINITE, - RADEON_USAGE_READWRITE); -diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h -index a768771..69ada10 100644 ---- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h -+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h -@@ -53,10 +53,6 @@ struct amdgpu_winsys_bo { - /* how many command streams is this bo referenced in? */ - int num_cs_references; - -- /* how many command streams, which are being emitted in a separate -- * thread, is this bo referenced in? */ -- volatile int num_active_ioctls; -- - /* whether buffer_get_handle or buffer_from_handle was called, - * it can only transition from false to true - */ -diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c -index e949874..ffb0b7b 100644 ---- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c -+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c -@@ -50,7 +50,6 @@ amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type, - fence->fence.ip_type = ip_type; - fence->fence.ip_instance = ip_instance; - fence->fence.ring = ring; -- fence->submission_in_progress = true; - p_atomic_inc(&ctx->refcount); - return (struct pipe_fence_handle *)fence; - } -@@ -63,7 +62,6 @@ static void amdgpu_fence_submitted(struct pipe_fence_handle *fence, - - rfence->fence.fence = request->seq_no; - rfence->user_fence_cpu_address = user_fence_cpu_address; -- rfence->submission_in_progress = false; - } - - static void amdgpu_fence_signalled(struct pipe_fence_handle *fence) -@@ -71,7 +69,6 @@ static void amdgpu_fence_signalled(struct pipe_fence_handle *fence) - struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence; - - rfence->signalled = true; -- rfence->submission_in_progress = false; - } - - bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout, -@@ -91,13 +88,6 @@ bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout, - else - abs_timeout = os_time_get_absolute_timeout(timeout); - -- /* The fence might not have a number assigned if its IB is being -- * submitted in the other thread right now. Wait until the submission -- * is done. */ -- if (!os_wait_until_zero_abs_timeout(&rfence->submission_in_progress, -- abs_timeout)) -- return false; -- - user_fence_cpu = rfence->user_fence_cpu_address; - if (user_fence_cpu) { - if (*user_fence_cpu >= rfence->fence.fence) { -@@ -280,7 +270,7 @@ static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib, - return true; - } - --static boolean amdgpu_init_cs_context(struct amdgpu_cs_context *cs, -+static boolean amdgpu_init_cs_context(struct amdgpu_cs *cs, - enum ring_type ring_type) - { - int i; -@@ -331,18 +321,10 @@ static boolean amdgpu_init_cs_context(struct amdgpu_cs_context *cs, - for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) { - cs->buffer_indices_hashlist[i] = -1; - } -- -- cs->request.number_of_ibs = 1; -- cs->request.ibs = &cs->ib[IB_MAIN]; -- -- cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE; -- cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE | -- AMDGPU_IB_FLAG_PREAMBLE; -- - return TRUE; - } - --static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs) -+static void amdgpu_cs_context_cleanup(struct amdgpu_cs *cs) - { - unsigned i; - -@@ -356,14 +338,13 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs) - cs->num_buffers = 0; - cs->used_gart = 0; - cs->used_vram = 0; -- amdgpu_fence_reference(&cs->fence, NULL); - - for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) { - cs->buffer_indices_hashlist[i] = -1; - } - } - --static void amdgpu_destroy_cs_context(struct amdgpu_cs_context *cs) -+static void amdgpu_destroy_cs_context(struct amdgpu_cs *cs) - { - amdgpu_cs_context_cleanup(cs); - FREE(cs->flags); -@@ -388,35 +369,24 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx, - return NULL; - } - -- pipe_semaphore_init(&cs->flush_completed, 1); -- - cs->ctx = ctx; - cs->flush_cs = flush; - cs->flush_data = flush_ctx; - cs->ring_type = ring_type; - -- if (!amdgpu_init_cs_context(&cs->csc1, ring_type)) { -+ if (!amdgpu_init_cs_context(cs, ring_type)) { - FREE(cs); - return NULL; - } - -- if (!amdgpu_init_cs_context(&cs->csc2, ring_type)) { -- amdgpu_destroy_cs_context(&cs->csc1); -+ if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN)) { -+ amdgpu_destroy_cs_context(cs); - FREE(cs); - return NULL; - } - -- /* Set the first submission context as current. */ -- cs->csc = &cs->csc1; -- cs->cst = &cs->csc2; -- -- if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->csc->ib[IB_MAIN], -- IB_MAIN)) { -- amdgpu_destroy_cs_context(&cs->csc2); -- amdgpu_destroy_cs_context(&cs->csc1); -- FREE(cs); -- return NULL; -- } -+ cs->request.number_of_ibs = 1; -+ cs->request.ibs = &cs->ib[IB_MAIN]; - - p_atomic_inc(&ctx->ws->num_cs); - return &cs->main.base; -@@ -432,15 +402,12 @@ amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs) - if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped) - return NULL; - -- if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->csc->ib[IB_CONST], -- IB_CONST)) -+ if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST)) - return NULL; - -- cs->csc->request.number_of_ibs = 2; -- cs->csc->request.ibs = &cs->csc->ib[IB_CONST]; -- -- cs->cst->request.number_of_ibs = 2; -- cs->cst->request.ibs = &cs->cst->ib[IB_CONST]; -+ cs->request.number_of_ibs = 2; -+ cs->request.ibs = &cs->ib[IB_CONST]; -+ cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE; - - return &cs->const_ib.base; - } -@@ -458,21 +425,19 @@ amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs) - return NULL; - - if (!amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib, -- &cs->csc->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE)) -+ &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE)) - return NULL; - -- cs->csc->request.number_of_ibs = 3; -- cs->csc->request.ibs = &cs->csc->ib[IB_CONST_PREAMBLE]; -- -- cs->cst->request.number_of_ibs = 3; -- cs->cst->request.ibs = &cs->cst->ib[IB_CONST_PREAMBLE]; -+ cs->request.number_of_ibs = 3; -+ cs->request.ibs = &cs->ib[IB_CONST_PREAMBLE]; -+ cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE | AMDGPU_IB_FLAG_PREAMBLE; - - return &cs->const_preamble_ib.base; - } - - #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value) - --int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo) -+int amdgpu_lookup_buffer(struct amdgpu_cs *cs, struct amdgpu_winsys_bo *bo) - { - unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1); - int i = cs->buffer_indices_hashlist[hash]; -@@ -500,14 +465,13 @@ int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo * - return -1; - } - --static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs, -+static unsigned amdgpu_add_buffer(struct amdgpu_cs *cs, - struct amdgpu_winsys_bo *bo, - enum radeon_bo_usage usage, - enum radeon_bo_domain domains, - unsigned priority, - enum radeon_bo_domain *added_domains) - { -- struct amdgpu_cs_context *cs = acs->csc; - struct amdgpu_cs_buffer *buffer; - unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1); - int i = -1; -@@ -575,9 +539,9 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs, - priority, &added_domains); - - if (added_domains & RADEON_DOMAIN_VRAM) -- cs->csc->used_vram += bo->base.size; -+ cs->used_vram += bo->base.size; - else if (added_domains & RADEON_DOMAIN_GTT) -- cs->csc->used_gart += bo->base.size; -+ cs->used_gart += bo->base.size; - - return index; - } -@@ -587,7 +551,7 @@ static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs, - { - struct amdgpu_cs *cs = amdgpu_cs(rcs); - -- return amdgpu_lookup_buffer(cs->csc, (struct amdgpu_winsys_bo*)buf); -+ return amdgpu_lookup_buffer(cs, (struct amdgpu_winsys_bo*)buf); - } - - static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs) -@@ -600,8 +564,8 @@ static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64 - struct amdgpu_cs *cs = amdgpu_cs(rcs); - struct amdgpu_winsys *ws = cs->ctx->ws; - -- vram += cs->csc->used_vram; -- gtt += cs->csc->used_gart; -+ vram += cs->used_vram; -+ gtt += cs->used_gart; - - /* Anything that goes above the VRAM size should go to GTT. */ - if (vram > ws->info.vram_size) -@@ -613,7 +577,7 @@ static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64 - - static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs *rcs) - { -- struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc; -+ struct amdgpu_cs *cs = amdgpu_cs(rcs); - - return cs->used_vram + cs->used_gart; - } -@@ -621,7 +585,7 @@ static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs *rcs) - static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs, - struct radeon_bo_list_item *list) - { -- struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc; -+ struct amdgpu_cs *cs = amdgpu_cs(rcs); - int i; - - if (list) { -@@ -634,18 +598,26 @@ static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs, - return cs->num_buffers; - } - --DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE) -- --/* Since the kernel driver doesn't synchronize execution between different -- * rings automatically, we have to add fence dependencies manually. -- */ --static void amdgpu_add_fence_dependencies(struct amdgpu_cs *acs) -+static void amdgpu_cs_do_submission(struct amdgpu_cs *cs, -+ struct pipe_fence_handle **out_fence) - { -- struct amdgpu_cs_context *cs = acs->csc; -- int i, j; -+ struct amdgpu_winsys *ws = cs->ctx->ws; -+ struct pipe_fence_handle *fence; -+ int i, j, r; -+ -+ /* Create a fence. */ -+ fence = amdgpu_fence_create(cs->ctx, -+ cs->request.ip_type, -+ cs->request.ip_instance, -+ cs->request.ring); -+ if (out_fence) -+ amdgpu_fence_reference(out_fence, fence); - - cs->request.number_of_dependencies = 0; - -+ /* Since the kernel driver doesn't synchronize execution between different -+ * rings automatically, we have to add fence dependencies manually. */ -+ pipe_mutex_lock(ws->bo_fence_lock); - for (i = 0; i < cs->num_buffers; i++) { - for (j = 0; j < RING_LAST; j++) { - struct amdgpu_cs_fence *dep; -@@ -655,7 +627,7 @@ static void amdgpu_add_fence_dependencies(struct amdgpu_cs *acs) - if (!bo_fence) - continue; - -- if (bo_fence->ctx == acs->ctx && -+ if (bo_fence->ctx == cs->ctx && - bo_fence->fence.ip_type == cs->request.ip_type && - bo_fence->fence.ip_instance == cs->request.ip_instance && - bo_fence->fence.ring == cs->request.ring) -@@ -664,10 +636,6 @@ static void amdgpu_add_fence_dependencies(struct amdgpu_cs *acs) - if (amdgpu_fence_wait((void *)bo_fence, 0, false)) - continue; - -- if (bo_fence->submission_in_progress) -- os_wait_until_zero(&bo_fence->submission_in_progress, -- PIPE_TIMEOUT_INFINITE); -- - idx = cs->request.number_of_dependencies++; - if (idx >= cs->max_dependencies) { - unsigned size; -@@ -681,62 +649,14 @@ static void amdgpu_add_fence_dependencies(struct amdgpu_cs *acs) - memcpy(dep, &bo_fence->fence, sizeof(*dep)); - } - } --} -- --void amdgpu_cs_submit_ib(struct amdgpu_cs *acs) --{ -- struct amdgpu_winsys *ws = acs->ctx->ws; -- struct amdgpu_cs_context *cs = acs->cst; -- int i, r; - - cs->request.fence_info.handle = NULL; -- if (cs->request.ip_type != AMDGPU_HW_IP_UVD && -- cs->request.ip_type != AMDGPU_HW_IP_VCE) { -- cs->request.fence_info.handle = acs->ctx->user_fence_bo; -- cs->request.fence_info.offset = acs->ring_type; -- } -- -- /* Create the buffer list. -- * Use a buffer list containing all allocated buffers if requested. -- */ -- if (debug_get_option_all_bos()) { -- struct amdgpu_winsys_bo *bo; -- amdgpu_bo_handle *handles; -- unsigned num = 0; -- -- pipe_mutex_lock(ws->global_bo_list_lock); -- -- handles = malloc(sizeof(handles[0]) * ws->num_buffers); -- if (!handles) { -- pipe_mutex_unlock(ws->global_bo_list_lock); -- amdgpu_cs_context_cleanup(cs); -- return; -- } -- -- LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) { -- assert(num < ws->num_buffers); -- handles[num++] = bo->bo; -- } -- -- r = amdgpu_bo_list_create(ws->dev, ws->num_buffers, -- handles, NULL, -- &cs->request.resources); -- free(handles); -- pipe_mutex_unlock(ws->global_bo_list_lock); -- } else { -- r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, -- cs->handles, cs->flags, -- &cs->request.resources); -- } -- -- if (r) { -- fprintf(stderr, "amdgpu: buffer list creation failed (%d)\n", r); -- cs->request.resources = NULL; -- amdgpu_fence_signalled(cs->fence); -- goto cleanup; -+ if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE) { -+ cs->request.fence_info.handle = cs->ctx->user_fence_bo; -+ cs->request.fence_info.offset = cs->ring_type; - } - -- r = amdgpu_cs_submit(acs->ctx->ctx, 0, &cs->request, 1); -+ r = amdgpu_cs_submit(cs->ctx->ctx, 0, &cs->request, 1); - if (r) { - if (r == -ENOMEM) - fprintf(stderr, "amdgpu: Not enough memory for command submission.\n"); -@@ -744,43 +664,30 @@ void amdgpu_cs_submit_ib(struct amdgpu_cs *acs) - fprintf(stderr, "amdgpu: The CS has been rejected, " - "see dmesg for more information.\n"); - -- amdgpu_fence_signalled(cs->fence); -+ amdgpu_fence_signalled(fence); - } else { - /* Success. */ - uint64_t *user_fence = NULL; -- if (cs->request.ip_type != AMDGPU_HW_IP_UVD && -- cs->request.ip_type != AMDGPU_HW_IP_VCE) -- user_fence = acs->ctx->user_fence_cpu_address_base + -+ if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE) -+ user_fence = cs->ctx->user_fence_cpu_address_base + - cs->request.fence_info.offset; -- amdgpu_fence_submitted(cs->fence, &cs->request, user_fence); -- } -- -- /* Cleanup. */ -- if (cs->request.resources) -- amdgpu_bo_list_destroy(cs->request.resources); -- --cleanup: -- for (i = 0; i < cs->num_buffers; i++) -- p_atomic_dec(&cs->buffers[i].bo->num_active_ioctls); -+ amdgpu_fence_submitted(fence, &cs->request, user_fence); - -- amdgpu_cs_context_cleanup(cs); -+ for (i = 0; i < cs->num_buffers; i++) -+ amdgpu_fence_reference(&cs->buffers[i].bo->fence[cs->ring_type], -+ fence); -+ } -+ pipe_mutex_unlock(ws->bo_fence_lock); -+ amdgpu_fence_reference(&fence, NULL); - } - --/* Make sure the previous submission is completed. */ --void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs) -+static void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs) - { -- struct amdgpu_cs *cs = amdgpu_cs(rcs); -- -- /* Wait for any pending ioctl of this CS to complete. */ -- if (cs->ctx->ws->thread) { -- /* wait and set the semaphore to "busy" */ -- pipe_semaphore_wait(&cs->flush_completed); -- /* set the semaphore to "idle" */ -- pipe_semaphore_signal(&cs->flush_completed); -- } -+ /* no-op */ - } - - DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE) -+DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE) - - static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs, - unsigned flags, -@@ -833,69 +740,74 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs, - RADEON_USAGE_READ, 0, RADEON_PRIO_IB1); - - /* If the CS is not empty or overflowed.... */ -- if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw && -- !debug_get_option_noop()) { -- struct amdgpu_cs_context *cur = cs->csc; -- unsigned i, num_buffers = cur->num_buffers; -+ if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw && !debug_get_option_noop()) { -+ int r; -+ -+ /* Use a buffer list containing all allocated buffers if requested. */ -+ if (debug_get_option_all_bos()) { -+ struct amdgpu_winsys_bo *bo; -+ amdgpu_bo_handle *handles; -+ unsigned num = 0; -+ -+ pipe_mutex_lock(ws->global_bo_list_lock); -+ -+ handles = malloc(sizeof(handles[0]) * ws->num_buffers); -+ if (!handles) { -+ pipe_mutex_unlock(ws->global_bo_list_lock); -+ goto cleanup; -+ } -+ -+ LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) { -+ assert(num < ws->num_buffers); -+ handles[num++] = bo->bo; -+ } -+ -+ r = amdgpu_bo_list_create(ws->dev, ws->num_buffers, -+ handles, NULL, -+ &cs->request.resources); -+ free(handles); -+ pipe_mutex_unlock(ws->global_bo_list_lock); -+ } else { -+ r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, -+ cs->handles, cs->flags, -+ &cs->request.resources); -+ } -+ -+ if (r) { -+ fprintf(stderr, "amdgpu: resource list creation failed (%d)\n", r); -+ cs->request.resources = NULL; -+ goto cleanup; -+ } - -- /* Set IB sizes. */ -- cur->ib[IB_MAIN].size = cs->main.base.cdw; -+ cs->ib[IB_MAIN].size = cs->main.base.cdw; - cs->main.used_ib_space += cs->main.base.cdw * 4; - - if (cs->const_ib.ib_mapped) { -- cur->ib[IB_CONST].size = cs->const_ib.base.cdw; -+ cs->ib[IB_CONST].size = cs->const_ib.base.cdw; - cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4; - } - - if (cs->const_preamble_ib.ib_mapped) { -- cur->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw; -+ cs->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw; - cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4; - } - -- /* Create a fence. */ -- amdgpu_fence_reference(&cur->fence, NULL); -- cur->fence = amdgpu_fence_create(cs->ctx, -- cur->request.ip_type, -- cur->request.ip_instance, -- cur->request.ring); -- if (fence) -- amdgpu_fence_reference(fence, cur->fence); -- -- /* Prepare buffers. */ -- pipe_mutex_lock(ws->bo_fence_lock); -- amdgpu_add_fence_dependencies(cs); -- for (i = 0; i < num_buffers; i++) { -- p_atomic_inc(&cur->buffers[i].bo->num_active_ioctls); -- amdgpu_fence_reference(&cur->buffers[i].bo->fence[cs->ring_type], -- cur->fence); -- } -- pipe_mutex_unlock(ws->bo_fence_lock); -- -- amdgpu_cs_sync_flush(rcs); -- -- /* Swap command streams. "cst" is going to be submitted. */ -- cs->csc = cs->cst; -- cs->cst = cur; -+ amdgpu_cs_do_submission(cs, fence); - -- /* Submit. */ -- if (ws->thread && (flags & RADEON_FLUSH_ASYNC)) { -- /* Set the semaphore to "busy". */ -- pipe_semaphore_wait(&cs->flush_completed); -- amdgpu_ws_queue_cs(ws, cs); -- } else { -- amdgpu_cs_submit_ib(cs); -- } -- } else { -- amdgpu_cs_context_cleanup(cs->csc); -+ /* Cleanup. */ -+ if (cs->request.resources) -+ amdgpu_bo_list_destroy(cs->request.resources); - } - -- amdgpu_get_new_ib(&ws->base, &cs->main, &cs->csc->ib[IB_MAIN], IB_MAIN); -+cleanup: -+ amdgpu_cs_context_cleanup(cs); -+ -+ amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN); - if (cs->const_ib.ib_mapped) -- amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->csc->ib[IB_CONST], -- IB_CONST); -+ amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST); - if (cs->const_preamble_ib.ib_mapped) - amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib, -- &cs->csc->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE); -+ &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE); - - ws->num_cs_flushes++; - } -@@ -904,14 +816,11 @@ static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs) - { - struct amdgpu_cs *cs = amdgpu_cs(rcs); - -- amdgpu_cs_sync_flush(rcs); -- pipe_semaphore_destroy(&cs->flush_completed); -+ amdgpu_destroy_cs_context(cs); - p_atomic_dec(&cs->ctx->ws->num_cs); - pb_reference(&cs->main.big_ib_buffer, NULL); - pb_reference(&cs->const_ib.big_ib_buffer, NULL); - pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL); -- amdgpu_destroy_cs_context(&cs->csc1); -- amdgpu_destroy_cs_context(&cs->csc2); - FREE(cs); - } - -diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h -index 1caec0a..4ed830b 100644 ---- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h -+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h -@@ -66,7 +66,18 @@ enum { - IB_NUM - }; - --struct amdgpu_cs_context { -+struct amdgpu_cs { -+ struct amdgpu_ib main; /* must be first because this is inherited */ -+ struct amdgpu_ib const_ib; /* optional constant engine IB */ -+ struct amdgpu_ib const_preamble_ib; -+ struct amdgpu_ctx *ctx; -+ -+ /* Flush CS. */ -+ void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence); -+ void *flush_data; -+ -+ /* amdgpu_cs_submit parameters */ -+ enum ring_type ring_type; - struct amdgpu_cs_request request; - struct amdgpu_cs_ib_info ib[IB_NUM]; - -@@ -83,32 +94,6 @@ struct amdgpu_cs_context { - uint64_t used_gart; - - unsigned max_dependencies; -- -- struct pipe_fence_handle *fence; --}; -- --struct amdgpu_cs { -- struct amdgpu_ib main; /* must be first because this is inherited */ -- struct amdgpu_ib const_ib; /* optional constant engine IB */ -- struct amdgpu_ib const_preamble_ib; -- struct amdgpu_ctx *ctx; -- enum ring_type ring_type; -- -- /* We flip between these two CS. While one is being consumed -- * by the kernel in another thread, the other one is being filled -- * by the pipe driver. */ -- struct amdgpu_cs_context csc1; -- struct amdgpu_cs_context csc2; -- /* The currently-used CS. */ -- struct amdgpu_cs_context *csc; -- /* The CS being currently-owned by the other thread. */ -- struct amdgpu_cs_context *cst; -- -- /* Flush CS. */ -- void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence); -- void *flush_data; -- -- pipe_semaphore flush_completed; - }; - - struct amdgpu_fence { -@@ -118,9 +103,6 @@ struct amdgpu_fence { - struct amdgpu_cs_fence fence; - uint64_t *user_fence_cpu_address; - -- /* If the fence is unknown due to an IB still being submitted -- * in the other thread. */ -- volatile int submission_in_progress; /* bool (int for atomicity) */ - volatile int signalled; /* bool (int for atomicity) */ - }; - -@@ -146,7 +128,7 @@ static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst, - *rdst = rsrc; - } - --int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo); -+int amdgpu_lookup_buffer(struct amdgpu_cs *csc, struct amdgpu_winsys_bo *bo); - - static inline struct amdgpu_cs * - amdgpu_cs(struct radeon_winsys_cs *base) -@@ -160,7 +142,7 @@ amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs, - { - int num_refs = bo->num_cs_references; - return num_refs == bo->ws->num_cs || -- (num_refs && amdgpu_lookup_buffer(cs->csc, bo) != -1); -+ (num_refs && amdgpu_lookup_buffer(cs, bo) != -1); - } - - static inline boolean -@@ -173,11 +155,11 @@ amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs, - if (!bo->num_cs_references) - return FALSE; - -- index = amdgpu_lookup_buffer(cs->csc, bo); -+ index = amdgpu_lookup_buffer(cs, bo); - if (index == -1) - return FALSE; - -- return (cs->csc->buffers[index].usage & usage) != 0; -+ return (cs->buffers[index].usage & usage) != 0; - } - - static inline boolean -@@ -188,8 +170,6 @@ amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo *bo) - - bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout, - bool absolute); --void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs); - void amdgpu_cs_init_functions(struct amdgpu_winsys *ws); --void amdgpu_cs_submit_ib(struct amdgpu_cs *cs); - - #endif -diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c -index 4e2cefc..bd08d9d 100644 ---- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c -+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c -@@ -317,14 +317,6 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws) - { - struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws; - -- if (ws->thread) { -- ws->kill_thread = 1; -- pipe_semaphore_signal(&ws->cs_queued); -- pipe_thread_wait(ws->thread); -- } -- pipe_semaphore_destroy(&ws->cs_queue_has_space); -- pipe_semaphore_destroy(&ws->cs_queued); -- pipe_mutex_destroy(ws->cs_queue_lock); - pipe_mutex_destroy(ws->bo_fence_lock); - pb_cache_deinit(&ws->bo_cache); - pipe_mutex_destroy(ws->global_bo_list_lock); -@@ -409,54 +401,6 @@ static int compare_dev(void *key1, void *key2) - return key1 != key2; - } - --void amdgpu_ws_queue_cs(struct amdgpu_winsys *ws, struct amdgpu_cs *cs) --{ -- pipe_semaphore_wait(&ws->cs_queue_has_space); -- -- pipe_mutex_lock(ws->cs_queue_lock); -- assert(ws->num_enqueued_cs < ARRAY_SIZE(ws->cs_queue)); -- ws->cs_queue[ws->num_enqueued_cs++] = cs; -- pipe_mutex_unlock(ws->cs_queue_lock); -- pipe_semaphore_signal(&ws->cs_queued); --} -- --static PIPE_THREAD_ROUTINE(amdgpu_cs_thread_func, param) --{ -- struct amdgpu_winsys *ws = (struct amdgpu_winsys *)param; -- struct amdgpu_cs *cs; -- unsigned i; -- -- while (1) { -- pipe_semaphore_wait(&ws->cs_queued); -- if (ws->kill_thread) -- break; -- -- pipe_mutex_lock(ws->cs_queue_lock); -- cs = ws->cs_queue[0]; -- for (i = 1; i < ws->num_enqueued_cs; i++) -- ws->cs_queue[i - 1] = ws->cs_queue[i]; -- ws->cs_queue[--ws->num_enqueued_cs] = NULL; -- pipe_mutex_unlock(ws->cs_queue_lock); -- -- pipe_semaphore_signal(&ws->cs_queue_has_space); -- -- if (cs) { -- amdgpu_cs_submit_ib(cs); -- pipe_semaphore_signal(&cs->flush_completed); -- } -- } -- pipe_mutex_lock(ws->cs_queue_lock); -- for (i = 0; i < ws->num_enqueued_cs; i++) { -- pipe_semaphore_signal(&ws->cs_queue[i]->flush_completed); -- ws->cs_queue[i] = NULL; -- } -- pipe_mutex_unlock(ws->cs_queue_lock); -- return 0; --} -- --DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE) --static PIPE_THREAD_ROUTINE(amdgpu_cs_thread_func, param); -- - static bool amdgpu_winsys_unref(struct radeon_winsys *rws) - { - struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws; -@@ -550,15 +494,8 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create) - - LIST_INITHEAD(&ws->global_bo_list); - pipe_mutex_init(ws->global_bo_list_lock); -- pipe_mutex_init(ws->cs_queue_lock); - pipe_mutex_init(ws->bo_fence_lock); - -- pipe_semaphore_init(&ws->cs_queue_has_space, ARRAY_SIZE(ws->cs_queue)); -- pipe_semaphore_init(&ws->cs_queued, 0); -- -- if (sysconf(_SC_NPROCESSORS_ONLN) > 1 && debug_get_option_thread()) -- ws->thread = pipe_thread_create(amdgpu_cs_thread_func, ws); -- - /* Create the screen at the end. The winsys must be initialized - * completely. - * -diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h -index d6734f7..f28524a 100644 ---- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h -+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h -@@ -58,15 +58,6 @@ struct amdgpu_winsys { - - struct radeon_info info; - -- /* multithreaded IB submission */ -- pipe_mutex cs_queue_lock; -- pipe_semaphore cs_queue_has_space; -- pipe_semaphore cs_queued; -- pipe_thread thread; -- int kill_thread; -- int num_enqueued_cs; -- struct amdgpu_cs *cs_queue[8]; -- - struct amdgpu_gpu_info amdinfo; - ADDR_HANDLE addrlib; - uint32_t rev_id; -@@ -84,7 +75,6 @@ amdgpu_winsys(struct radeon_winsys *base) - return (struct amdgpu_winsys*)base; - } - --void amdgpu_ws_queue_cs(struct amdgpu_winsys *ws, struct amdgpu_cs *cs); - void amdgpu_surface_init_functions(struct amdgpu_winsys *ws); - ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws); - --- -2.7.4 - diff --git a/common/recipes-graphics/mesa/mesa_git.bbappend b/common/recipes-graphics/mesa/mesa_17.3.%.bbappend index 573f8035..facae1c8 100644 --- a/common/recipes-graphics/mesa/mesa_git.bbappend +++ b/common/recipes-graphics/mesa/mesa_17.3.%.bbappend @@ -1,14 +1,13 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" -SRCREV_amd = "09460b8cf7ddac4abb46eb6439314b29954c76a6" -LIC_FILES_CHKSUM_amd = "file://docs/license.html;md5=899fbe7e42d494c7c8c159c7001693d5" -PV_amd = "12.0.3+git${SRCPV}" + DEPENDS_append_amd = " libvdpau libomxil" PACKAGECONFIG[va] = "--enable-va,--disable-va,libva" -PACKAGECONFIG_append_amd = " xvmc gallium r600 gallium-llvm xa" +PACKAGECONFIG_append_amd = " xvmc gallium r600 gallium-llvm xa osmesa" PACKAGECONFIG_append_radeon = " va" PACKAGECONFIG_append_amdgpu = " va" PACKAGECONFIG_remove_amdfalconx86 = "xvmc" +PACKAGECONFIG_remove_amd = "vulkan" LIBVA_PLATFORMS = "libva" LIBVA_PLATFORMS .= "${@bb.utils.contains('DISTRO_FEATURES', 'x11', ' libva-x11', '', d)}" @@ -16,27 +15,20 @@ LIBVA_PLATFORMS .= "${@bb.utils.contains('DISTRO_FEATURES', 'wayland', ' libva-w LIBVA_PLATFORMS .= "${@bb.utils.contains('DISTRO_FEATURES', 'opengl', ' libva-gl', '', d)}" RDEPENDS_mesa-megadriver += "${@bb.utils.contains('PACKAGECONFIG', 'va', '${LIBVA_PLATFORMS}', '', d)}" -MESA_LLVM_RELEASE_amd = "3.9" - -SRC_URI_amd = "\ - git://anongit.freedesktop.org/git/mesa/mesa;branch=12.0 \ - file://0001-reverse-the-patch-radeonsi-rework-clear_buffer-flags.patch \ - file://0002-radeonsi-silence-runtime-warnings-with-LLVM-3.9.patch \ - file://0003-st-mesa-Revert-patches-solves-perf-issues-with-mesa-.patch \ - file://0004-st-mesa-fix-swizzle-issue-in-st_create_sampler_view_.patch \ - file://0005-Revert-winsys-amdgpu-add-back-multithreaded-command-.patch \ - file://0001-radeonsi-always-set-all-blend-registers.patch \ - file://0002-radeonsi-set-CB_BLEND1_CONTROL.ENABLE-for-dual-sourc.patch \ - file://0003-radeonsi-disable-RB-blend-optimizations-for-dual-sou.patch \ +SRC_URI_append_amd = "\ + file://0001-fix-building-with-flex-2.6.2.patch \ + file://0001-configure.ac-for-llvm-config-to-report-correct-libdi.patch \ + file://0002-configure.ac-fix-the-llvm-version-correctly.patch \ + file://0003-strip-llvm-ldflags.patch \ + file://0004-egd_tables.py-fix-compatibility-with-python-versions.patch \ " EXTRA_OECONF_append_amd = " \ --enable-vdpau \ - --enable-osmesa \ --enable-glx \ - --enable-omx \ --enable-texture-float \ - --with-omx-libdir=${libdir}/bellagio \ + --enable-omx-bellagio \ + --with-omx-bellagio-libdir=${libdir}/bellagio \ " # Package all the libXvMC gallium extensions together @@ -68,8 +60,3 @@ python () { d.setVar("DRIDRIVERS", "swrast,radeon") d.setVar("GALLIUMDRIVERS", "swrast,r300,r600,radeonsi") } - -# We're using components like vdpau which depend -# on nettle so lets just use it as the default for -# crypto as well. -MESA_CRYPTO ?= "nettle" diff --git a/common/recipes-graphics/xorg-driver/xf86-video-amd_git.bb b/common/recipes-graphics/xorg-driver/xf86-video-amd_git.bb index 2a19f2eb..f119c674 100644 --- a/common/recipes-graphics/xorg-driver/xf86-video-amd_git.bb +++ b/common/recipes-graphics/xorg-driver/xf86-video-amd_git.bb @@ -17,13 +17,13 @@ PACKAGECONFIG[udev] = "--enable-udev,--disable-udev,udev" PACKAGECONFIG[glamor] = "--enable-glamor,--disable-glamor" SRC_URI_radeon = "git://anongit.freedesktop.org/git/xorg/driver/xf86-video-ati" -SRCREV_radeon = "99cb8c3faf1a4ce368b7500f17a2a7868c15e8e8" -PV_radeon = "radeon-7.6.1" +SRCREV_radeon = "5cbe1ee8e499e1b6b2646e341946292721d07e69" +PV_radeon = "radeon-7.8.0" PACKAGECONFIG_append_radeon = " udev glamor" -SRC_URI_amdgpu = "git://anongit.freedesktop.org/xorg/driver/xf86-video-amdgpu;branch=1.1" -SRCREV_amdgpu = "b407c1244d28a80f76275abca2239cdd4120f017" -PV_amdgpu = "amdgpu-1.1.0" +SRC_URI_amdgpu = "git://anongit.freedesktop.org/xorg/driver/xf86-video-amdgpu" +SRCREV_amdgpu = "a00032050873fc99f3ceaa3293468dad1d94d4b1" +PV_amdgpu = "amdgpu-1.2.0" PACKAGECONFIG_append_amdgpu = " udev glamor" PV = "git${SRCPV}" diff --git a/common/recipes-kernel/linux/files/0307-drm-radeon-Modify-kgd_engine_type-enum-to-match-CZ.patch b/common/recipes-kernel/linux/files/0307-drm-radeon-Modify-kgd_engine_type-enum-to-match-CZ.patch deleted file mode 100644 index 95cf4372..00000000 --- a/common/recipes-kernel/linux/files/0307-drm-radeon-Modify-kgd_engine_type-enum-to-match-CZ.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 22801f76fa59870aed2c0b8a4eb6c8d6993347ae Mon Sep 17 00:00:00 2001 -From: Oded Gabbay <oded.gabbay@gmail.com> -Date: Mon, 19 Jan 2015 16:20:21 +0200 -Subject: [PATCH 0307/1050] drm/radeon: Modify kgd_engine_type enum to match CZ - -This patch splits the KGD_ENGINE_SDMA to KGD_ENGINE_SDMA1 and -KGD_ENGINE_SDMA2 to match CZ definitions. - -Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> ---- - drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h -index 9080daa..888250b 100644 ---- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h -+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h -@@ -52,7 +52,8 @@ enum kgd_engine_type { - KGD_ENGINE_MEC1, - KGD_ENGINE_MEC2, - KGD_ENGINE_RLC, -- KGD_ENGINE_SDMA, -+ KGD_ENGINE_SDMA1, -+ KGD_ENGINE_SDMA2, - KGD_ENGINE_MAX - }; - --- -1.9.1 - diff --git a/common/recipes-kernel/linux/linux-yocto-rt_4.4.bb b/common/recipes-kernel/linux/linux-yocto-rt_4.4.bb new file mode 100644 index 00000000..5fd13f13 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-rt_4.4.bb @@ -0,0 +1,36 @@ +KBRANCH ?= "standard/preempt-rt/base" + +require recipes-kernel/linux/linux-yocto.inc + +# Skip processing of this recipe if it is not explicitly specified as the +# PREFERRED_PROVIDER for virtual/kernel. This avoids errors when trying +# to build multiple virtual/kernel providers, e.g. as dependency of +# core-image-rt-sdk, core-image-rt. +python () { + if d.getVar("KERNEL_PACKAGE_NAME") == "kernel" and d.getVar("PREFERRED_PROVIDER_virtual/kernel") != "linux-yocto-rt": + raise bb.parse.SkipRecipe("Set PREFERRED_PROVIDER_virtual/kernel to linux-yocto-rt to enable it") +} + +SRCREV_machine ?= "d5efeeeb928a0111fc187fd1e8d03d2e4e35d4a0" +SRCREV_meta ?= "b149d14ccae8349ab33e101f6af233a12f4b17ba" + +SRC_URI = "git://git.yoctoproject.org/linux-yocto-4.4.git;branch=${KBRANCH};name=machine \ + git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-4.4;destsuffix=${KMETA}" + +LINUX_VERSION ?= "4.4.113" + +PV = "${LINUX_VERSION}+git${SRCPV}" + +KMETA = "kernel-meta" +KCONF_BSP_AUDIT_LEVEL = "2" + +LINUX_KERNEL_TYPE = "preempt-rt" + +COMPATIBLE_MACHINE = "(qemux86|qemux86-64|qemuarm|qemuppc|qemumips)" + +# Functionality flags +KERNEL_EXTRA_FEATURES ?= "features/netfilter/netfilter.scc features/taskstats/taskstats.scc" +KERNEL_FEATURES_append = " ${KERNEL_EXTRA_FEATURES}" +KERNEL_FEATURES_append_qemuall=" cfg/virtio.scc" +KERNEL_FEATURES_append_qemux86=" cfg/sound.scc cfg/paravirt_kvm.scc" +KERNEL_FEATURES_append_qemux86-64=" cfg/sound.scc" diff --git a/common/recipes-kernel/linux/linux-yocto_4.4.bb b/common/recipes-kernel/linux/linux-yocto_4.4.bb new file mode 100644 index 00000000..97c16d59 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto_4.4.bb @@ -0,0 +1,42 @@ +KBRANCH ?= "standard/base" + +require recipes-kernel/linux/linux-yocto.inc + +# board specific branches +KBRANCH_qemuarm ?= "standard/arm-versatile-926ejs" +KBRANCH_qemuarm64 ?= "standard/qemuarm64" +KBRANCH_qemumips ?= "standard/mti-malta32" +KBRANCH_qemuppc ?= "standard/qemuppc" +KBRANCH_qemux86 ?= "standard/base" +KBRANCH_qemux86-64 ?= "standard/base" +KBRANCH_qemumips64 ?= "standard/mti-malta64" + +SRCREV_machine_qemuarm ?= "400c0f39b954cd8fffdf53e6ec97852b73fea7af" +SRCREV_machine_qemuarm64 ?= "4d31a8b7661509ff1044abcf9050750cc2478e20" +SRCREV_machine_qemumips ?= "fb03a9472367b6c177729ac631326aafd5d17c92" +SRCREV_machine_qemuppc ?= "4d31a8b7661509ff1044abcf9050750cc2478e20" +SRCREV_machine_qemux86 ?= "4d31a8b7661509ff1044abcf9050750cc2478e20" +SRCREV_machine_qemux86-64 ?= "4d31a8b7661509ff1044abcf9050750cc2478e20" +SRCREV_machine_qemumips64 ?= "26b8ba186a6d39728fc1510bd2264110c75842f5" +SRCREV_machine ?= "4d31a8b7661509ff1044abcf9050750cc2478e20" +SRCREV_meta ?= "b149d14ccae8349ab33e101f6af233a12f4b17ba" + +SRC_URI = "git://git.yoctoproject.org/linux-yocto-4.4.git;name=machine;branch=${KBRANCH}; \ + git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-4.4;destsuffix=${KMETA}" + +LINUX_VERSION ?= "4.4.113" + +PV = "${LINUX_VERSION}+git${SRCPV}" + +KMETA = "kernel-meta" +KCONF_BSP_AUDIT_LEVEL = "2" + +COMPATIBLE_MACHINE = "qemuarm|qemuarm64|qemux86|qemuppc|qemumips|qemumips64|qemux86-64" + +# Functionality flags +KERNEL_EXTRA_FEATURES ?= "features/netfilter/netfilter.scc" +KERNEL_FEATURES_append = " ${KERNEL_EXTRA_FEATURES}" +KERNEL_FEATURES_append_qemuall=" cfg/virtio.scc" +KERNEL_FEATURES_append_qemux86=" cfg/sound.scc cfg/paravirt_kvm.scc" +KERNEL_FEATURES_append_qemux86-64=" cfg/sound.scc cfg/paravirt_kvm.scc" +KERNEL_FEATURES_append = " ${@bb.utils.contains("TUNE_FEATURES", "mx32", " cfg/x32.scc", "" ,d)}" diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-adjust-gstomx.conf-for-mesa.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-adjust-gstomx.conf-for-mesa.patch index 3efa8059..8a413227 100644 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-adjust-gstomx.conf-for-mesa.patch +++ b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-adjust-gstomx.conf-for-mesa.patch @@ -1,31 +1,53 @@ -From 1091020cfd26089583d3f83f21c26bba88d5e8d0 Mon Sep 17 00:00:00 2001 -From: Arindam Nath <arindam.nath@amd.com> -Date: Fri, 17 Apr 2015 18:26:10 +0530 -Subject: [PATCH 1/1] adjust gstomx.conf for mesa-omx +From b9e5a41ec439d9ccbe18aaa6b7437ca2be82498a Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Thu, 6 Apr 2017 15:45:12 +0500 +Subject: [PATCH] adjust gstomx.conf for mesa-omx Signed-off-by: Arindam Nath <arindam.nath@amd.com> +Signed-off-by: Awais Belal <awais_belal@mentor.com> --- - config/bellagio/gstomx.conf | 19 +++++++++++++++++-- - 1 file changed, 17 insertions(+), 2 deletions(-) + config/bellagio/gstomx.conf | 25 ++++++++++++++++++++----- + 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/config/bellagio/gstomx.conf b/config/bellagio/gstomx.conf -index 78f8e7d..bc26507 100644 +index 5ca8ba6..48c243d 100644 --- a/config/bellagio/gstomx.conf +++ b/config/bellagio/gstomx.conf -@@ -10,11 +10,10 @@ hacks=event-port-settings-changed-ndata-parameter-swap;event-port-settings-chang +@@ -1,7 +1,7 @@ + [omxmpeg4videodec] + type-name=GstOMXMPEG4VideoDec + core-name=/usr/local/lib/libomxil-bellagio.so.0 +-component-name=OMX.st.video_decoder.mpeg4 ++component-name=OMX.mesa.video_decoder.mpeg4 + rank=257 + in-port-index=0 + out-port-index=1 +@@ -10,16 +10,15 @@ hacks=event-port-settings-changed-ndata-parameter-swap;event-port-settings-chang [omxh264dec] type-name=GstOMXH264Dec core-name=/usr/local/lib/libomxil-bellagio.so.0 -component-name=OMX.st.video_decoder.avc +component-name=OMX.mesa.video_decoder.avc - rank=256 + rank=257 in-port-index=0 out-port-index=1 -hacks=event-port-settings-changed-ndata-parameter-swap;event-port-settings-changed-port-0-to-1 [omxmpeg4videoenc] type-name=GstOMXMPEG4VideoEnc -@@ -33,3 +32,19 @@ rank=0 + core-name=/usr/local/lib/libomxil-bellagio.so.0 +-component-name=OMX.st.video_encoder.mpeg4 ++component-name=OMX.mesa.video_encoder.mpeg4 + rank=0 + in-port-index=0 + out-port-index=1 +@@ -28,8 +27,24 @@ hacks=event-port-settings-changed-ndata-parameter-swap;video-framerate-integer;s + [omxaacenc] + type-name=GstOMXAACEnc + core-name=/usr/local/lib/libomxil-bellagio.so.0 +-component-name=OMX.st.audio_encoder.aac ++component-name=OMX.mesa.audio_encoder.aac + rank=0 in-port-index=0 out-port-index=1 hacks=event-port-settings-changed-ndata-parameter-swap @@ -46,5 +68,5 @@ index 78f8e7d..bc26507 100644 +in-port-index=0 +out-port-index=1 -- -1.9.1 +2.11.1 diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-gstomxvideodec-fix-multithreads-negotiation-problem-.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-gstomxvideodec-fix-multithreads-negotiation-problem-.patch deleted file mode 100644 index 28078995..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-gstomxvideodec-fix-multithreads-negotiation-problem-.patch +++ /dev/null @@ -1,36 +0,0 @@ -From c223d8863624a93cd969b421b302df5d74f7fbaf Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Thu, 7 Nov 2013 13:13:19 -0500 -Subject: [PATCH 01/11] gstomxvideodec: fix multithreads negotiation problem - v2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -v2: update comment text - -Signed-off-by: Leo Liu <leo.liu@amd.com> -Signed-off-by: Christian König <christian.koenig@amd.com> ---- - omx/gstomxvideodec.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/omx/gstomxvideodec.c b/omx/gstomxvideodec.c -index bf44b3d..0d8801e 100644 ---- a/omx/gstomxvideodec.c -+++ b/omx/gstomxvideodec.c -@@ -2675,6 +2675,11 @@ gst_omx_video_dec_set_format (GstVideoDecoder * decoder, - if (!gst_omx_video_dec_negotiate (self)) - GST_LOG_OBJECT (self, "Negotiation failed, will get output format later"); - -+ /* Make sure other threads are done enabling it */ -+ if (gst_omx_port_wait_enabled (self->dec_out_port, -+ 1 * GST_SECOND) != OMX_ErrorNone) -+ return FALSE; -+ - /* Disable output port */ - if (gst_omx_port_set_enabled (self->dec_out_port, FALSE) != OMX_ErrorNone) - return FALSE; --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-gstomxvideoenc-use-scaling-default-macro-s.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-gstomxvideoenc-use-scaling-default-macro-s.patch deleted file mode 100644 index b5cdb082..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-gstomxvideoenc-use-scaling-default-macro-s.patch +++ /dev/null @@ -1,59 +0,0 @@ -From ca0e2ccb9323129b69036094145afa872799ce53 Mon Sep 17 00:00:00 2001 -From: Arindam Nath <arindam.nath@amd.com> -Date: Fri, 31 Jul 2015 11:51:22 +0530 -Subject: [PATCH 1/4] gstomxvideoenc: use scaling default macro's - -* use #define macros instead of hardcoded value for default -* if omx failed to set the request scaling parameter then use default scaling value - -Signed-off-by: Brijesh Singh <brijeshkumar.singh@amd.com> -Signed-off-by: Arindam Nath <arindam.nath@amd.com> ---- - omx/gstomxvideoenc.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index f42ec13..1a0ecea 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -395,8 +395,8 @@ gst_omx_video_enc_open (GstVideoEncoder * encoder) - } - } - -- if (self->scaling_width != 0xffffffff || -- self->scaling_height != 0xffffffff) { -+ if (self->scaling_width != GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT || -+ self->scaling_height != GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT) { - OMX_CONFIG_SCALEFACTORTYPE scale_factor; - GST_OMX_INIT_STRUCT (&scale_factor); - scale_factor.nPortIndex = self->enc_out_port->index; -@@ -406,9 +406,9 @@ gst_omx_video_enc_open (GstVideoEncoder * encoder) - - if (err == OMX_ErrorNone) { - -- if (self->scaling_width != 0xffffffff) -+ if (self->scaling_width != GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT) - scale_factor.xWidth = self->scaling_width; -- if (self->scaling_height != 0xffffffff) -+ if (self->scaling_height != GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT) - scale_factor.xHeight = self->scaling_height; - - err = -@@ -417,10 +417,14 @@ gst_omx_video_enc_open (GstVideoEncoder * encoder) - if (err == OMX_ErrorUnsupportedIndex) { - GST_WARNING_OBJECT (self, - "Setting scale configuration not supported by the component"); -+ self->scaling_width = GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT; -+ self->scaling_height = GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT; - } else if (err == OMX_ErrorUnsupportedSetting) { - GST_WARNING_OBJECT (self, - "Setting scale configuration %u %u not supported by the component", - self->scaling_width, self->scaling_height); -+ self->scaling_width = GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT; -+ self->scaling_height = GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT; - } else if (err != OMX_ErrorNone) { - GST_ERROR_OBJECT (self, - "Failed to set scale configuration: %s (0x%08x)", --- -1.9.1 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0002-gstomxvideodec-remove-dead-code.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0002-gstomxvideodec-remove-dead-code.patch deleted file mode 100644 index 305e8b20..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0002-gstomxvideodec-remove-dead-code.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 45a91c687ea3a2ce80fcffcdea413b9dcac55242 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> -Date: Thu, 5 Sep 2013 02:05:52 -0600 -Subject: [PATCH 02/11] gstomxvideodec: remove dead code -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This code doesn't seems to be used for quite a while, -remove it before it starts to rot. - -Signed-off-by: Christian König <christian.koenig@amd.com> ---- - omx/gstomxvideodec.c | 48 +----------------------------------------------- - 1 file changed, 1 insertion(+), 47 deletions(-) - -diff --git a/omx/gstomxvideodec.c b/omx/gstomxvideodec.c -index 0d8801e..6b5cbe3 100644 ---- a/omx/gstomxvideodec.c -+++ b/omx/gstomxvideodec.c -@@ -1008,19 +1008,13 @@ gst_omx_video_dec_change_state (GstElement * element, GstStateChange transition) - return ret; - } - --#define MAX_FRAME_DIST_TICKS (5 * OMX_TICKS_PER_SECOND) --#define MAX_FRAME_DIST_FRAMES (100) -- - static GstVideoCodecFrame * - _find_nearest_frame (GstOMXVideoDec * self, GstOMXBuffer * buf) - { -- GList *l, *best_l = NULL; -- GList *finish_frames = NULL; - GstVideoCodecFrame *best = NULL; -- guint64 best_timestamp = 0; - guint64 best_diff = G_MAXUINT64; -- BufferIdentification *best_id = NULL; - GList *frames; -+ GList *l; - - frames = gst_video_decoder_get_frames (GST_VIDEO_DECODER (self)); - -@@ -1045,10 +1039,7 @@ _find_nearest_frame (GstOMXVideoDec * self, GstOMXBuffer * buf) - - if (best == NULL || diff < best_diff) { - best = tmp; -- best_timestamp = timestamp; - best_diff = diff; -- best_l = l; -- best_id = id; - - /* For frames without timestamp we simply take the first frame */ - if ((buf->omx_buf->nTimeStamp == 0 && timestamp == 0) || diff == 0) -@@ -1056,43 +1047,6 @@ _find_nearest_frame (GstOMXVideoDec * self, GstOMXBuffer * buf) - } - } - -- if (FALSE && best_id) { -- for (l = frames; l && l != best_l; l = l->next) { -- GstVideoCodecFrame *tmp = l->data; -- BufferIdentification *id = gst_video_codec_frame_get_user_data (tmp); -- guint64 diff_ticks, diff_frames; -- -- /* This happens for frames that were just added but -- * which were not passed to the component yet. Ignore -- * them here! -- */ -- if (!id) -- continue; -- -- if (id->timestamp > best_timestamp) -- break; -- -- if (id->timestamp == 0 || best_timestamp == 0) -- diff_ticks = 0; -- else -- diff_ticks = best_timestamp - id->timestamp; -- diff_frames = best->system_frame_number - tmp->system_frame_number; -- -- if (diff_ticks > MAX_FRAME_DIST_TICKS -- || diff_frames > MAX_FRAME_DIST_FRAMES) { -- finish_frames = -- g_list_prepend (finish_frames, gst_video_codec_frame_ref (tmp)); -- } -- } -- } -- -- if (FALSE && finish_frames) { -- g_warning ("Too old frames, bug in decoder -- please file a bug"); -- for (l = finish_frames; l; l = l->next) { -- gst_video_decoder_drop_frame (GST_VIDEO_DECODER (self), l->data); -- } -- } -- - if (best) - gst_video_codec_frame_ref (best); - --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0002-gstomxvideoenc-fix-srcpad-caps-when-scaling-property.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0002-gstomxvideoenc-fix-srcpad-caps-when-scaling-property.patch deleted file mode 100644 index f1952e8d..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0002-gstomxvideoenc-fix-srcpad-caps-when-scaling-property.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 647b180a8805f9f8b5fdd35c1bbc0a8e03d3e91f Mon Sep 17 00:00:00 2001 -From: Arindam Nath <arindam.nath@amd.com> -Date: Fri, 31 Jul 2015 12:36:36 +0530 -Subject: [PATCH 2/4] gstomxvideoenc: fix srcpad caps when scaling property is - specified - -if scaling parameter is specified then use the scaling width and height to configure the encoder state. - -Signed-off-by: Brijesh Singh <brijeshkumar.singh@amd.com> -Signed-off-by: Arindam Nath <arindam.nath@amd.com> ---- - omx/gstomxvideoenc.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index 1a0ecea..c372a0d 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -805,6 +805,14 @@ gst_omx_video_enc_handle_output_frame (GstOMXVideoEnc * self, GstOMXPort * port, - gst_video_encoder_set_output_state (GST_VIDEO_ENCODER (self), caps, - self->input_state); - state->codec_data = codec_data; -+ if (GST_OMX_VIDEO_ENC(self)->scaling_width != -+ GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT || -+ GST_OMX_VIDEO_ENC(self)->scaling_height != -+ GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT) { -+ state->info.width = self->scaling_width; -+ state->info.height = self->scaling_height; -+ } -+ - if (!gst_video_encoder_negotiate (GST_VIDEO_ENCODER (self))) { - gst_video_codec_frame_unref (frame); - return GST_FLOW_NOT_NEGOTIATED; -@@ -928,6 +936,11 @@ gst_omx_video_enc_loop (GstOMXVideoEnc * self) - state = - gst_video_encoder_set_output_state (GST_VIDEO_ENCODER (self), caps, - self->input_state); -+ if (self->scaling_width != GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT || -+ self->scaling_height != GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT) { -+ state->info.width = self->scaling_width; -+ state->info.height = self->scaling_height; -+ } - gst_video_codec_state_unref (state); - - if (!gst_video_encoder_negotiate (GST_VIDEO_ENCODER (self))) { --- -1.9.1 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0003-gstomxvideodec-simplify-_find_nearest_frame.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0003-gstomxvideodec-simplify-_find_nearest_frame.patch deleted file mode 100644 index f2c9a912..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0003-gstomxvideodec-simplify-_find_nearest_frame.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 75402afb7acd7bee4fe02ca2c2e524d3d7426d19 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> -Date: Thu, 5 Sep 2013 02:23:39 -0600 -Subject: [PATCH 03/11] gstomxvideodec: simplify _find_nearest_frame -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -No need to make it more complicated and error prone than -necessary. Also give the function a gst_omx_video_dec prefix -to distinct it from the encoder function. - -Signed-off-by: Christian König <christian.koenig@amd.com> ---- - omx/gstomxvideodec.c | 60 ++++++++++++++------------------------------------ - 1 file changed, 16 insertions(+), 44 deletions(-) - -diff --git a/omx/gstomxvideodec.c b/omx/gstomxvideodec.c -index 6b5cbe3..020b7d3 100644 ---- a/omx/gstomxvideodec.c -+++ b/omx/gstomxvideodec.c -@@ -646,18 +646,6 @@ gst_omx_buffer_pool_new (GstElement * element, GstOMXComponent * component, - return GST_BUFFER_POOL (pool); - } - --typedef struct _BufferIdentification BufferIdentification; --struct _BufferIdentification --{ -- guint64 timestamp; --}; -- --static void --buffer_identification_free (BufferIdentification * id) --{ -- g_slice_free (BufferIdentification, id); --} -- - /* prototypes */ - static void gst_omx_video_dec_finalize (GObject * object); - -@@ -1009,40 +997,32 @@ gst_omx_video_dec_change_state (GstElement * element, GstStateChange transition) - } - - static GstVideoCodecFrame * --_find_nearest_frame (GstOMXVideoDec * self, GstOMXBuffer * buf) -+gst_omx_video_dec_find_nearest_frame (GstOMXVideoDec * self, GstOMXBuffer * buf) - { - GstVideoCodecFrame *best = NULL; -- guint64 best_diff = G_MAXUINT64; -+ GstClockTimeDiff best_diff = G_MAXINT64; -+ GstClockTime timestamp; - GList *frames; - GList *l; - -+ if (buf->omx_buf->nTimeStamp) -+ timestamp = -+ gst_util_uint64_scale (buf->omx_buf->nTimeStamp, GST_SECOND, -+ OMX_TICKS_PER_SECOND); -+ else -+ timestamp = GST_CLOCK_TIME_NONE; -+ - frames = gst_video_decoder_get_frames (GST_VIDEO_DECODER (self)); - - for (l = frames; l; l = l->next) { - GstVideoCodecFrame *tmp = l->data; -- BufferIdentification *id = gst_video_codec_frame_get_user_data (tmp); -- guint64 timestamp, diff; -+ GstClockTimeDiff diff = ABS (GST_CLOCK_DIFF (timestamp, tmp->pts)); - -- /* This happens for frames that were just added but -- * which were not passed to the component yet. Ignore -- * them here! -- */ -- if (!id) -- continue; -- -- timestamp = id->timestamp; -- -- if (timestamp > buf->omx_buf->nTimeStamp) -- diff = timestamp - buf->omx_buf->nTimeStamp; -- else -- diff = buf->omx_buf->nTimeStamp - timestamp; -- -- if (best == NULL || diff < best_diff) { -+ if (diff < best_diff) { - best = tmp; - best_diff = diff; - -- /* For frames without timestamp we simply take the first frame */ -- if ((buf->omx_buf->nTimeStamp == 0 && timestamp == 0) || diff == 0) -+ if (diff == 0) - break; - } - } -@@ -1947,7 +1927,7 @@ gst_omx_video_dec_loop (GstOMXVideoDec * self) - (guint) buf->omx_buf->nFlags, (guint64) buf->omx_buf->nTimeStamp); - - GST_VIDEO_DECODER_STREAM_LOCK (self); -- frame = _find_nearest_frame (self, buf); -+ frame = gst_omx_video_dec_find_nearest_frame (self, buf); - - if (frame - && (deadline = gst_video_decoder_get_max_decode_time -@@ -2926,16 +2906,8 @@ gst_omx_video_dec_handle_frame (GstVideoDecoder * decoder, - buf->omx_buf->nTickCount = 0; - } - -- if (offset == 0) { -- BufferIdentification *id = g_slice_new0 (BufferIdentification); -- -- if (GST_VIDEO_CODEC_FRAME_IS_SYNC_POINT (frame)) -- buf->omx_buf->nFlags |= OMX_BUFFERFLAG_SYNCFRAME; -- -- id->timestamp = buf->omx_buf->nTimeStamp; -- gst_video_codec_frame_set_user_data (frame, id, -- (GDestroyNotify) buffer_identification_free); -- } -+ if (offset == 0 && GST_VIDEO_CODEC_FRAME_IS_SYNC_POINT (frame)) -+ buf->omx_buf->nFlags |= OMX_BUFFERFLAG_SYNCFRAME; - - /* TODO: Set flags - * - OMX_BUFFERFLAG_DECODEONLY for buffers that are outside --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0003-gstomxvideoenc-add-fix-timestamp-property.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0003-gstomxvideoenc-add-fix-timestamp-property.patch deleted file mode 100644 index a7e9bdd1..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0003-gstomxvideoenc-add-fix-timestamp-property.patch +++ /dev/null @@ -1,111 +0,0 @@ -From e40121374266c6e72901ce77c09673fb28f78380 Mon Sep 17 00:00:00 2001 -From: Arindam Nath <arindam.nath@amd.com> -Date: Fri, 31 Jul 2015 12:48:45 +0530 -Subject: [PATCH 3/4] gstomxvideoenc: add fix-timestamp property - -The property will force element to calculate the timestamp (dts and pts) based on duration. - -Signed-off-by: Brijesh Singh <brijeshkumar.singh@amd.com> -Signed-off-by: Arindam Nath <arindam.nath@amd.com> ---- - omx/gstomxvideoenc.c | 20 +++++++++++++++++++- - omx/gstomxvideoenc.h | 3 +++ - 2 files changed, 22 insertions(+), 1 deletion(-) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index c372a0d..bba349a 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -101,7 +101,8 @@ enum - PROP_SCALING_HEIGHT, - PROP_CAPTURE, - PROP_POS_X, -- PROP_POS_Y -+ PROP_POS_Y, -+ PROP_FIX_TIMESTAMP - }; - - /* FIXME: Better defaults */ -@@ -115,6 +116,7 @@ enum - #define GST_OMX_VIDEO_ENC_CAPTURE_DEFAULT (FALSE) - #define GST_OMX_VIDEO_ENC_POS_X_DEFAULT (0) - #define GST_OMX_VIDEO_ENC_POS_Y_DEFAULT (0) -+#define GST_OMX_VIDEO_ENC_FIX_TIMESTAMP_DEFAULT FALSE - - /* class initialization */ - -@@ -207,6 +209,11 @@ gst_omx_video_enc_class_init (GstOMXVideoEncClass * klass) - G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | - GST_PARAM_MUTABLE_READY)); - -+ g_object_class_install_property (gobject_class, PROP_FIX_TIMESTAMP, -+ g_param_spec_boolean ("fix-timestamp", "Calculate timestamp", -+ "Calculate timestamp (dts/pts) based on duration", -+ 0, G_PARAM_READWRITE)); -+ - element_class->change_state = - GST_DEBUG_FUNCPTR (gst_omx_video_enc_change_state); - -@@ -246,6 +253,8 @@ gst_omx_video_enc_init (GstOMXVideoEnc * self) - self->capture = GST_OMX_VIDEO_ENC_CAPTURE_DEFAULT; - self->pos_x = GST_OMX_VIDEO_ENC_POS_X_DEFAULT; - self->pos_y = GST_OMX_VIDEO_ENC_POS_Y_DEFAULT; -+ self->prev_timestamp = 0; -+ self->fix_timestamp = GST_OMX_VIDEO_ENC_FIX_TIMESTAMP_DEFAULT; - - g_mutex_init (&self->drain_lock); - g_cond_init (&self->drain_cond); -@@ -623,6 +632,9 @@ gst_omx_video_enc_set_property (GObject * object, guint prop_id, - case PROP_POS_Y: - self->pos_y = g_value_get_uint (value); - break; -+ case PROP_FIX_TIMESTAMP: -+ self->fix_timestamp = g_value_get_boolean (value); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -@@ -666,6 +678,9 @@ gst_omx_video_enc_get_property (GObject * object, guint prop_id, GValue * value, - case PROP_POS_Y: - g_value_set_uint (value, self->pos_y); - break; -+ case PROP_FIX_TIMESTAMP: -+ g_value_set_boolean (value, self->fix_timestamp); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -@@ -998,6 +1013,9 @@ gst_omx_video_enc_loop (GstOMXVideoEnc * self) - GST_VIDEO_ENCODER_STREAM_LOCK (self); - frame = gst_omx_video_enc_find_nearest_frame (self, buf); - -+ GST_INFO_OBJECT (self, "dts %" GST_TIME_FORMAT " pts %" GST_TIME_FORMAT, -+ GST_TIME_ARGS(frame->dts), GST_TIME_ARGS(frame->pts)); -+ - g_assert (klass->handle_output_frame); - flow_ret = klass->handle_output_frame (self, self->enc_out_port, buf, frame); - -diff --git a/omx/gstomxvideoenc.h b/omx/gstomxvideoenc.h -index 3de563b..064583f 100644 ---- a/omx/gstomxvideoenc.h -+++ b/omx/gstomxvideoenc.h -@@ -60,6 +60,7 @@ struct _GstOMXVideoEnc - gboolean started; - - GstClockTime last_upstream_ts; -+ GstClockTime prev_timestamp; - - /* Draining state */ - GMutex drain_lock; -@@ -77,6 +78,8 @@ struct _GstOMXVideoEnc - guint32 quant_p_frames; - guint32 quant_b_frames; - -+ gboolean fix_timestamp; -+ - guint32 scaling_width; - guint32 scaling_height; - --- -1.9.1 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0004-gstomxvideoenc-add-force-keyframe-period-property.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0004-gstomxvideoenc-add-force-keyframe-period-property.patch deleted file mode 100644 index 5d0d606d..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0004-gstomxvideoenc-add-force-keyframe-period-property.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 8a24b4c8cbfc49deceb5595b76c5d9fc8dc5e602 Mon Sep 17 00:00:00 2001 -From: Arindam Nath <arindam.nath@amd.com> -Date: Fri, 31 Jul 2015 13:05:36 +0530 -Subject: [PATCH 4/4] gstomxvideoenc: add force-keyframe-period property - -Add property to allow overriding the default keyframe period. - -Signed-off-by: Brijesh Singh <brijeshkumar.singh@amd.com> -Signed-off-by: Arindam Nath <arindam.nath@amd.com> ---- - omx/gstomxvideoenc.c | 56 +++++++++++++++++++++++++++++++++++++++------------- - omx/gstomxvideoenc.h | 3 +++ - 2 files changed, 45 insertions(+), 14 deletions(-) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index bba349a..e7c7db5 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -102,7 +102,8 @@ enum - PROP_CAPTURE, - PROP_POS_X, - PROP_POS_Y, -- PROP_FIX_TIMESTAMP -+ PROP_FIX_TIMESTAMP, -+ PROP_FORCE_KEYFRAME_PERIOD - }; - - /* FIXME: Better defaults */ -@@ -117,6 +118,7 @@ enum - #define GST_OMX_VIDEO_ENC_POS_X_DEFAULT (0) - #define GST_OMX_VIDEO_ENC_POS_Y_DEFAULT (0) - #define GST_OMX_VIDEO_ENC_FIX_TIMESTAMP_DEFAULT FALSE -+#define GST_OMX_VIDEO_ENC_FORCE_KEYFRAME_PERIOD (0xffffffff) - - /* class initialization */ - -@@ -209,6 +211,13 @@ gst_omx_video_enc_class_init (GstOMXVideoEncClass * klass) - G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | - GST_PARAM_MUTABLE_READY)); - -+ g_object_class_install_property (gobject_class, PROP_FORCE_KEYFRAME_PERIOD, -+ g_param_spec_uint ("force-keyframe-period", "Force key frame", -+ "Generate keyframe after a specified number of frames (0xffffffff=component default)", -+ 0, G_MAXUINT, GST_OMX_VIDEO_ENC_FORCE_KEYFRAME_PERIOD, -+ G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | -+ GST_PARAM_MUTABLE_READY)); -+ - g_object_class_install_property (gobject_class, PROP_FIX_TIMESTAMP, - g_param_spec_boolean ("fix-timestamp", "Calculate timestamp", - "Calculate timestamp (dts/pts) based on duration", -@@ -255,6 +264,7 @@ gst_omx_video_enc_init (GstOMXVideoEnc * self) - self->pos_y = GST_OMX_VIDEO_ENC_POS_Y_DEFAULT; - self->prev_timestamp = 0; - self->fix_timestamp = GST_OMX_VIDEO_ENC_FIX_TIMESTAMP_DEFAULT; -+ self->force_keyframe_period = GST_OMX_VIDEO_ENC_FORCE_KEYFRAME_PERIOD; - - g_mutex_init (&self->drain_lock); - g_cond_init (&self->drain_cond); -@@ -635,6 +645,9 @@ gst_omx_video_enc_set_property (GObject * object, guint prop_id, - case PROP_FIX_TIMESTAMP: - self->fix_timestamp = g_value_get_boolean (value); - break; -+ case PROP_FORCE_KEYFRAME_PERIOD: -+ self->force_keyframe_period = g_value_get_uint (value); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -@@ -681,6 +694,9 @@ gst_omx_video_enc_get_property (GObject * object, guint prop_id, GValue * value, - case PROP_FIX_TIMESTAMP: - g_value_set_boolean (value, self->fix_timestamp); - break; -+ case PROP_FORCE_KEYFRAME_PERIOD: -+ g_value_set_uint (value, self->force_keyframe_period); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -@@ -1708,6 +1724,25 @@ done: - return ret; - } - -+static void -+gst_omx_video_enc_force_keyframe (GstOMXVideoEnc * self, GstOMXPort * port) -+{ -+ OMX_ERRORTYPE err; -+ OMX_CONFIG_INTRAREFRESHVOPTYPE config; -+ -+ GST_OMX_INIT_STRUCT (&config); -+ config.nPortIndex = port->index; -+ config.IntraRefreshVOP = OMX_TRUE; -+ -+ GST_DEBUG_OBJECT (self, "Forcing a keyframe"); -+ err = -+ gst_omx_component_set_config (self->enc, -+ OMX_IndexConfigVideoIntraVOPRefresh, &config); -+ if (err != OMX_ErrorNone) -+ GST_ERROR_OBJECT (self, "Failed to force a keyframe: %s (0x%08x)", -+ gst_omx_error_to_string (err), err); -+} -+ - static GstFlowReturn - gst_omx_video_enc_handle_frame (GstVideoEncoder * encoder, - GstVideoCodecFrame * frame) -@@ -1735,6 +1770,11 @@ gst_omx_video_enc_handle_frame (GstVideoEncoder * encoder, - - port = self->enc_in_port; - -+ /* do we need to force key frame ? */ -+ if ((self->force_keyframe_period != 0xffffffff) && -+ (self->input_frame_count++ % self->force_keyframe_period == 0)) -+ gst_omx_video_enc_force_keyframe (self, port); -+ - if (port->tunneled) { - gst_video_codec_frame_unref (frame); - return self->downstream_flow_ret; -@@ -1827,19 +1867,7 @@ gst_omx_video_enc_handle_frame (GstVideoEncoder * encoder, - GST_DEBUG_OBJECT (self, "Handling frame"); - - if (GST_VIDEO_CODEC_FRAME_IS_FORCE_KEYFRAME (frame)) { -- OMX_CONFIG_INTRAREFRESHVOPTYPE config; -- -- GST_OMX_INIT_STRUCT (&config); -- config.nPortIndex = port->index; -- config.IntraRefreshVOP = OMX_TRUE; -- -- GST_DEBUG_OBJECT (self, "Forcing a keyframe"); -- err = -- gst_omx_component_set_config (self->enc, -- OMX_IndexConfigVideoIntraVOPRefresh, &config); -- if (err != OMX_ErrorNone) -- GST_ERROR_OBJECT (self, "Failed to force a keyframe: %s (0x%08x)", -- gst_omx_error_to_string (err), err); -+ gst_omx_video_enc_force_keyframe (self, port); - } - - /* Copy the buffer content in chunks of size as requested -diff --git a/omx/gstomxvideoenc.h b/omx/gstomxvideoenc.h -index 064583f..bb8bff7 100644 ---- a/omx/gstomxvideoenc.h -+++ b/omx/gstomxvideoenc.h -@@ -87,6 +87,9 @@ struct _GstOMXVideoEnc - guint32 pos_x; - guint32 pos_y; - -+ guint32 force_keyframe_period; -+ guint64 input_frame_count; -+ - GstFlowReturn downstream_flow_ret; - }; - --- -1.9.1 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0004-gstomxvideoenc-simplify-_find_nearest_frame.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0004-gstomxvideoenc-simplify-_find_nearest_frame.patch deleted file mode 100644 index b12bac17..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0004-gstomxvideoenc-simplify-_find_nearest_frame.patch +++ /dev/null @@ -1,175 +0,0 @@ -From 91123307c8f934a867cf70b9ae6b27373311b8fc Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> -Date: Thu, 5 Sep 2013 03:41:10 -0600 -Subject: [PATCH 04/11] gstomxvideoenc: simplify _find_nearest_frame -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Just the same as we did with the decoder. Also give the -function a gst_omx_video_enc prefix to distinct it from -the decoder function. - -Signed-off-by: Christian König <christian.koenig@amd.com> ---- - omx/gstomxvideoenc.c | 102 ++++++++------------------------------------------ - 1 file changed, 15 insertions(+), 87 deletions(-) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index a85e815..3a139bb 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -55,18 +55,6 @@ gst_omx_video_enc_control_rate_get_type (void) - return qtype; - } - --typedef struct _BufferIdentification BufferIdentification; --struct _BufferIdentification --{ -- guint64 timestamp; --}; -- --static void --buffer_identification_free (BufferIdentification * id) --{ -- g_slice_free (BufferIdentification, id); --} -- - /* prototypes */ - static void gst_omx_video_enc_finalize (GObject * object); - static void gst_omx_video_enc_set_property (GObject * object, guint prop_id, -@@ -551,88 +539,34 @@ gst_omx_video_enc_change_state (GstElement * element, GstStateChange transition) - return ret; - } - --#define MAX_FRAME_DIST_TICKS (5 * OMX_TICKS_PER_SECOND) --#define MAX_FRAME_DIST_FRAMES (100) -- - static GstVideoCodecFrame * --_find_nearest_frame (GstOMXVideoEnc * self, GstOMXBuffer * buf) -+gst_omx_video_enc_find_nearest_frame (GstOMXVideoEnc * self, GstOMXBuffer * buf) - { -- GList *l, *best_l = NULL; -- GList *finish_frames = NULL; - GstVideoCodecFrame *best = NULL; -- guint64 best_timestamp = 0; -- guint64 best_diff = G_MAXUINT64; -- BufferIdentification *best_id = NULL; -+ GstClockTimeDiff best_diff = G_MAXINT64; -+ GstClockTime timestamp; - GList *frames; -+ GList *l; -+ -+ if (buf->omx_buf->nTimeStamp) -+ timestamp = -+ gst_util_uint64_scale (buf->omx_buf->nTimeStamp, GST_SECOND, -+ OMX_TICKS_PER_SECOND); -+ else -+ timestamp = GST_CLOCK_TIME_NONE; - - frames = gst_video_encoder_get_frames (GST_VIDEO_ENCODER (self)); - - for (l = frames; l; l = l->next) { - GstVideoCodecFrame *tmp = l->data; -- BufferIdentification *id = gst_video_codec_frame_get_user_data (tmp); -- guint64 timestamp, diff; -- -- /* This happens for frames that were just added but -- * which were not passed to the component yet. Ignore -- * them here! -- */ -- if (!id) -- continue; -- -- timestamp = id->timestamp; -+ GstClockTimeDiff diff = ABS (GST_CLOCK_DIFF (timestamp, tmp->pts)); - -- if (timestamp > buf->omx_buf->nTimeStamp) -- diff = timestamp - buf->omx_buf->nTimeStamp; -- else -- diff = buf->omx_buf->nTimeStamp - timestamp; -- -- if (best == NULL || diff < best_diff) { -+ if (diff < best_diff) { - best = tmp; -- best_timestamp = timestamp; - best_diff = diff; -- best_l = l; -- best_id = id; -- -- /* For frames without timestamp we simply take the first frame */ -- if ((buf->omx_buf->nTimeStamp == 0 && timestamp == 0) || diff == 0) -- break; -- } -- } -- -- if (best_id) { -- for (l = frames; l && l != best_l; l = l->next) { -- GstVideoCodecFrame *tmp = l->data; -- BufferIdentification *id = gst_video_codec_frame_get_user_data (tmp); -- guint64 diff_ticks, diff_frames; -- -- /* This happens for frames that were just added but -- * which were not passed to the component yet. Ignore -- * them here! -- */ -- if (!id) -- continue; - -- if (id->timestamp > best_timestamp) -+ if (diff == 0) - break; -- -- if (id->timestamp == 0 || best_timestamp == 0) -- diff_ticks = 0; -- else -- diff_ticks = best_timestamp - id->timestamp; -- diff_frames = best->system_frame_number - tmp->system_frame_number; -- -- if (diff_ticks > MAX_FRAME_DIST_TICKS -- || diff_frames > MAX_FRAME_DIST_FRAMES) { -- finish_frames = -- g_list_prepend (finish_frames, gst_video_codec_frame_ref (tmp)); -- } -- } -- } -- -- if (finish_frames) { -- g_warning ("Too old frames, bug in encoder -- please file a bug"); -- for (l = finish_frames; l; l = l->next) { -- gst_video_encoder_finish_frame (GST_VIDEO_ENCODER (self), l->data); - } - } - -@@ -851,7 +785,7 @@ gst_omx_video_enc_loop (GstOMXVideoEnc * self) - (guint) buf->omx_buf->nFlags, (guint64) buf->omx_buf->nTimeStamp); - - GST_VIDEO_ENCODER_STREAM_LOCK (self); -- frame = _find_nearest_frame (self, buf); -+ frame = gst_omx_video_enc_find_nearest_frame (self, buf); - - g_assert (klass->handle_output_frame); - flow_ret = klass->handle_output_frame (self, self->enc_out_port, buf, frame); -@@ -1559,7 +1493,6 @@ gst_omx_video_enc_handle_frame (GstVideoEncoder * encoder, - port = self->enc_in_port; - - while (acq_ret != GST_OMX_ACQUIRE_BUFFER_OK) { -- BufferIdentification *id; - GstClockTime timestamp, duration; - - /* Make sure to release the base class stream lock, otherwise -@@ -1683,11 +1616,6 @@ gst_omx_video_enc_handle_frame (GstVideoEncoder * encoder, - self->last_upstream_ts += duration; - } - -- id = g_slice_new0 (BufferIdentification); -- id->timestamp = buf->omx_buf->nTimeStamp; -- gst_video_codec_frame_set_user_data (frame, id, -- (GDestroyNotify) buffer_identification_free); -- - self->started = TRUE; - err = gst_omx_port_release_buffer (port, buf); - if (err != OMX_ErrorNone) --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0005-gstomxvideoenc-Add-new-property-to-set-framerate.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0005-gstomxvideoenc-Add-new-property-to-set-framerate.patch deleted file mode 100644 index cc93f02c..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0005-gstomxvideoenc-Add-new-property-to-set-framerate.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 9ea8f85d9b9fac5de07256bd7a5f2e3f73291f3f Mon Sep 17 00:00:00 2001 -From: Nishanth Peethambaran <nishanth.peethambaran@amd.com> -Date: Tue, 22 Mar 2016 18:58:42 -0400 -Subject: [PATCH 2/3] gstomxvideoenc: Add new property to set framerate - -Signed-off-by: Nishanth Peethambaran <nishanth.peethambaran@amd.com> ---- - omx/gstomxvideoenc.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++- - omx/gstomxvideoenc.h | 4 +++ - 2 files changed, 92 insertions(+), 1 deletion(-) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index a1bc9fb..54c8f2c 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -103,7 +103,9 @@ enum - PROP_POS_X, - PROP_POS_Y, - PROP_FIX_TIMESTAMP, -- PROP_FORCE_KEYFRAME_PERIOD -+ PROP_FORCE_KEYFRAME_PERIOD, -+ PROP_FRAMERATE_NUM, -+ PROP_FRAMERATE_DEN - }; - - /* FIXME: Better defaults */ -@@ -119,6 +121,7 @@ enum - #define GST_OMX_VIDEO_ENC_POS_Y_DEFAULT (0) - #define GST_OMX_VIDEO_ENC_FIX_TIMESTAMP_DEFAULT FALSE - #define GST_OMX_VIDEO_ENC_FORCE_KEYFRAME_PERIOD (0xffffffff) -+#define GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT (0) - - /* class initialization */ - -@@ -223,6 +226,20 @@ gst_omx_video_enc_class_init (GstOMXVideoEncClass * klass) - "Calculate timestamp (dts/pts) based on duration", - 0, G_PARAM_READWRITE)); - -+ g_object_class_install_property (gobject_class, PROP_FRAMERATE_NUM, -+ g_param_spec_uint ("framerate-num", "Framerate Numerator", -+ "Numerator for output framerate", -+ 0, G_MAXUINT, GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT, -+ G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | -+ GST_PARAM_MUTABLE_READY)); -+ -+ g_object_class_install_property (gobject_class, PROP_FRAMERATE_DEN, -+ g_param_spec_uint ("framerate-den", "Framerate Denominator", -+ "Denominator for output framerate", -+ 0, G_MAXUINT, GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT, -+ G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | -+ GST_PARAM_MUTABLE_READY)); -+ - element_class->change_state = - GST_DEBUG_FUNCPTR (gst_omx_video_enc_change_state); - -@@ -265,6 +282,9 @@ gst_omx_video_enc_init (GstOMXVideoEnc * self) - self->prev_timestamp = 0; - self->fix_timestamp = GST_OMX_VIDEO_ENC_FIX_TIMESTAMP_DEFAULT; - self->force_keyframe_period = GST_OMX_VIDEO_ENC_FORCE_KEYFRAME_PERIOD; -+ self->framerate_num = GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT; -+ self->framerate_den = GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT; -+ self->xEncodeFramerate = 0; - - g_mutex_init (&self->drain_lock); - g_cond_init (&self->drain_cond); -@@ -525,6 +545,49 @@ gst_omx_video_enc_open (GstVideoEncoder * encoder) - gst_omx_error_to_string (err), err); - } - } -+ -+ if (self->framerate_num != GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT && -+ self->framerate_den != GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT) { -+ -+ OMX_CONFIG_FRAMERATETYPE framerate_config; -+ -+ GST_OMX_INIT_STRUCT (&framerate_config); -+ framerate_config.nPortIndex = self->enc_out_port->index; -+ -+ err = gst_omx_component_get_config (self->enc, -+ OMX_IndexConfigVideoFramerate, &framerate_config); -+ -+ if (err == OMX_ErrorNone) { -+ -+ framerate_config.xEncodeFramerate = -+ (self->framerate_num << 16) / (self->framerate_den); -+ err = -+ gst_omx_component_set_config (self->enc, -+ OMX_IndexConfigVideoFramerate, &framerate_config); -+ if (err == OMX_ErrorUnsupportedIndex) { -+ GST_WARNING_OBJECT (self, -+ "Setting parameter not supported by the component"); -+ self->framerate_num = GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT; -+ self->framerate_den = GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT; -+ } else if (err == OMX_ErrorUnsupportedSetting) { -+ GST_WARNING_OBJECT (self, -+ "Setting framerate %u %u not supported by the component", -+ self->framerate_num, self->framerate_den); -+ self->framerate_num = GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT; -+ self->framerate_den = GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT; -+ } else if (err != OMX_ErrorNone) { -+ GST_ERROR_OBJECT (self, -+ "Failed to set encoder framerate config: %s (0x%08x)", -+ gst_omx_error_to_string (err), err); -+ return FALSE; -+ } else { -+ self->xEncodeFramerate = framerate_config.xEncodeFramerate; -+ } -+ } else { -+ GST_ERROR_OBJECT (self, "Failed to get framerate config: %s (0x%08x)", -+ gst_omx_error_to_string (err), err); -+ } -+ } - } - - return TRUE; -@@ -647,6 +710,12 @@ gst_omx_video_enc_set_property (GObject * object, guint prop_id, - case PROP_FORCE_KEYFRAME_PERIOD: - self->force_keyframe_period = g_value_get_uint (value); - break; -+ case PROP_FRAMERATE_NUM: -+ self->framerate_num = g_value_get_uint (value); -+ break; -+ case PROP_FRAMERATE_DEN: -+ self->framerate_den = g_value_get_uint (value); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -@@ -696,6 +765,12 @@ gst_omx_video_enc_get_property (GObject * object, guint prop_id, GValue * value, - case PROP_FORCE_KEYFRAME_PERIOD: - g_value_set_uint (value, self->force_keyframe_period); - break; -+ case PROP_FRAMERATE_NUM: -+ self->framerate_num = g_value_get_uint (value); -+ break; -+ case PROP_FRAMERATE_DEN: -+ self->framerate_den = g_value_get_uint (value); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -@@ -848,6 +923,13 @@ gst_omx_video_enc_handle_output_frame (GstOMXVideoEnc * self, GstOMXPort * port, - state->info.width = self->scaling_width; - state->info.height = self->scaling_height; - } -+ if (GST_OMX_VIDEO_ENC (self)->framerate_num != -+ GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT && -+ GST_OMX_VIDEO_ENC (self)->framerate_den != -+ GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT) { -+ state->info.fps_n = self->framerate_num; -+ state->info.fps_d = self->framerate_den; -+ } - - if (!gst_video_encoder_negotiate (GST_VIDEO_ENCODER (self))) { - gst_video_codec_frame_unref (frame); -@@ -978,6 +1060,11 @@ gst_omx_video_enc_loop (GstOMXVideoEnc * self) - state->info.width = self->scaling_width; - state->info.height = self->scaling_height; - } -+ if (self->framerate_num != GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT && -+ self->framerate_den != GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT) { -+ state->info.fps_n = self->framerate_num; -+ state->info.fps_d = self->framerate_den; -+ } - gst_video_codec_state_unref (state); - - if (!gst_video_encoder_negotiate (GST_VIDEO_ENCODER (self))) { -diff --git a/omx/gstomxvideoenc.h b/omx/gstomxvideoenc.h -index d348643..f09a23b 100644 ---- a/omx/gstomxvideoenc.h -+++ b/omx/gstomxvideoenc.h -@@ -92,6 +92,10 @@ struct _GstOMXVideoEnc - gboolean is_keyframe; - - GstFlowReturn downstream_flow_ret; -+ -+ guint32 framerate_num; -+ guint32 framerate_den; -+ OMX_U32 xEncodeFramerate; /* Q16 format */ - }; - - struct _GstOMXVideoEncClass --- -2.1.4 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0005-omx-improve-tunneling-support.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0005-omx-improve-tunneling-support.patch deleted file mode 100644 index 686e0693..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0005-omx-improve-tunneling-support.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 1975efe159dc52a8030602736c5319785fb62329 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> -Date: Thu, 5 Sep 2013 04:15:26 -0600 -Subject: [PATCH 05/11] omx: improve tunneling support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Keep track where the tunnel leads us instead of just if it's tunneled or not. - -Signed-off-by: Christian König <christian.koenig@amd.com> ---- - omx/gstomx.c | 13 +++++++------ - omx/gstomx.h | 2 +- - 2 files changed, 8 insertions(+), 7 deletions(-) - -diff --git a/omx/gstomx.c b/omx/gstomx.c -index 4e94712..c8a8927 100644 ---- a/omx/gstomx.c -+++ b/omx/gstomx.c -@@ -920,7 +920,7 @@ gst_omx_component_add_port (GstOMXComponent * comp, guint32 index) - port->comp = comp; - port->index = index; - -- port->tunneled = FALSE; -+ port->tunneled = NULL; - - port->port_def = port_def; - -@@ -1085,8 +1085,8 @@ gst_omx_component_setup_tunnel (GstOMXComponent * comp1, GstOMXPort * port1, - port2->index); - - if (err == OMX_ErrorNone) { -- port1->tunneled = TRUE; -- port2->tunneled = TRUE; -+ port1->tunneled = port2; -+ port2->tunneled = port1; - } - - GST_DEBUG_OBJECT (comp1->parent, -@@ -1115,7 +1115,8 @@ gst_omx_component_close_tunnel (GstOMXComponent * comp1, GstOMXPort * port1, - g_return_val_if_fail (port2->port_def.eDir == OMX_DirInput, - OMX_ErrorUndefined); - g_return_val_if_fail (comp1->core == comp2->core, OMX_ErrorUndefined); -- g_return_val_if_fail (port1->tunneled && port2->tunneled, OMX_ErrorUndefined); -+ g_return_val_if_fail (port1->tunneled == port2, OMX_ErrorUndefined); -+ g_return_val_if_fail (port2->tunneled == port1, OMX_ErrorUndefined); - - g_mutex_lock (&comp1->lock); - g_mutex_lock (&comp2->lock); -@@ -1136,8 +1137,8 @@ gst_omx_component_close_tunnel (GstOMXComponent * comp1, GstOMXPort * port1, - gst_omx_error_to_string (err), err); - } - -- port1->tunneled = FALSE; -- port2->tunneled = FALSE; -+ port1->tunneled = NULL; -+ port2->tunneled = NULL; - - GST_DEBUG_OBJECT (comp1->parent, - "Closed tunnel between %s port %u and %s port %u", -diff --git a/omx/gstomx.h b/omx/gstomx.h -index 8af81b8..3645b63 100644 ---- a/omx/gstomx.h -+++ b/omx/gstomx.h -@@ -199,7 +199,7 @@ struct _GstOMXPort { - GstOMXComponent *comp; - guint32 index; - -- gboolean tunneled; -+ GstOMXPort *tunneled; - - OMX_PARAM_PORTDEFINITIONTYPE port_def; - GPtrArray *buffers; /* Contains GstOMXBuffer* */ --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0006-gstomxvideoenc-Update-GstBuffer-fields-on-FRC.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0006-gstomxvideoenc-Update-GstBuffer-fields-on-FRC.patch deleted file mode 100644 index 1bd0971a..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0006-gstomxvideoenc-Update-GstBuffer-fields-on-FRC.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 1fdd9ba35575f9d5001509111166e98c9d359984 Mon Sep 17 00:00:00 2001 -From: Nishanth Peethambaran <nishanth.peethambaran@amd.com> -Date: Tue, 22 Mar 2016 19:21:20 -0400 -Subject: [PATCH 3/3] gstomxvideoenc: Update GstBuffer fields on FRC - -Update the ts, duration and offset fields of the encoder output -GstBuffer to ensure the bitstream/container has the right header -information. - -Signed-off-by: Nishanth Peethambaran <nishanth.peethambaran@amd.com> ---- - omx/gstomxvideoenc.c | 13 +++++++++++++ - omx/gstomxvideoenc.h | 1 + - 2 files changed, 14 insertions(+) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index 54c8f2c..e3a1b19 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -285,6 +285,7 @@ gst_omx_video_enc_init (GstOMXVideoEnc * self) - self->framerate_num = GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT; - self->framerate_den = GST_OMX_VIDEO_ENC_FRAMERATE_DEFAULT; - self->xEncodeFramerate = 0; -+ self->out_frame_count = 0; - - g_mutex_init (&self->drain_lock); - g_cond_init (&self->drain_cond); -@@ -977,10 +978,22 @@ gst_omx_video_enc_handle_output_frame (GstOMXVideoEnc * self, GstOMXPort * port, - } - - if (frame) { -+ if (self->xEncodeFramerate) { -+ outbuf->offset = self->out_frame_count++; -+ outbuf->offset_end = self->out_frame_count; -+ frame->pts = outbuf->pts; -+ frame->dts = outbuf->pts; -+ frame->duration = outbuf->duration; -+ } - frame->output_buffer = outbuf; - flow_ret = - gst_video_encoder_finish_frame (GST_VIDEO_ENCODER (self), frame); - } else { -+ if (self->xEncodeFramerate) { -+ outbuf->offset = self->out_frame_count++; -+ outbuf->offset_end = self->out_frame_count; -+ outbuf->dts = outbuf->pts; -+ } - GST_ERROR_OBJECT (self, "No corresponding frame found"); - flow_ret = gst_pad_push (GST_VIDEO_ENCODER_SRC_PAD (self), outbuf); - } -diff --git a/omx/gstomxvideoenc.h b/omx/gstomxvideoenc.h -index f09a23b..653d78c 100644 ---- a/omx/gstomxvideoenc.h -+++ b/omx/gstomxvideoenc.h -@@ -96,6 +96,7 @@ struct _GstOMXVideoEnc - guint32 framerate_num; - guint32 framerate_den; - OMX_U32 xEncodeFramerate; /* Q16 format */ -+ guint32 out_frame_count; - }; - - struct _GstOMXVideoEncClass --- -2.1.4 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0006-omx-add-tunneling-support-between-decoder-and-encode.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0006-omx-add-tunneling-support-between-decoder-and-encode.patch deleted file mode 100644 index aa3e403f..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0006-omx-add-tunneling-support-between-decoder-and-encode.patch +++ /dev/null @@ -1,328 +0,0 @@ -From 17e9d641799a075a085a64d0543c5a51b11fd73d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> -Date: Fri, 13 Sep 2013 03:33:19 -0600 -Subject: [PATCH 06/11] omx: add tunneling support between decoder and - encoders v2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Forward the frames through both the OMX tunnel as well as the gst pad, this -way we can map OMX buffers to their frame counterpart when they left the -tunnel on the other side. - -v2: fix tunnel close and buffer dealloc order - -Signed-off-by: Christian König <christian.koenig@amd.com> ---- - omx/gstomx.c | 6 +++- - omx/gstomx.h | 2 ++ - omx/gstomxvideodec.c | 90 ++++++++++++++++++++++++++++++++++++++++++++------ - omx/gstomxvideoenc.c | 29 +++++++++++++--- - 4 files changed, 110 insertions(+), 17 deletions(-) - -diff --git a/omx/gstomx.c b/omx/gstomx.c -index c8a8927..df3a8ff 100644 ---- a/omx/gstomx.c -+++ b/omx/gstomx.c -@@ -1204,7 +1204,6 @@ gst_omx_port_acquire_buffer (GstOMXPort * port, GstOMXBuffer ** buf) - GstOMXBuffer *_buf = NULL; - - g_return_val_if_fail (port != NULL, GST_OMX_ACQUIRE_BUFFER_ERROR); -- g_return_val_if_fail (!port->tunneled, GST_OMX_ACQUIRE_BUFFER_ERROR); - g_return_val_if_fail (buf != NULL, GST_OMX_ACQUIRE_BUFFER_ERROR); - - *buf = NULL; -@@ -1298,6 +1297,11 @@ retry: - goto done; - } - -+ if (port->tunneled) { -+ ret = GST_OMX_ACQUIRE_BUFFER_TUNNELED; -+ goto done; -+ } -+ - /* - * At this point we have no error or flushing/eos port - * and a properly configured port. -diff --git a/omx/gstomx.h b/omx/gstomx.h -index 3645b63..9b534bd 100644 ---- a/omx/gstomx.h -+++ b/omx/gstomx.h -@@ -124,6 +124,8 @@ typedef enum { - GST_OMX_ACQUIRE_BUFFER_RECONFIGURE, - /* The port is EOS */ - GST_OMX_ACQUIRE_BUFFER_EOS, -+ /* The port is tunneled */ -+ GST_OMX_ACQUIRE_BUFFER_TUNNELED, - /* A fatal error happened */ - GST_OMX_ACQUIRE_BUFFER_ERROR - } GstOMXAcquireBufferReturn; -diff --git a/omx/gstomxvideodec.c b/omx/gstomxvideodec.c -index 020b7d3..e8813fb 100644 ---- a/omx/gstomxvideodec.c -+++ b/omx/gstomxvideodec.c -@@ -50,6 +50,7 @@ - #include <string.h> - - #include "gstomxvideodec.h" -+#include "gstomxvideoenc.h" - - GST_DEBUG_CATEGORY_STATIC (gst_omx_video_dec_debug_category); - #define GST_CAT_DEFAULT gst_omx_video_dec_debug_category -@@ -881,6 +882,11 @@ gst_omx_video_dec_shutdown (GstOMXVideoDec * self) - gst_omx_component_get_state (self->dec, 5 * GST_SECOND); - } - -+ if (self->dec_out_port->tunneled) { -+ gst_omx_component_close_tunnel (self->dec, self->dec_out_port, -+ self->dec_out_port->tunneled->comp, self->dec_out_port->tunneled); -+ } -+ - return TRUE; - } - -@@ -1527,7 +1533,7 @@ done: - static OMX_ERRORTYPE - gst_omx_video_dec_deallocate_output_buffers (GstOMXVideoDec * self) - { -- OMX_ERRORTYPE err; -+ OMX_ERRORTYPE err = OMX_ErrorNone; - - if (self->out_port_pool) { - gst_buffer_pool_set_active (self->out_port_pool, FALSE); -@@ -1543,7 +1549,10 @@ gst_omx_video_dec_deallocate_output_buffers (GstOMXVideoDec * self) - gst_omx_port_deallocate_buffers (self-> - eglimage ? self->egl_out_port : self->dec_out_port); - #else -- err = gst_omx_port_deallocate_buffers (self->dec_out_port); -+ if (!self->dec_out_port->tunneled) -+ err = gst_omx_port_deallocate_buffers (self->dec_out_port); -+ else -+ err = gst_omx_port_set_enabled (self->dec_out_port, FALSE); - #endif - - return err; -@@ -1772,12 +1781,28 @@ gst_omx_video_dec_reconfigure_output_port (GstOMXVideoDec * self) - - GST_VIDEO_DECODER_STREAM_UNLOCK (self); - -+ { -+ GstPad *peer = gst_pad_get_peer (GST_VIDEO_DECODER_SRC_PAD (self)); -+ GstElement *element = peer ? gst_pad_get_parent_element (peer) : NULL; -+ -+ if (element && GST_IS_OMX_VIDEO_ENC (element)) { -+ GstOMXVideoEnc *enc = GST_OMX_VIDEO_ENC (element); -+ -+ gst_omx_component_setup_tunnel (self->dec, self->dec_out_port, -+ enc->enc, enc->enc_in_port); -+ -+ } -+ } -+ - #if defined (USE_OMX_TARGET_RPI) && defined (HAVE_GST_EGL) - enable_port: - #endif -- err = gst_omx_video_dec_allocate_output_buffers (self); -- if (err != OMX_ErrorNone) -- goto done; -+ -+ if (!self->dec_out_port->tunneled) { -+ err = gst_omx_video_dec_allocate_output_buffers (self); -+ if (err != OMX_ErrorNone) -+ goto done; -+ } - - err = gst_omx_port_populate (port); - if (err != OMX_ErrorNone) -@@ -1816,6 +1841,9 @@ gst_omx_video_dec_loop (GstOMXVideoDec * self) - goto flushing; - } else if (acq_return == GST_OMX_ACQUIRE_BUFFER_EOS) { - goto eos; -+ } else if (acq_return == GST_OMX_ACQUIRE_BUFFER_TUNNELED) { -+ gst_pad_pause_task (GST_VIDEO_DECODER_SRC_PAD (self)); -+ return; - } - - if (!gst_pad_has_current_caps (GST_VIDEO_DECODER_SRC_PAD (self)) || -@@ -2657,6 +2685,7 @@ gst_omx_video_dec_set_format (GstVideoDecoder * decoder, - GST_DEBUG_OBJECT (self, "Starting task again"); - - self->downstream_flow_ret = GST_FLOW_OK; -+ - gst_pad_start_task (GST_VIDEO_DECODER_SRC_PAD (self), - (GstTaskFunction) gst_omx_video_dec_loop, decoder, NULL); - -@@ -2703,6 +2732,7 @@ gst_omx_video_dec_reset (GstVideoDecoder * decoder, gboolean hard) - self->last_upstream_ts = 0; - self->eos = FALSE; - self->downstream_flow_ret = GST_FLOW_OK; -+ - gst_pad_start_task (GST_VIDEO_DECODER_SRC_PAD (self), - (GstTaskFunction) gst_omx_video_dec_loop, decoder, NULL); - -@@ -2925,7 +2955,11 @@ gst_omx_video_dec_handle_frame (GstVideoDecoder * decoder, - goto release_error; - } - -- gst_video_codec_frame_unref (frame); -+ if (self->dec_out_port->tunneled) { -+ frame->output_buffer = gst_buffer_new (); -+ gst_video_decoder_finish_frame (GST_VIDEO_DECODER (self), frame); -+ } else -+ gst_video_codec_frame_unref (frame); - - GST_DEBUG_OBJECT (self, "Passed frame to component"); - -@@ -3003,6 +3037,7 @@ gst_omx_video_dec_finish (GstVideoDecoder * decoder) - static GstFlowReturn - gst_omx_video_dec_drain (GstOMXVideoDec * self, gboolean is_eos) - { -+ GstOMXVideoEnc *enc = NULL; - GstOMXVideoDecClass *klass; - GstOMXBuffer *buf; - GstOMXAcquireBufferReturn acq_ret; -@@ -3031,6 +3066,14 @@ gst_omx_video_dec_drain (GstOMXVideoDec * self, gboolean is_eos) - return GST_FLOW_OK; - } - -+ if (self->dec_out_port->tunneled) { -+ GstPad *peer = gst_pad_get_peer (GST_VIDEO_DECODER_SRC_PAD (self)); -+ GstElement *element = peer ? gst_pad_get_parent_element (peer) : NULL; -+ -+ if (element && GST_IS_OMX_VIDEO_ENC (element)) -+ enc = GST_OMX_VIDEO_ENC (element); -+ } -+ - /* Make sure to release the base class stream lock, otherwise - * _loop() can't call _finish_frame() and we might block forever - * because no input buffers are released */ -@@ -3047,8 +3090,14 @@ gst_omx_video_dec_drain (GstOMXVideoDec * self, gboolean is_eos) - return GST_FLOW_ERROR; - } - -- g_mutex_lock (&self->drain_lock); -- self->draining = TRUE; -+ if (enc) { -+ g_mutex_lock (&enc->drain_lock); -+ enc->draining = TRUE; -+ } else { -+ g_mutex_lock (&self->drain_lock); -+ self->draining = TRUE; -+ } -+ - buf->omx_buf->nFilledLen = 0; - buf->omx_buf->nTimeStamp = - gst_util_uint64_scale (self->last_upstream_ts, OMX_TICKS_PER_SECOND, -@@ -3059,6 +3108,10 @@ gst_omx_video_dec_drain (GstOMXVideoDec * self, gboolean is_eos) - if (err != OMX_ErrorNone) { - GST_ERROR_OBJECT (self, "Failed to drain component: %s (0x%08x)", - gst_omx_error_to_string (err), err); -+ if (enc) -+ g_mutex_unlock (&enc->drain_lock); -+ else -+ g_mutex_unlock (&self->drain_lock); - GST_VIDEO_DECODER_STREAM_LOCK (self); - return GST_FLOW_ERROR; - } -@@ -3067,18 +3120,33 @@ gst_omx_video_dec_drain (GstOMXVideoDec * self, gboolean is_eos) - - if (G_UNLIKELY (self->dec->hacks & GST_OMX_HACK_DRAIN_MAY_NOT_RETURN)) { - gint64 wait_until = g_get_monotonic_time () + G_TIME_SPAN_SECOND / 2; -+ gboolean result; -+ -+ if (enc) -+ result = -+ g_cond_wait_until (&enc->drain_cond, &enc->drain_lock, wait_until); -+ else -+ result = -+ g_cond_wait_until (&self->drain_cond, &self->drain_lock, wait_until); - -- if (!g_cond_wait_until (&self->drain_cond, &self->drain_lock, wait_until)) -+ if (!result) - GST_WARNING_OBJECT (self, "Drain timed out"); - else - GST_DEBUG_OBJECT (self, "Drained component"); - - } else { -- g_cond_wait (&self->drain_cond, &self->drain_lock); -+ if (enc) -+ g_cond_wait (&enc->drain_cond, &enc->drain_lock); -+ else -+ g_cond_wait (&self->drain_cond, &self->drain_lock); - GST_DEBUG_OBJECT (self, "Drained component"); - } - -- g_mutex_unlock (&self->drain_lock); -+ if (enc) -+ g_mutex_unlock (&enc->drain_lock); -+ else -+ g_mutex_unlock (&self->drain_lock); -+ - GST_VIDEO_DECODER_STREAM_LOCK (self); - - self->started = FALSE; -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index 3a139bb..8f6cab3 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -364,7 +364,10 @@ gst_omx_video_enc_shutdown (GstOMXVideoEnc * self) - gst_omx_component_get_state (self->enc, 5 * GST_SECOND); - } - gst_omx_component_set_state (self->enc, OMX_StateLoaded); -- gst_omx_port_deallocate_buffers (self->enc_in_port); -+ if (!self->enc_in_port->tunneled) -+ gst_omx_port_deallocate_buffers (self->enc_in_port); -+ else -+ gst_omx_port_set_enabled (self->enc_in_port, FALSE); - gst_omx_port_deallocate_buffers (self->enc_out_port); - if (state > OMX_StateLoaded) - gst_omx_component_get_state (self->enc, 5 * GST_SECOND); -@@ -1086,8 +1089,9 @@ gst_omx_video_enc_set_format (GstVideoEncoder * encoder, - if (gst_omx_port_wait_buffers_released (self->enc_out_port, - 1 * GST_SECOND) != OMX_ErrorNone) - return FALSE; -- if (gst_omx_port_deallocate_buffers (self->enc_in_port) != OMX_ErrorNone) -- return FALSE; -+ if (!self->enc_in_port->tunneled) -+ if (gst_omx_port_deallocate_buffers (self->enc_in_port) != OMX_ErrorNone) -+ return FALSE; - if (gst_omx_port_deallocate_buffers (self->enc_out_port) != OMX_ErrorNone) - return FALSE; - if (gst_omx_port_wait_enabled (self->enc_in_port, -@@ -1225,8 +1229,18 @@ gst_omx_video_enc_set_format (GstVideoEncoder * encoder, - return FALSE; - - /* Need to allocate buffers to reach Idle state */ -- if (gst_omx_port_allocate_buffers (self->enc_in_port) != OMX_ErrorNone) -- return FALSE; -+ if (self->enc_in_port->tunneled) { -+ if (gst_omx_port_set_enabled (self->enc_in_port->tunneled, -+ TRUE) != OMX_ErrorNone) -+ return FALSE; -+ -+ if (gst_omx_port_wait_enabled (self->enc_in_port->tunneled, -+ 1 * GST_SECOND) != OMX_ErrorNone) -+ return FALSE; -+ } else { -+ if (gst_omx_port_allocate_buffers (self->enc_in_port) != OMX_ErrorNone) -+ return FALSE; -+ } - - if (gst_omx_component_get_state (self->enc, - GST_CLOCK_TIME_NONE) != OMX_StateIdle) -@@ -1492,6 +1506,11 @@ gst_omx_video_enc_handle_frame (GstVideoEncoder * encoder, - - port = self->enc_in_port; - -+ if (port->tunneled) { -+ gst_video_codec_frame_unref (frame); -+ return self->downstream_flow_ret; -+ } -+ - while (acq_ret != GST_OMX_ACQUIRE_BUFFER_OK) { - GstClockTime timestamp, duration; - --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0007-gstomxvideoenc-implement-scaling-configuration-suppo.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0007-gstomxvideoenc-implement-scaling-configuration-suppo.patch deleted file mode 100644 index 6db5e742..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0007-gstomxvideoenc-implement-scaling-configuration-suppo.patch +++ /dev/null @@ -1,155 +0,0 @@ -From 9d1fc5ceb72222037b959c1a2c3fe05c50de676a Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Thu, 14 Nov 2013 18:47:24 -0500 -Subject: [PATCH 07/11] gstomxvideoenc: implement scaling configuration - support - -Signed-off-by: Leo Liu <leo.liu@amd.com> ---- - omx/gstomxvideoenc.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++- - omx/gstomxvideoenc.h | 3 +++ - 2 files changed, 75 insertions(+), 1 deletion(-) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index 8f6cab3..ee41fa0 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -96,7 +96,9 @@ enum - PROP_TARGET_BITRATE, - PROP_QUANT_I_FRAMES, - PROP_QUANT_P_FRAMES, -- PROP_QUANT_B_FRAMES -+ PROP_QUANT_B_FRAMES, -+ PROP_SCALING_WIDTH, -+ PROP_SCALING_HEIGHT - }; - - /* FIXME: Better defaults */ -@@ -105,6 +107,8 @@ enum - #define GST_OMX_VIDEO_ENC_QUANT_I_FRAMES_DEFAULT (0xffffffff) - #define GST_OMX_VIDEO_ENC_QUANT_P_FRAMES_DEFAULT (0xffffffff) - #define GST_OMX_VIDEO_ENC_QUANT_B_FRAMES_DEFAULT (0xffffffff) -+#define GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT (0xffffffff) -+#define GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT (0xffffffff) - - /* class initialization */ - -@@ -163,6 +167,20 @@ gst_omx_video_enc_class_init (GstOMXVideoEncClass * klass) - G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | - GST_PARAM_MUTABLE_READY)); - -+ g_object_class_install_property (gobject_class, PROP_SCALING_WIDTH, -+ g_param_spec_uint ("scaling-width", "Scaling Width", -+ "Scaling Width parameter (0xffffffff=component default)", -+ 0, G_MAXUINT, GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT, -+ G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | -+ GST_PARAM_MUTABLE_READY)); -+ -+ g_object_class_install_property (gobject_class, PROP_SCALING_HEIGHT, -+ g_param_spec_uint ("scaling-height", "Scaling Height", -+ "Scaling Height parameter (0xffffffff=component default)", -+ 0, G_MAXUINT, GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT, -+ G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | -+ GST_PARAM_MUTABLE_READY)); -+ - element_class->change_state = - GST_DEBUG_FUNCPTR (gst_omx_video_enc_change_state); - -@@ -197,6 +215,8 @@ gst_omx_video_enc_init (GstOMXVideoEnc * self) - self->quant_i_frames = GST_OMX_VIDEO_ENC_QUANT_I_FRAMES_DEFAULT; - self->quant_p_frames = GST_OMX_VIDEO_ENC_QUANT_P_FRAMES_DEFAULT; - self->quant_b_frames = GST_OMX_VIDEO_ENC_QUANT_B_FRAMES_DEFAULT; -+ self->scaling_width = GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT; -+ self->scaling_height = GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT; - - g_mutex_init (&self->drain_lock); - g_cond_init (&self->drain_cond); -@@ -345,6 +365,45 @@ gst_omx_video_enc_open (GstVideoEncoder * encoder) - - } - } -+ -+ if (self->scaling_width != 0xffffffff || -+ self->scaling_height != 0xffffffff) { -+ OMX_CONFIG_SCALEFACTORTYPE scale_factor; -+ GST_OMX_INIT_STRUCT (&scale_factor); -+ scale_factor.nPortIndex = self->enc_out_port->index; -+ -+ err = gst_omx_component_get_config (self->enc, -+ OMX_IndexConfigCommonScale, &scale_factor); -+ -+ if (err == OMX_ErrorNone) { -+ -+ if (self->scaling_width != 0xffffffff) -+ scale_factor.xWidth = self->scaling_width; -+ if (self->scaling_height != 0xffffffff) -+ scale_factor.xHeight = self->scaling_height; -+ -+ err = -+ gst_omx_component_set_config (self->enc, -+ OMX_IndexConfigCommonScale, &scale_factor); -+ if (err == OMX_ErrorUnsupportedIndex) { -+ GST_WARNING_OBJECT (self, -+ "Setting scale configuration not supported by the component"); -+ } else if (err == OMX_ErrorUnsupportedSetting) { -+ GST_WARNING_OBJECT (self, -+ "Setting scale configuration %u %u not supported by the component", -+ self->scaling_width, self->scaling_height); -+ } else if (err != OMX_ErrorNone) { -+ GST_ERROR_OBJECT (self, -+ "Failed to set scale configuration: %s (0x%08x)", -+ gst_omx_error_to_string (err), err); -+ return FALSE; -+ } -+ } else { -+ GST_ERROR_OBJECT (self, -+ "Failed to set scale configuration: %s (0x%08x)", -+ gst_omx_error_to_string (err), err); -+ } -+ } - } - - return TRUE; -@@ -443,6 +502,12 @@ gst_omx_video_enc_set_property (GObject * object, guint prop_id, - case PROP_QUANT_B_FRAMES: - self->quant_b_frames = g_value_get_uint (value); - break; -+ case PROP_SCALING_WIDTH: -+ self->scaling_width = g_value_get_uint (value); -+ break; -+ case PROP_SCALING_HEIGHT: -+ self->scaling_height = g_value_get_uint (value); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -@@ -471,6 +536,12 @@ gst_omx_video_enc_get_property (GObject * object, guint prop_id, GValue * value, - case PROP_QUANT_B_FRAMES: - g_value_set_uint (value, self->quant_b_frames); - break; -+ case PROP_SCALING_WIDTH: -+ g_value_set_uint (value, self->scaling_width); -+ break; -+ case PROP_SCALING_HEIGHT: -+ g_value_set_uint (value, self->scaling_height); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -diff --git a/omx/gstomxvideoenc.h b/omx/gstomxvideoenc.h -index e266537..86e9c8f 100644 ---- a/omx/gstomxvideoenc.h -+++ b/omx/gstomxvideoenc.h -@@ -77,6 +77,9 @@ struct _GstOMXVideoEnc - guint32 quant_p_frames; - guint32 quant_b_frames; - -+ guint32 scaling_width; -+ guint32 scaling_height; -+ - GstFlowReturn downstream_flow_ret; - }; - --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0008-configure-fix-first-run-of-autogen-automake.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0008-configure-fix-first-run-of-autogen-automake.patch deleted file mode 100644 index 8478cc3a..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0008-configure-fix-first-run-of-autogen-automake.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 8e089ae8249899b8e47cbe7abfe3dd8814458c89 Mon Sep 17 00:00:00 2001 -From: Tim Writer <Tim.Writer@amd.com> -Date: Mon, 25 Nov 2013 15:51:21 -0500 -Subject: [PATCH 08/11] configure: fix first run of autogen/automake - -Without AC_CONFIG_AUX_DIR, libtoolize fails to copy ltmain.sh, -causing the first run of automake to fail. ---- - configure.ac | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/configure.ac b/configure.ac -index fcf4d9d..6dcca1c 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -9,6 +9,10 @@ AC_INIT(GStreamer OpenMAX Plug-ins, 1.0.0.1, - http://bugzilla.gnome.org/enter_bug.cgi?product=GStreamer, - gst-omx) - -+dnl Forces libtoolize to copy ltmain.sh. Without it, automake fails on -+dnl the first run. -+AC_CONFIG_AUX_DIR([.]) -+ - AG_GST_INIT - - dnl initialize automake --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0009-omxvideodec-fix-startup-race-condition.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0009-omxvideodec-fix-startup-race-condition.patch deleted file mode 100644 index df070f44..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0009-omxvideodec-fix-startup-race-condition.patch +++ /dev/null @@ -1,33 +0,0 @@ -From c79c13c43e4d535fdb0c7fc508a7d5219eebe940 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> -Date: Sat, 1 Mar 2014 18:48:17 +0100 -Subject: [PATCH 09/11] omxvideodec: fix startup race condition -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The reset function shouldn't start the src pad -loop if it wasn't started before. - -Signed-off-by: Christian König <christian.koenig@amd.com> ---- - omx/gstomxvideodec.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/omx/gstomxvideodec.c b/omx/gstomxvideodec.c -index e8813fb..00f3951 100644 ---- a/omx/gstomxvideodec.c -+++ b/omx/gstomxvideodec.c -@@ -2703,6 +2703,9 @@ gst_omx_video_dec_reset (GstVideoDecoder * decoder, gboolean hard) - - GST_DEBUG_OBJECT (self, "Resetting decoder"); - -+ if (gst_omx_component_get_state (self->dec, 0) == OMX_StateLoaded) -+ return TRUE; -+ - gst_omx_port_set_flushing (self->dec_in_port, 5 * GST_SECOND, TRUE); - gst_omx_port_set_flushing (self->dec_out_port, 5 * GST_SECOND, TRUE); - --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0010-omxvideoenc-fix-startup-race-condition.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0010-omxvideoenc-fix-startup-race-condition.patch deleted file mode 100644 index 68b89b8a..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0010-omxvideoenc-fix-startup-race-condition.patch +++ /dev/null @@ -1,33 +0,0 @@ -From ba51373c66f4c9c3349eb083c5218b31e4162a6e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> -Date: Sat, 1 Mar 2014 18:49:41 +0100 -Subject: [PATCH 10/11] omxvideoenc: fix startup race condition -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The reset function shouldn't start the src pad -loop if it wasn't started before. - -Signed-off-by: Christian König <christian.koenig@amd.com> ---- - omx/gstomxvideoenc.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index ee41fa0..e65a9e0 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -1359,6 +1359,9 @@ gst_omx_video_enc_reset (GstVideoEncoder * encoder, gboolean hard) - - GST_DEBUG_OBJECT (self, "Resetting encoder"); - -+ if (gst_omx_component_get_state (self->enc, 0) == OMX_StateLoaded) -+ return TRUE; -+ - gst_omx_port_set_flushing (self->enc_in_port, 5 * GST_SECOND, TRUE); - gst_omx_port_set_flushing (self->enc_out_port, 5 * GST_SECOND, TRUE); - --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0011-omx-fix-two-serious-message-handling-bugs.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0011-omx-fix-two-serious-message-handling-bugs.patch deleted file mode 100644 index 6de3b84a..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0011-omx-fix-two-serious-message-handling-bugs.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 6d0b6813745b54eb5dd249ba4446118b21383059 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> -Date: Sat, 1 Mar 2014 22:28:24 +0100 -Subject: [PATCH 11/11] omx: fix two serious message handling bugs - -Waiting for the next message if we already got one -is nonsense and can lead to lockups. - -https://bugzilla.gnome.org/show_bug.cgi?id=725468 ---- - omx/gstomx.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/omx/gstomx.c b/omx/gstomx.c -index df3a8ff..b77c904 100644 ---- a/omx/gstomx.c -+++ b/omx/gstomx.c -@@ -842,8 +842,7 @@ gst_omx_component_get_state (GstOMXComponent * comp, GstClockTime timeout) - g_mutex_unlock (&comp->lock); - if (!g_queue_is_empty (&comp->messages)) { - signalled = TRUE; -- } -- if (timeout == GST_CLOCK_TIME_NONE) { -+ } else if (timeout == GST_CLOCK_TIME_NONE) { - g_cond_wait (&comp->messages_cond, &comp->messages_lock); - signalled = TRUE; - } else { -@@ -1519,8 +1518,7 @@ gst_omx_port_set_flushing (GstOMXPort * port, GstClockTime timeout, - - if (!g_queue_is_empty (&comp->messages)) { - signalled = TRUE; -- } -- if (timeout == GST_CLOCK_TIME_NONE) { -+ } else if (timeout == GST_CLOCK_TIME_NONE) { - g_cond_wait (&comp->messages_cond, &comp->messages_lock); - signalled = TRUE; - } else { --- -1.7.9.5 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0012-gstomxvideoenc-implement-capture-configuration-suppo.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0012-gstomxvideoenc-implement-capture-configuration-suppo.patch deleted file mode 100644 index 3df8f37f..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0012-gstomxvideoenc-implement-capture-configuration-suppo.patch +++ /dev/null @@ -1,131 +0,0 @@ -From eb7b8df4eb363f3799d2264f4761401aeb40fa26 Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Mon, 24 Feb 2014 15:03:50 -0500 -Subject: [PATCH 12/14] gstomxvideoenc: implement capture configuration support - -Signed-off-by: Leo Liu <leo.liu@amd.com> ---- - omx/gstomxvideoenc.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++- - omx/gstomxvideoenc.h | 2 ++ - 2 files changed, 52 insertions(+), 1 deletion(-) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index e65a9e0..cbb8cb9 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -98,7 +98,8 @@ enum - PROP_QUANT_P_FRAMES, - PROP_QUANT_B_FRAMES, - PROP_SCALING_WIDTH, -- PROP_SCALING_HEIGHT -+ PROP_SCALING_HEIGHT, -+ PROP_CAPTURE - }; - - /* FIXME: Better defaults */ -@@ -109,6 +110,7 @@ enum - #define GST_OMX_VIDEO_ENC_QUANT_B_FRAMES_DEFAULT (0xffffffff) - #define GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT (0xffffffff) - #define GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT (0xffffffff) -+#define GST_OMX_VIDEO_ENC_CAPTURE_DEFAULT (FALSE) - - /* class initialization */ - -@@ -181,6 +183,12 @@ gst_omx_video_enc_class_init (GstOMXVideoEncClass * klass) - G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | - GST_PARAM_MUTABLE_READY)); - -+ g_object_class_install_property (gobject_class, PROP_CAPTURE, -+ g_param_spec_boolean ("capture", "Capture", -+ "Capture parameter (FALSE=component default)", -+ FALSE, G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | -+ GST_PARAM_MUTABLE_READY)); -+ - element_class->change_state = - GST_DEBUG_FUNCPTR (gst_omx_video_enc_change_state); - -@@ -217,6 +225,7 @@ gst_omx_video_enc_init (GstOMXVideoEnc * self) - self->quant_b_frames = GST_OMX_VIDEO_ENC_QUANT_B_FRAMES_DEFAULT; - self->scaling_width = GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT; - self->scaling_height = GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT; -+ self->capture = GST_OMX_VIDEO_ENC_CAPTURE_DEFAULT; - - g_mutex_init (&self->drain_lock); - g_cond_init (&self->drain_cond); -@@ -404,6 +413,40 @@ gst_omx_video_enc_open (GstVideoEncoder * encoder) - gst_omx_error_to_string (err), err); - } - } -+ -+ if (self->capture) { -+ OMX_CONFIG_BOOLEANTYPE capture_factor; -+ GST_OMX_INIT_STRUCT (&capture_factor); -+ -+ err = gst_omx_component_get_config (self->enc, -+ OMX_IndexConfigCapturing, &capture_factor); -+ -+ if (err == OMX_ErrorNone) { -+ -+ if (self->capture) -+ capture_factor.bEnabled = TRUE; -+ -+ err = -+ gst_omx_component_set_config (self->enc, -+ OMX_IndexConfigCapturing, &capture_factor); -+ if (err == OMX_ErrorUnsupportedIndex) { -+ GST_WARNING_OBJECT (self, -+ "Setting capture configuration not supported by the component"); -+ } else if (err == OMX_ErrorUnsupportedSetting) { -+ GST_WARNING_OBJECT (self, -+ "Setting capture configuration not supported by the component"); -+ } else if (err != OMX_ErrorNone) { -+ GST_ERROR_OBJECT (self, -+ "Failed to set capture configuration: %s (0x%08x)", -+ gst_omx_error_to_string (err), err); -+ return FALSE; -+ } -+ } else { -+ GST_ERROR_OBJECT (self, -+ "Failed to set capture configuration: %s (0x%08x)", -+ gst_omx_error_to_string (err), err); -+ } -+ } - } - - return TRUE; -@@ -508,6 +551,9 @@ gst_omx_video_enc_set_property (GObject * object, guint prop_id, - case PROP_SCALING_HEIGHT: - self->scaling_height = g_value_get_uint (value); - break; -+ case PROP_CAPTURE: -+ self->capture = g_value_get_boolean (value); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -@@ -542,6 +588,9 @@ gst_omx_video_enc_get_property (GObject * object, guint prop_id, GValue * value, - case PROP_SCALING_HEIGHT: - g_value_set_uint (value, self->scaling_height); - break; -+ case PROP_CAPTURE: -+ g_value_set_boolean (value, self->capture); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -diff --git a/omx/gstomxvideoenc.h b/omx/gstomxvideoenc.h -index 86e9c8f..e9844b8 100644 ---- a/omx/gstomxvideoenc.h -+++ b/omx/gstomxvideoenc.h -@@ -80,6 +80,8 @@ struct _GstOMXVideoEnc - guint32 scaling_width; - guint32 scaling_height; - -+ gboolean capture; -+ - GstFlowReturn downstream_flow_ret; - }; - --- -1.9.1 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0013-gstomxvideoenc-add-capture-geometry-support.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0013-gstomxvideoenc-add-capture-geometry-support.patch deleted file mode 100644 index 72f579ba..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0013-gstomxvideoenc-add-capture-geometry-support.patch +++ /dev/null @@ -1,158 +0,0 @@ -From 407a4cdc9fe7b8c4e8a3a5a76a0c9e6a34b4cd96 Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Mon, 3 Mar 2014 16:38:20 -0500 -Subject: [PATCH 13/14] gstomxvideoenc: add capture geometry support - -Signed-off-by: Leo Liu <leo.liu@amd.com> ---- - omx/gstomxvideoenc.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++++---- - omx/gstomxvideoenc.h | 2 ++ - 2 files changed, 75 insertions(+), 5 deletions(-) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index cbb8cb9..83c68fe 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -99,7 +99,9 @@ enum - PROP_QUANT_B_FRAMES, - PROP_SCALING_WIDTH, - PROP_SCALING_HEIGHT, -- PROP_CAPTURE -+ PROP_CAPTURE, -+ PROP_POS_X, -+ PROP_POS_Y - }; - - /* FIXME: Better defaults */ -@@ -111,6 +113,8 @@ enum - #define GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT (0xffffffff) - #define GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT (0xffffffff) - #define GST_OMX_VIDEO_ENC_CAPTURE_DEFAULT (FALSE) -+#define GST_OMX_VIDEO_ENC_POS_X_DEFAULT (0) -+#define GST_OMX_VIDEO_ENC_POS_Y_DEFAULT (0) - - /* class initialization */ - -@@ -189,6 +193,20 @@ gst_omx_video_enc_class_init (GstOMXVideoEncClass * klass) - FALSE, G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | - GST_PARAM_MUTABLE_READY)); - -+ g_object_class_install_property (gobject_class, PROP_POS_X, -+ g_param_spec_uint ("pos-x", "Position X", -+ "Capture Position X parameter (0=component default)", -+ 0, G_MAXUINT, GST_OMX_VIDEO_ENC_POS_X_DEFAULT, -+ G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | -+ GST_PARAM_MUTABLE_READY)); -+ -+ g_object_class_install_property (gobject_class, PROP_POS_Y, -+ g_param_spec_uint ("pos-y", "Position Y", -+ "Capture Position Y parameter (0=component default)", -+ 0, G_MAXUINT, GST_OMX_VIDEO_ENC_POS_Y_DEFAULT, -+ G_PARAM_READWRITE | G_PARAM_STATIC_STRINGS | -+ GST_PARAM_MUTABLE_READY)); -+ - element_class->change_state = - GST_DEBUG_FUNCPTR (gst_omx_video_enc_change_state); - -@@ -226,6 +244,8 @@ gst_omx_video_enc_init (GstOMXVideoEnc * self) - self->scaling_width = GST_OMX_VIDEO_ENC_SCALING_WIDTH_DEFAULT; - self->scaling_height = GST_OMX_VIDEO_ENC_SCALING_HEIGHT_DEFAULT; - self->capture = GST_OMX_VIDEO_ENC_CAPTURE_DEFAULT; -+ self->pos_x = GST_OMX_VIDEO_ENC_POS_X_DEFAULT; -+ self->pos_y = GST_OMX_VIDEO_ENC_POS_Y_DEFAULT; - - g_mutex_init (&self->drain_lock); - g_cond_init (&self->drain_cond); -@@ -426,10 +446,46 @@ gst_omx_video_enc_open (GstVideoEncoder * encoder) - if (self->capture) - capture_factor.bEnabled = TRUE; - -- err = -- gst_omx_component_set_config (self->enc, -- OMX_IndexConfigCapturing, &capture_factor); -- if (err == OMX_ErrorUnsupportedIndex) { -+ err = gst_omx_component_set_config (self->enc, -+ OMX_IndexConfigCapturing, &capture_factor); -+ if (err == OMX_ErrorNone) { -+ if (self->pos_x || self->pos_y) { -+ OMX_CONFIG_POINTTYPE pos_factor; -+ -+ GST_OMX_INIT_STRUCT (&pos_factor); -+ pos_factor.nPortIndex = self->enc_out_port->index; -+ -+ err = gst_omx_component_get_config (self->enc, -+ OMX_IndexConfigCommonOutputPosition, &pos_factor); -+ -+ if (err == OMX_ErrorNone) { -+ if (self->pos_x) -+ pos_factor.nX = self->pos_x; -+ if (self->pos_y) -+ pos_factor.nY = self->pos_y; -+ err = gst_omx_component_set_config (self->enc, -+ OMX_IndexConfigCommonOutputPosition, &pos_factor); -+ if (err == OMX_ErrorUnsupportedIndex) { -+ GST_WARNING_OBJECT (self, -+ "Setting capture position configuration not supported by the component"); -+ } else if (err == OMX_ErrorUnsupportedSetting) { -+ GST_WARNING_OBJECT (self, -+ "Setting capture position configuration %u %u not supported by the component", -+ self->pos_x, self->pos_y); -+ } else if (err != OMX_ErrorNone) { -+ GST_ERROR_OBJECT (self, -+ "Failed to set capture position configuration: %s (0x%08x)", -+ gst_omx_error_to_string (err), err); -+ return FALSE; -+ } -+ }else { -+ GST_ERROR_OBJECT (self, -+ "Failed to set capture position configuration: %s (0x%08x)", -+ gst_omx_error_to_string (err), err); -+ } -+ } -+ } -+ else if (err == OMX_ErrorUnsupportedIndex) { - GST_WARNING_OBJECT (self, - "Setting capture configuration not supported by the component"); - } else if (err == OMX_ErrorUnsupportedSetting) { -@@ -554,6 +610,12 @@ gst_omx_video_enc_set_property (GObject * object, guint prop_id, - case PROP_CAPTURE: - self->capture = g_value_get_boolean (value); - break; -+ case PROP_POS_X: -+ self->pos_x = g_value_get_uint (value); -+ break; -+ case PROP_POS_Y: -+ self->pos_y = g_value_get_uint (value); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -@@ -591,6 +653,12 @@ gst_omx_video_enc_get_property (GObject * object, guint prop_id, GValue * value, - case PROP_CAPTURE: - g_value_set_boolean (value, self->capture); - break; -+ case PROP_POS_X: -+ g_value_set_uint (value, self->pos_x); -+ break; -+ case PROP_POS_Y: -+ g_value_set_uint (value, self->pos_y); -+ break; - default: - G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); - break; -diff --git a/omx/gstomxvideoenc.h b/omx/gstomxvideoenc.h -index e9844b8..3de563b 100644 ---- a/omx/gstomxvideoenc.h -+++ b/omx/gstomxvideoenc.h -@@ -81,6 +81,8 @@ struct _GstOMXVideoEnc - guint32 scaling_height; - - gboolean capture; -+ guint32 pos_x; -+ guint32 pos_y; - - GstFlowReturn downstream_flow_ret; - }; --- -1.9.1 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0014-gstomxvideoenc-reduce-shutdown-timeout-for-tunnellin.patch b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0014-gstomxvideoenc-reduce-shutdown-timeout-for-tunnellin.patch deleted file mode 100644 index 2a8d1c42..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx/0014-gstomxvideoenc-reduce-shutdown-timeout-for-tunnellin.patch +++ /dev/null @@ -1,29 +0,0 @@ -From c321d1666fd107d5e3a673789ddf5b9db2b831ec Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Fri, 22 Aug 2014 12:37:55 -0400 -Subject: [PATCH 14/14] gstomxvideoenc: reduce shutdown timeout for tunnelling - -Signed-off-by: Leo Liu <leo.liu@amd.com> ---- - omx/gstomxvideoenc.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/omx/gstomxvideoenc.c b/omx/gstomxvideoenc.c -index 83c68fe..f42ec13 100644 ---- a/omx/gstomxvideoenc.c -+++ b/omx/gstomxvideoenc.c -@@ -528,7 +528,10 @@ gst_omx_video_enc_shutdown (GstOMXVideoEnc * self) - gst_omx_port_set_enabled (self->enc_in_port, FALSE); - gst_omx_port_deallocate_buffers (self->enc_out_port); - if (state > OMX_StateLoaded) -- gst_omx_component_get_state (self->enc, 5 * GST_SECOND); -+ if (!self->enc_in_port->tunneled) -+ gst_omx_component_get_state (self->enc, 5 * GST_SECOND); -+ else -+ gst_omx_component_get_state (self->enc, 1 * GST_SECOND); - } - - return TRUE; --- -1.9.1 - diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx_1.12.%.bbappend b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx_1.12.%.bbappend new file mode 100644 index 00000000..628ea68e --- /dev/null +++ b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx_1.12.%.bbappend @@ -0,0 +1,16 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + +# +# Remove plugins-bad from DEPENDS as it is +# not strictly needed. +# +DEPENDS_remove_amd = "gstreamer1.0-plugins-bad" + +SRC_URI_append_amd = " file://0001-adjust-gstomx.conf-for-mesa.patch" + +# +# This package should not have commercial license flags. +# There is discussion in the OE community about fixing this +# but in the meantime we'll explicitly remove it here. +# +LICENSE_FLAGS_remove = "commercial" diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx_git.bbappend b/common/recipes-multimedia/gstreamer/gstreamer1.0-omx_git.bbappend deleted file mode 100644 index d55b14ce..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-omx_git.bbappend +++ /dev/null @@ -1,48 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" - -# -# Remove plugins-bad from DEPENDS as it is -# not strictly needed. -# -DEPENDS_remove_amd = "gstreamer1.0-plugins-bad" - -# -# Remove the patch as it is not needed with the new SRCREV we are using -# -SRC_URI_remove_amd = "file://0001-omx-fixed-type-error-in-printf-call.patch" - -SRC_URI_append_amd = " \ - file://0001-gstomxvideodec-fix-multithreads-negotiation-problem-.patch \ - file://0002-gstomxvideodec-remove-dead-code.patch \ - file://0003-gstomxvideodec-simplify-_find_nearest_frame.patch \ - file://0004-gstomxvideoenc-simplify-_find_nearest_frame.patch \ - file://0005-omx-improve-tunneling-support.patch \ - file://0006-omx-add-tunneling-support-between-decoder-and-encode.patch \ - file://0007-gstomxvideoenc-implement-scaling-configuration-suppo.patch \ - file://0008-configure-fix-first-run-of-autogen-automake.patch \ - file://0009-omxvideodec-fix-startup-race-condition.patch \ - file://0010-omxvideoenc-fix-startup-race-condition.patch \ - file://0011-omx-fix-two-serious-message-handling-bugs.patch \ - file://0012-gstomxvideoenc-implement-capture-configuration-suppo.patch \ - file://0013-gstomxvideoenc-add-capture-geometry-support.patch \ - file://0014-gstomxvideoenc-reduce-shutdown-timeout-for-tunnellin.patch \ - ${@bb.utils.contains("RT_KERNEL_AMD", "yes", "", "file://0001-gstomxvideoenc-use-scaling-default-macro-s.patch", d)} \ - ${@bb.utils.contains("RT_KERNEL_AMD", "yes", "", "file://0002-gstomxvideoenc-fix-srcpad-caps-when-scaling-property.patch", d)} \ - ${@bb.utils.contains("RT_KERNEL_AMD", "yes", "", "file://0003-gstomxvideoenc-add-fix-timestamp-property.patch", d)} \ - ${@bb.utils.contains("RT_KERNEL_AMD", "yes", "", "file://0004-gstomxvideoenc-add-force-keyframe-period-property.patch", d)} \ - ${@bb.utils.contains("RT_KERNEL_AMD", "yes", "", "file://0005-gstomxvideoenc-Add-new-property-to-set-framerate.patch", d)} \ - ${@bb.utils.contains("RT_KERNEL_AMD", "yes", "", "file://0006-gstomxvideoenc-Update-GstBuffer-fields-on-FRC.patch", d)} \ - ${@bb.utils.contains("RT_KERNEL_AMD", "yes", "", "file://0001-adjust-gstomx.conf-for-mesa.patch", d)} \ - " - -SRCREV_gst-omx_amd = "c44cd849400b90f5f4b1f4f429278d9685b1daca" -SRCREV_common_amd = "1a07da9a64c733842651ece62ddefebedd29c2da" - -PV .= "+git${SRCPV}" - -# -# This package should not have commercial license flags. -# There is discussion in the OE community about fixing this -# but in the meantime we'll explicitly remove it here. -# -LICENSE_FLAGS_remove = "commercial" diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-vaapi.inc b/common/recipes-multimedia/gstreamer/gstreamer1.0-vaapi.inc deleted file mode 100644 index b8e70704..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-vaapi.inc +++ /dev/null @@ -1,37 +0,0 @@ -SUMMARY = "VA-API support to GStreamer" -DESCRIPTION = "gstreamer-vaapi consists of a collection of VA-API \ -based plugins for GStreamer and helper libraries: `vaapidecode', \ -`vaapiconvert', and `vaapisink'." - -REALPN = "gstreamer-vaapi" -FILESPATH = "${@base_set_filespath(["${FILE_DIRNAME}/${REALPN}", "${FILE_DIRNAME}/${REALPN}"], d)}" - -LICENSE = "LGPLv2.1+" -LIC_FILES_CHKSUM = "file://COPYING.LIB;md5=4fbd65380cdd255951079008b364516c" - -DEPENDS = "libva" - -SRC_URI = "https://gstreamer.freedesktop.org/src/${REALPN}/${REALPN}-${PV}.tar.xz \ - file://install-tests.patch" - -S = "${WORKDIR}/${REALPN}-${PV}" - -inherit autotools pkgconfig gtk-doc - -PACKAGES =+ "${PN}-tests" - -PACKAGECONFIG ??= "drm \ - ${@bb.utils.contains("DISTRO_FEATURES", "opengl x11", "glx", "", d)} \ - ${@bb.utils.contains("DISTRO_FEATURES", "wayland", "wayland", "", d)} \ - ${@bb.utils.contains("DISTRO_FEATURES", "x11", "x11", "", d)}" - -PACKAGECONFIG[drm] = "--enable-drm,--disable-drm,udev libdrm" -PACKAGECONFIG[glx] = "--enable-glx,--disable-glx,virtual/mesa" -PACKAGECONFIG[egl] = "--enable-egl,--disable-egl,gstreamer-gl-1.0" -PACKAGECONFIG[wayland] = "--enable-wayland,--disable-wayland,wayland" -PACKAGECONFIG[x11] = "--enable-x11,--disable-x11,virtual/libx11 libxrandr libxrender" - -FILES_${PN} += "${libdir}/gstreamer-*/*.so" -FILES_${PN}-dbg += "${libdir}/gstreamer-*/.debug" -FILES_${PN}-dev += "${libdir}/gstreamer-*/*.la ${libdir}/gstreamer-*/*.a" -FILES_${PN}-tests = "${bindir}/*" diff --git a/common/recipes-multimedia/gstreamer/gstreamer1.0-vaapi_1.8.3.bb b/common/recipes-multimedia/gstreamer/gstreamer1.0-vaapi_1.8.3.bb deleted file mode 100644 index 6951703c..00000000 --- a/common/recipes-multimedia/gstreamer/gstreamer1.0-vaapi_1.8.3.bb +++ /dev/null @@ -1,6 +0,0 @@ -require gstreamer1.0-vaapi.inc - -DEPENDS += "gstreamer1.0 gstreamer1.0-plugins-base gstreamer1.0-plugins-bad" - -SRC_URI[md5sum] = "727267a0a7a8dcb76b8c58cdf5ea61d4" -SRC_URI[sha256sum] = "6cf3ded097924d23df40239c8f00811d1c727aa41cdc9baaedfc2a39ff2aac0c" diff --git a/common/recipes-multimedia/libomxil/libomxil_0.9.3.bbappend b/common/recipes-multimedia/libomxil/libomxil_0.9.3.bbappend index 12d21b31..aadab2cd 100644 --- a/common/recipes-multimedia/libomxil/libomxil_0.9.3.bbappend +++ b/common/recipes-multimedia/libomxil/libomxil_0.9.3.bbappend @@ -30,10 +30,6 @@ do_install_append_amd () { PACKAGES_prepend_amd = "${PN}-test " FILES_${PN}-test_amd = "${bindir}/omxvolcontroltest ${bindir}/omxaudiomixertest ${bindir}/omxrmtest" -pkg_postinst_${PN}_amd () { - if test -n "$D"; then - exit 1 - else - OMX_BELLAGIO_REGISTRY=${ROOT_HOME}/.omxregister ${bindir}/omxregister-bellagio -v - fi +pkg_postinst_ontarget_${PN}_amd () { + OMX_BELLAGIO_REGISTRY=${ROOT_HOME}/.omxregister ${bindir}/omxregister-bellagio -v } diff --git a/common/recipes-multimedia/mpv/mpv_%.bbappend b/common/recipes-multimedia/mpv/mpv_%.bbappend index f23b1cbc..45addc3c 100644 --- a/common/recipes-multimedia/mpv/mpv_%.bbappend +++ b/common/recipes-multimedia/mpv/mpv_%.bbappend @@ -1,9 +1,4 @@ -PACKAGECONFIG[drm] = "--enable-drm, --disable-drm, libdrm" -PACKAGECONFIG[gbm] = "--enable-gbm, --disable-gbm, virtual/libgl" -PACKAGECONFIG[vdpau] = "--enable-vdpau, --disable-vdpau, libvdpau" -PACKAGECONFIG[va] = "--enable-vaapi, --disable-vaapi, libva" - -PACKAGECONFIG_append_amdx86 = " drm gbm vdpau va" +PACKAGECONFIG_append_amdx86 = " drm gbm vdpau vaapi" PACKAGECONFIG_remove_amdx86 = "lua" EXTRA_OECONF_remove = "--disable-gl" diff --git a/common/recipes-sato/images/core-image-sato.bbappend b/common/recipes-sato/images/core-image-sato.bbappend deleted file mode 100644 index 40e53b7f..00000000 --- a/common/recipes-sato/images/core-image-sato.bbappend +++ /dev/null @@ -1,16 +0,0 @@ -require conf/machine/include/amd-common.inc - -IMAGE_INSTALL_append_amdgpu = " mesa-demos" -IMAGE_INSTALL_append_radeon = " mesa-demos" - -VULKAN_COMPONENTS = "" -CODEXL_COMPONENTS = "" - -VULKAN_COMPONENTS_amdfalconx86 = "glslang spirv-tools vulkan-loader-layers vulkan-tools vulkan-samples" -CODEXL_COMPONENTS_amdfalconx86 = "codexl codexl-examples" - -VULKAN_COMPONENTS_v1000 = "amdvlk glslang spirv-tools vulkan-loader-layers vulkan-tools vulkan-samples" - -IMAGE_INSTALL_append = "${@bb.utils.contains("INCLUDE_VULKAN", "yes", " ${VULKAN_COMPONENTS}", "", d)} \ - ${@bb.utils.contains("INCLUDE_CODEXL", "yes", " ${CODEXL_COMPONENTS}", "", d)} \ - " diff --git a/common/recipes-sato/matchbox-keyboard/matchbox-keyboard_0.1.1.bbappend b/common/recipes-sato/matchbox-keyboard/matchbox-keyboard_0.1.1.bbappend new file mode 100644 index 00000000..812c36c7 --- /dev/null +++ b/common/recipes-sato/matchbox-keyboard/matchbox-keyboard_0.1.1.bbappend @@ -0,0 +1,12 @@ +gtk_immodule_cache_postinst_amd() { +} +pkg_postinst_matchbox-keyboard-im_amd () { +} +pkg_postinst_ontarget_matchbox-keyboard-im_amd () { + if [ ! -z `which gtk-query-immodules-2.0` ]; then + gtk-query-immodules-2.0 > ${libdir}/gtk-2.0/2.10.0/immodules.cache + fi + if [ ! -z `which gtk-query-immodules-3.0` ]; then + gtk-query-immodules-3.0 > ${libdir}/gtk-3.0/3.0.0/immodules.cache + fi +} diff --git a/common/recipes-support/fltk/fltk/0001-fix_undefined_Fl_XFont_On_Demand.patch b/common/recipes-support/fltk/fltk/0001-fix_undefined_Fl_XFont_On_Demand.patch deleted file mode 100644 index b162de62..00000000 --- a/common/recipes-support/fltk/fltk/0001-fix_undefined_Fl_XFont_On_Demand.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff --git a/FL/x.H b/FL/x.H -index 85c6f6c..0ea132f 100644 ---- a/FL/x.H -+++ b/FL/x.H -@@ -114,7 +114,7 @@ FL_EXPORT Fl_Region XRectangleRegion(int x, int y, int w, int h); // in fl_rect. - // With Xlib / X11 fonts, fl_xfont will return the current selected font. - // With XFT / X11 fonts, fl_xfont will attempt to return the bitmap "core" font most - // similar to (usually the same as) the current XFT font. --class Fl_XFont_On_Demand -+class FL_EXPORT Fl_XFont_On_Demand - { - public: - Fl_XFont_On_Demand(XFontStruct* p = NULL) : ptr(p) { } diff --git a/common/recipes-support/fltk/fltk_1.3.3.bbappend b/common/recipes-support/fltk/fltk_1.3.3.bbappend deleted file mode 100644 index 825db2bd..00000000 --- a/common/recipes-support/fltk/fltk_1.3.3.bbappend +++ /dev/null @@ -1,3 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" - -SRC_URI_append += "file://0001-fix_undefined_Fl_XFont_On_Demand.patch" diff --git a/common/recipes-x11/images/core-image-x11.bbappend b/common/recipes-x11/images/core-image-x11.bbappend deleted file mode 100644 index cb597e98..00000000 --- a/common/recipes-x11/images/core-image-x11.bbappend +++ /dev/null @@ -1 +0,0 @@ -require conf/machine/include/amd-common.inc diff --git a/meta-amdfalconx86/conf/layer.conf b/meta-amdfalconx86/conf/layer.conf index a4ee8991..0aa17d32 100644 --- a/meta-amdfalconx86/conf/layer.conf +++ b/meta-amdfalconx86/conf/layer.conf @@ -8,5 +8,6 @@ BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ BBFILE_COLLECTIONS += "amdfalconx86" BBFILE_PATTERN_amdfalconx86 = "^${LAYERDIR}/" BBFILE_PRIORITY_amdfalconx86 = "14" +LAYERSERIES_COMPAT_amdfalconx86 = "sumo" LAYERDEPENDS_amdfalconx86 = "amd openembedded-layer" diff --git a/meta-amdfalconx86/conf/local.conf.append.amdfalconx86 b/meta-amdfalconx86/conf/local.conf.append.amdfalconx86 index 742f5e5e..68cf3405 100644 --- a/meta-amdfalconx86/conf/local.conf.append.amdfalconx86 +++ b/meta-amdfalconx86/conf/local.conf.append.amdfalconx86 @@ -27,7 +27,7 @@ RT_KERNEL_AMD = "no" # or software. INCLUDE_MPV ??= "no" -COMMERCIAL_LIC_FLAGS_MPV = "commercial_ffmpeg commercial_x264" +COMMERCIAL_LIC_FLAGS_MPV = "commercial_mpv commercial_ffmpeg commercial_x264" LICENSE_FLAGS_WHITELIST_append = "${@' ${COMMERCIAL_LIC_FLAGS_MPV}' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}" CORE_IMAGE_EXTRA_INSTALL_append = "${@' mpv' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}" diff --git a/meta-amdfalconx86/conf/machine/amdfalconx86.conf b/meta-amdfalconx86/conf/machine/amdfalconx86.conf index 81c1f235..ce28890a 100644 --- a/meta-amdfalconx86/conf/machine/amdfalconx86.conf +++ b/meta-amdfalconx86/conf/machine/amdfalconx86.conf @@ -5,10 +5,14 @@ PREFERRED_PROVIDER_virtual/kernel ?= "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "linux-yocto-rt", "linux-yocto", d)}" PREFERRED_VERSION_linux-yocto-rt ?= "4.4%" -PREFERRED_VERSION_libdrm ?= "2.4.66" require conf/machine/include/tune-amdfalconx86.inc +# Add machine specific AMD features and feature pkgs here +EXTRA_IMAGE_FEATURES += "amd-feature-graphics amd-feature-debug-profile" +VULKAN_PKGS_amdfalconx86 = "glslang spirv-tools vulkan-loader-layers vulkan-tools vulkan-samples" +CODEXL_PKGS_amdfalconx86 = "codexl codexl-examples" + include conf/machine/include/amd-common-configurations.inc include conf/machine/include/amd-customer-configurations.inc diff --git a/meta-amdfalconx86/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.26.bb b/meta-amdfalconx86/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.26.bb index 5a6761c6..fe8fb10b 100644 --- a/meta-amdfalconx86/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.26.bb +++ b/meta-amdfalconx86/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.26.bb @@ -57,8 +57,8 @@ do_install_append() { # Conditional building of vktraceviewer QTBITS ?= "${@bb.utils.contains('BBFILE_COLLECTIONS', 'qt5-layer', 'cmake_qt5', '',d)}" inherit ${QTBITS} -DEPENDS += "${@base_conditional('QTBITS', '', '', 'libxcb qtsvg', d)}" -RDEPENDS_${PN}_append = " ${@base_conditional('QTBITS', '', '', 'qtsvg', d)}" +DEPENDS += "${@oe.utils.conditional('QTBITS', '', '', 'libxcb qtsvg', d)}" +RDEPENDS_${PN}_append = " ${@oe.utils.conditional('QTBITS', '', '', 'qtsvg', d)}" do_install_append() { if [ "${QTBITS}" != "" ] then diff --git a/meta-snowyowl/conf/layer.conf b/meta-snowyowl/conf/layer.conf index 598d973c..8810231e 100644 --- a/meta-snowyowl/conf/layer.conf +++ b/meta-snowyowl/conf/layer.conf @@ -8,5 +8,6 @@ BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ BBFILE_COLLECTIONS += "snowyowl" BBFILE_PATTERN_snowyowl = "^${LAYERDIR}/" BBFILE_PRIORITY_snowyowl = "14" +LAYERSERIES_COMPAT_snowyowl = "sumo" LAYERDEPENDS_snowyowl = "amd" diff --git a/meta-snowyowl/conf/machine/snowyowl.conf b/meta-snowyowl/conf/machine/snowyowl.conf index 1035486f..38a78f87 100755..100644 --- a/meta-snowyowl/conf/machine/snowyowl.conf +++ b/meta-snowyowl/conf/machine/snowyowl.conf @@ -11,6 +11,10 @@ require conf/machine/include/tune-snowyowl.inc RELEASE_IMAGE ?= "console-image" +# Add machine specific AMD features and feature pkgs here +EXTRA_IMAGE_FEATURES += "amd-feature-networking" +DPDK_PKGS_snowyowl = "dpdk dpdk-examples dpdk-test" + include conf/machine/include/amd-common-configurations.inc include conf/machine/include/amd-customer-configurations.inc diff --git a/meta-snowyowl/recipes-kernel/lttng/lttng-modules_git.bbappend b/meta-snowyowl/recipes-kernel/lttng/lttng-modules_%.bbappend index cae9d002..cae9d002 100644 --- a/meta-snowyowl/recipes-kernel/lttng/lttng-modules_git.bbappend +++ b/meta-snowyowl/recipes-kernel/lttng/lttng-modules_%.bbappend diff --git a/meta-steppeeagle/conf/layer.conf b/meta-steppeeagle/conf/layer.conf index 0a820bf4..cfa18612 100644 --- a/meta-steppeeagle/conf/layer.conf +++ b/meta-steppeeagle/conf/layer.conf @@ -8,5 +8,6 @@ BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ BBFILE_COLLECTIONS += "steppeeagle" BBFILE_PATTERN_steppeeagle = "^${LAYERDIR}/" BBFILE_PRIORITY_steppeeagle = "14" +LAYERSERIES_COMPAT_steppeeagle = "sumo" LAYERDEPENDS_steppeeagle = "amd openembedded-layer" diff --git a/meta-steppeeagle/conf/local.conf.append.steppeeagle b/meta-steppeeagle/conf/local.conf.append.steppeeagle index c3f1b0b6..9ed86ffe 100644 --- a/meta-steppeeagle/conf/local.conf.append.steppeeagle +++ b/meta-steppeeagle/conf/local.conf.append.steppeeagle @@ -23,7 +23,7 @@ # or software. INCLUDE_MPV ??= "no" -COMMERCIAL_LIC_FLAGS_MPV = "commercial_ffmpeg commercial_x264" +COMMERCIAL_LIC_FLAGS_MPV = "commercial_mpv commercial_ffmpeg commercial_x264" LICENSE_FLAGS_WHITELIST .= "${@' ${COMMERCIAL_LIC_FLAGS_MPV}' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}" CORE_IMAGE_EXTRA_INSTALL .= "${@' mpv' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}" diff --git a/meta-v1000/conf/layer.conf b/meta-v1000/conf/layer.conf index 0940b88b..8189b34b 100644 --- a/meta-v1000/conf/layer.conf +++ b/meta-v1000/conf/layer.conf @@ -8,5 +8,6 @@ BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ BBFILE_COLLECTIONS += "v1000" BBFILE_PATTERN_v1000 = "^${LAYERDIR}/" BBFILE_PRIORITY_v1000 = "14" +LAYERSERIES_COMPAT_v1000 = "sumo" LAYERDEPENDS_v1000 = "amd openembedded-layer" diff --git a/meta-v1000/conf/local.conf.append.v1000 b/meta-v1000/conf/local.conf.append.v1000 index bac98044..4c5658ec 100644 --- a/meta-v1000/conf/local.conf.append.v1000 +++ b/meta-v1000/conf/local.conf.append.v1000 @@ -23,7 +23,7 @@ # or software. INCLUDE_MPV ??= "no" -COMMERCIAL_LIC_FLAGS_MPV = "commercial_ffmpeg commercial_x264" +COMMERCIAL_LIC_FLAGS_MPV = "commercial_mpv commercial_ffmpeg commercial_x264" LICENSE_FLAGS_WHITELIST_append = "${@' ${COMMERCIAL_LIC_FLAGS_MPV}' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}" CORE_IMAGE_EXTRA_INSTALL_append = "${@' mpv' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}" diff --git a/meta-v1000/conf/machine/v1000.conf b/meta-v1000/conf/machine/v1000.conf index 0bdbbe33..e5c24dff 100644 --- a/meta-v1000/conf/machine/v1000.conf +++ b/meta-v1000/conf/machine/v1000.conf @@ -5,11 +5,14 @@ PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto" PREFERRED_VERSION_linux-yocto ?= "4.9%" -PREFERRED_VERSION_mesa ?= "17.3.0+git%" -PREFERRED_PROVIDER_llvm ?= "llvm6.0" +PREFERRED_VERSION_mesa ?= "17.3.%" require conf/machine/include/tune-v1000.inc +# Add machine specific AMD features and feature pkgs here +EXTRA_IMAGE_FEATURES += "amd-feature-graphics" +VULKAN_PKGS_v1000 = "amdvlk glslang spirv-tools vulkan-loader-layers vulkan-tools vulkan-samples" + include conf/machine/include/amd-common-configurations.inc include conf/machine/include/amd-customer-configurations.inc diff --git a/meta-v1000/recipes-core/llvm/files/0001-CrossCompile.cmake-adjust-build-for-OE.patch b/meta-v1000/recipes-core/llvm/files/0001-CrossCompile.cmake-adjust-build-for-OE.patch deleted file mode 100644 index bf03ec2f..00000000 --- a/meta-v1000/recipes-core/llvm/files/0001-CrossCompile.cmake-adjust-build-for-OE.patch +++ /dev/null @@ -1,44 +0,0 @@ -From eb27ad28d5171770d27415ace95f4c91f15828bf Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Wed, 21 Dec 2016 14:32:50 +0500 -Subject: [PATCH] CrossCompile.cmake: adjust build for OE - -CMake picks up its values from these environment variables -in case of native builds and in OE we set these to target -tools which will be incorrect in this case. -We specifically need to strip the BUILD_CC variable -before setting CC through it because OE tends to -add a space which isn't liked too much by cmake. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - cmake/modules/CrossCompile.cmake | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/cmake/modules/CrossCompile.cmake b/cmake/modules/CrossCompile.cmake -index 9c598a6..cf76fd6 100644 ---- a/cmake/modules/CrossCompile.cmake -+++ b/cmake/modules/CrossCompile.cmake -@@ -4,6 +4,19 @@ function(llvm_create_cross_target_internal target_name toolchain buildtype) - set(LLVM_${target_name}_BUILD "${CMAKE_BINARY_DIR}/${target_name}") - set(LLVM_${target_name}_BUILD ${LLVM_${target_name}_BUILD} PARENT_SCOPE) - message(STATUS "Setting native build dir to " ${LLVM_${target_name}_BUILD}) -+ string(STRIP $ENV{BUILD_CC} build_cc) -+ set(ENV{AR} $ENV{BUILD_AR}) -+ set(ENV{ASM} ${build_cc}) -+ set(ENV{ASMFLAGS} $ENV{BUILD_CFLAGS}) -+ set(ENV{CC} ${build_cc}) -+ set(ENV{CFLAGS} $ENV{BUILD_CFLAGS}) -+ set(ENV{CXX} $ENV{BUILD_CXX}) -+ set(ENV{CXXFLAGS} $ENV{BUILD_CXXFLAGS}) -+ set(ENV{CPP} $ENV{BUILD_CPP}) -+ set(ENV{CPPFLAGS} $ENV{BUILD_CPPFLAGS}) -+ set(ENV{NM} $ENV{BUILD_NM}) -+ set(ENV{RANLIB} $ENV{BUILD_RANLIB}) -+ set(ENV{LDFLAGS} $ENV{BUILD_LDFLAGS}) - endif(NOT DEFINED LLVM_${target_name}_BUILD) - - if (EXISTS ${LLVM_MAIN_SRC_DIR}/cmake/platforms/${toolchain}.cmake) --- -1.9.1 - diff --git a/meta-v1000/recipes-core/llvm/files/0002-CrossCompile.cmake-use-target-BuildVariables-include.patch b/meta-v1000/recipes-core/llvm/files/0002-CrossCompile.cmake-use-target-BuildVariables-include.patch deleted file mode 100644 index 5ed00757..00000000 --- a/meta-v1000/recipes-core/llvm/files/0002-CrossCompile.cmake-use-target-BuildVariables-include.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 489b229104c76651ff36fc5639384cf9dc6b8d7d Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Fri, 23 Dec 2016 03:19:18 +0500 -Subject: [PATCH] CrossCompile.cmake: use target BuildVariables include for - host - -This is primarily OE specific where we'd like to report -the target build variables when checked through host -llvm-config because that is used for configuring -projects depending on LLVM. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - cmake/modules/CrossCompile.cmake | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/cmake/modules/CrossCompile.cmake b/cmake/modules/CrossCompile.cmake -index 9c598a6..173aefd 100644 ---- a/cmake/modules/CrossCompile.cmake -+++ b/cmake/modules/CrossCompile.cmake -@@ -22,7 +22,8 @@ function(llvm_create_cross_target_internal target_name toolchain buildtype) - -DLLVM_TARGET_IS_CROSSCOMPILE_HOST=TRUE - WORKING_DIRECTORY ${LLVM_${target_name}_BUILD} - DEPENDS ${LLVM_${target_name}_BUILD} -- COMMENT "Configuring ${target_name} LLVM...") -+ COMMENT "Configuring ${target_name} LLVM..." -+ COMMAND "${CMAKE_COMMAND}" "-E" "copy" "${CMAKE_SOURCE_DIR}/../build/tools/llvm-config/BuildVariables.inc" "${CMAKE_SOURCE_DIR}/../build/NATIVE/tools/llvm-config/BuildVariables.inc") - - add_custom_target(CONFIGURE_LLVM_${target_name} - DEPENDS ${LLVM_${target_name}_BUILD}/CMakeCache.txt) --- -1.9.1 - diff --git a/meta-v1000/recipes-core/llvm/files/0003-CMakeLists-don-t-use-a-version-suffix.patch b/meta-v1000/recipes-core/llvm/files/0003-CMakeLists-don-t-use-a-version-suffix.patch deleted file mode 100644 index 860f7fc7..00000000 --- a/meta-v1000/recipes-core/llvm/files/0003-CMakeLists-don-t-use-a-version-suffix.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 83d45faafe24bed9c53937d226d500bba6d41a01 Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Mon, 22 May 2017 12:43:51 +0500 -Subject: [PATCH] CMakeLists: don't use a version suffix - -In OE-Core we do a manual package splitting for llvm -because of various reasons and the splitting does -its job using the filenames under libdir. Using a -version suffix in this scenario breaks up things -for packages that depend on LLVM e.g. mesa. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - CMakeLists.txt | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/CMakeLists.txt b/CMakeLists.txt -index 78e2e016625..605a3551b62 100644 ---- a/CMakeLists.txt -+++ b/CMakeLists.txt -@@ -29,7 +29,7 @@ if(NOT DEFINED LLVM_VERSION_PATCH) - set(LLVM_VERSION_PATCH 0) - endif() - if(NOT DEFINED LLVM_VERSION_SUFFIX) -- set(LLVM_VERSION_SUFFIX svn) -+ set(LLVM_VERSION_SUFFIX "") - endif() - - if (POLICY CMP0048) --- -2.11.1 - diff --git a/meta-v1000/recipes-core/llvm/files/0004-CrossCompile.cmake-strip-sysroot-info-from-build-var.patch b/meta-v1000/recipes-core/llvm/files/0004-CrossCompile.cmake-strip-sysroot-info-from-build-var.patch deleted file mode 100644 index 832cdceb..00000000 --- a/meta-v1000/recipes-core/llvm/files/0004-CrossCompile.cmake-strip-sysroot-info-from-build-var.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 8b668989bc17433ab507ec442b51a1518b593604 Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Thu, 9 Feb 2017 18:15:45 +0500 -Subject: [PATCH] CrossCompile.cmake: strip sysroot info from build variables - -This is to align with the recipe specific sysroot mechanism -which will otherwise break the build for any other package -that utilizes LLVM by specifying the LLVM sysroot on the -compiler/linker commandline rather than that package's -specific sysroot. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - cmake/modules/CrossCompile.cmake | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/cmake/modules/CrossCompile.cmake b/cmake/modules/CrossCompile.cmake -index 6378b7e..9682a98 100644 ---- a/cmake/modules/CrossCompile.cmake -+++ b/cmake/modules/CrossCompile.cmake -@@ -36,7 +36,9 @@ function(llvm_create_cross_target_internal target_name toolchain buildtype) - WORKING_DIRECTORY ${LLVM_${target_name}_BUILD} - DEPENDS ${LLVM_${target_name}_BUILD} - COMMENT "Configuring ${target_name} LLVM..." -- COMMAND "${CMAKE_COMMAND}" "-E" "copy" "${CMAKE_SOURCE_DIR}/../build/tools/llvm-config/BuildVariables.inc" "${CMAKE_SOURCE_DIR}/../build/NATIVE/tools/llvm-config/BuildVariables.inc") -+ COMMAND "${CMAKE_COMMAND}" "-E" "copy" "${CMAKE_SOURCE_DIR}/../build/tools/llvm-config/BuildVariables.inc" "${CMAKE_SOURCE_DIR}/../build/NATIVE/tools/llvm-config/BuildVariables.inc" -+ COMMAND sed -i "'s/\\(.*--sysroot=\\\)[^ ]* \\(.*\\)/\\1 \\2/g'" "${CMAKE_SOURCE_DIR}/../build/NATIVE/tools/llvm-config/BuildVariables.inc" -+ COMMAND sed -i "'s/--sysroot=//g'" "${CMAKE_SOURCE_DIR}/../build/NATIVE/tools/llvm-config/BuildVariables.inc") - - add_custom_target(CONFIGURE_LLVM_${target_name} - DEPENDS ${LLVM_${target_name}_BUILD}/CMakeCache.txt) --- -1.9.1 - diff --git a/meta-v1000/recipes-core/llvm/llvm6.0_6.0.bb b/meta-v1000/recipes-core/llvm/llvm6.0_6.0.bb deleted file mode 100644 index d7dbfdb8..00000000 --- a/meta-v1000/recipes-core/llvm/llvm6.0_6.0.bb +++ /dev/null @@ -1,163 +0,0 @@ -DESCRIPTION = "The Low Level Virtual Machine" -HOMEPAGE = "http://llvm.org" - -# 3-clause BSD-like -# University of Illinois/NCSA Open Source License -LICENSE = "NCSA" -LIC_FILES_CHKSUM = "file://LICENSE.TXT;md5=e825e017edc35cfd58e26116e5251771" - -DEPENDS = "libffi libxml2 libxml2-native llvm-common zlib ninja-native" -RDEPENDS_${PN} += "ncurses-terminfo" - -inherit perlnative pythonnative cmake - -PROVIDES += "llvm" - -LLVM_RELEASE = "${PV}" -LLVM_DIR = "llvm${LLVM_RELEASE}" - -SRCREV = "99469895318be8283586e314b145d1552cb687c6" -PV = "6.0" -PATCH_VERSION = "0" -SRC_URI = "git://llvm.org/git/llvm.git;branch=master;protocol=http \ - file://0001-CrossCompile.cmake-adjust-build-for-OE.patch \ - file://0002-CrossCompile.cmake-use-target-BuildVariables-include.patch \ - file://0003-CMakeLists-don-t-use-a-version-suffix.patch \ - file://0004-CrossCompile.cmake-strip-sysroot-info-from-build-var.patch \ -" -S = "${WORKDIR}/git" - -LLVM_INSTALL_DIR = "${WORKDIR}/llvm-install" - -EXTRA_OECMAKE += "-DLLVM_ENABLE_ASSERTIONS=OFF \ - -DLLVM_ENABLE_EXPENSIVE_CHECKS=OFF \ - -DLLVM_BINDINGS_LIST="" \ - -DLLVM_LINK_LLVM_DYLIB=ON \ - -DLLVM_ENABLE_FFI=ON \ - -DLLVM_OPTIMIZED_TABLEGEN=ON \ - -DLLVM_TARGETS_TO_BUILD="AMDGPU;X86"" - -do_configure() { - # Fix paths in llvm-config - sed -i "s|sys::path::parent_path(CurrentPath))\.str()|sys::path::parent_path(sys::path::parent_path(CurrentPath))).str()|g" ${S}/tools/llvm-config/llvm-config.cpp - sed -ri "s#/(bin|include|lib)(/?\")#/\1/${LLVM_DIR}\2#g" ${S}/tools/llvm-config/llvm-config.cpp - sed -ri "s#lib/${LLVM_DIR}#${baselib}/${LLVM_DIR}#g" ${S}/tools/llvm-config/llvm-config.cpp - cd ${B} - cmake \ - -G Ninja \ - ${S} \ - -DCMAKE_INSTALL_PREFIX:PATH=/usr \ - -DCMAKE_INSTALL_BINDIR:PATH=bin \ - -DCMAKE_INSTALL_SBINDIR:PATH=sbin \ - -DCMAKE_INSTALL_LIBEXECDIR:PATH=libexec \ - -DCMAKE_INSTALL_SYSCONFDIR:PATH=/etc \ - -DCMAKE_INSTALL_SHAREDSTATEDIR:PATH=../com \ - -DCMAKE_INSTALL_LOCALSTATEDIR:PATH=/var \ - -DCMAKE_INSTALL_LIBDIR:PATH=lib64 \ - -DCMAKE_INSTALL_INCLUDEDIR:PATH=include \ - -DCMAKE_INSTALL_DATAROOTDIR:PATH=share \ - -DCMAKE_INSTALL_SO_NO_EXE=0 \ - -DCMAKE_TOOLCHAIN_FILE=${WORKDIR}/toolchain.cmake \ - -DCMAKE_VERBOSE_MAKEFILE=1 \ - -DCMAKE_NO_SYSTEM_FROM_IMPORTED=1 \ - ${EXTRA_OECMAKE} -} - -do_compile() { - cd ${B} - NINJA_STATUS="[%p] " ninja -v -} - -do_install() { - DESTDIR=${LLVM_INSTALL_DIR} ninja -v install - - install ${B}/NATIVE/bin/llvm-config ${LLVM_INSTALL_DIR}/llvm-config-host - - install -d ${D}${bindir}/${LLVM_DIR} - cp -r ${LLVM_INSTALL_DIR}${bindir}/* ${D}${bindir}/${LLVM_DIR}/ - - install -d ${D}${includedir}/${LLVM_DIR} - cp -r ${LLVM_INSTALL_DIR}${includedir}/* ${D}${includedir}/${LLVM_DIR}/ - - install -d ${D}${libdir}/${LLVM_DIR} - - # The LLVM sources have "/lib" embedded and so we cannot completely rely on the ${libdir} variable - if [ -d ${LLVM_INSTALL_DIR}${libdir}/ ]; then - cp -r ${LLVM_INSTALL_DIR}${libdir}/* ${D}${libdir}/${LLVM_DIR}/ - elif [ -d ${LLVM_INSTALL_DIR}${prefix}/lib ]; then - cp -r ${LLVM_INSTALL_DIR}${prefix}/lib/* ${D}${libdir}/${LLVM_DIR}/ - elif [ -d ${LLVM_INSTALL_DIR}${prefix}/lib64 ]; then - cp -r ${LLVM_INSTALL_DIR}${prefix}/lib64/* ${D}${libdir}/${LLVM_DIR}/ - fi - - # Remove unnecessary cmake files - rm -rf ${D}${libdir}/${LLVM_DIR}/cmake - - ln -s ${LLVM_DIR}/libLLVM-${PV}${SOLIBSDEV} ${D}${libdir}/libLLVM-${PV}${SOLIBSDEV} - - # We'll have to delete libLLVM.so and libLTO.so due to multiple reasons... - rm -rf ${D}${libdir}/${LLVM_DIR}/libLLVM.so - rm -rf ${D}${libdir}/${LLVM_DIR}/libLTO.so -} - -SYSROOT_PREPROCESS_FUNCS += "llvm_sysroot_preprocess" - -llvm_sysroot_preprocess() { - install -d ${SYSROOT_DESTDIR}${bindir_crossscripts} - cp ${LLVM_INSTALL_DIR}/llvm-config-host ${SYSROOT_DESTDIR}${bindir_crossscripts}/llvm-config${PV} -} - -PACKAGES += "${PN}-bugpointpasses ${PN}-llvmhello" -ALLOW_EMPTY_${PN} = "1" -ALLOW_EMPTY_${PN}-staticdev = "1" -FILES_${PN} = "" -FILES_${PN}-staticdev = "" -FILES_${PN}-dbg = " \ - ${bindir}/${LLVM_DIR}/.debug \ - ${libdir}/${LLVM_DIR}/.debug/BugpointPasses.so \ - ${libdir}/${LLVM_DIR}/.debug/LLVMHello.so \ - ${libdir}/${LLVM_DIR}/.debug/libLTO.so* \ - ${libdir}/${LLVM_DIR}/.debug/llvm-config \ - /usr/src/debug \ -" - -FILES_${PN}-dev = " \ - ${bindir}/${LLVM_DIR} \ - ${includedir}/${LLVM_DIR} \ - ${libdir}/${LLVM_DIR}/llvm-config \ -" -RRECOMMENDS_${PN}-dev += "${PN}-bugpointpasses ${PN}-llvmhello" - -FILES_${PN}-bugpointpasses = "\ - ${libdir}/${LLVM_DIR}/BugpointPasses.so \ -" - -FILES_${PN}-llvmhello = "\ - ${libdir}/${LLVM_DIR}/LLVMHello.so \ -" - -FILES_${PN} += "\ - ${libdir}/${LLVM_DIR}/libLTO.so.* \ -" - -PACKAGES_DYNAMIC = "^libllvm${LLVM_RELEASE}-.*$" -NOAUTOPACKAGEDEBUG = "1" - -INSANE_SKIP_${MLPREFIX}libllvm${LLVM_RELEASE}-llvm-${LLVM_RELEASE}.${PATCH_VERSION} += "dev-so" -INSANE_SKIP_${MLPREFIX}libllvm${LLVM_RELEASE}-llvm-${LLVM_RELEASE} += "dev-so" -INSANE_SKIP_${MLPREFIX}libllvm${LLVM_RELEASE}-llvm += "dev-so" - -python llvm_populate_packages() { - libdir = bb.data.expand('${libdir}', d) - libllvm_libdir = bb.data.expand('${libdir}/${LLVM_DIR}', d) - split_dbg_packages = do_split_packages(d, libllvm_libdir+'/.debug', '^lib(.*)\.so$', 'libllvm${LLVM_RELEASE}-%s-dbg', 'Split debug package for %s', allow_dirs=True) - split_packages = do_split_packages(d, libdir, '^lib(.*)\.so$', 'libllvm${LLVM_RELEASE}-%s', 'Split package for %s', allow_dirs=True, allow_links=True, recursive=True) - split_staticdev_packages = do_split_packages(d, libllvm_libdir, '^lib(.*)\.a$', 'libllvm${LLVM_RELEASE}-%s-staticdev', 'Split staticdev package for %s', allow_dirs=True) - if split_packages: - pn = d.getVar('PN', True) - d.appendVar('RDEPENDS_' + pn, ' '+' '.join(split_packages)) - d.appendVar('RDEPENDS_' + pn + '-dbg', ' '+' '.join(split_dbg_packages)) - d.appendVar('RDEPENDS_' + pn + '-staticdev', ' '+' '.join(split_staticdev_packages)) -} - -PACKAGESPLITFUNCS_prepend = "llvm_populate_packages " diff --git a/meta-v1000/recipes-core/llvm/llvm_git.bbappend b/meta-v1000/recipes-core/llvm/llvm_git.bbappend new file mode 100644 index 00000000..a46a7c3f --- /dev/null +++ b/meta-v1000/recipes-core/llvm/llvm_git.bbappend @@ -0,0 +1,8 @@ +SRCREV = "089d4c0c490687db6c75f1d074e99c4d42936a50" +PV = "6.0" +PATCH_VERSION = "0" + +DEPENDS += "libxml2" + +SRC_URI_remove = "git://github.com/llvm-mirror/llvm.git;branch=release_50;protocol=http" +SRC_URI_append = " git://github.com/llvm-mirror/llvm.git;branch=release_60;protocol=http" diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0001-amdgpu-Implement-SVM-v3.patch b/meta-v1000/recipes-graphics/drm/libdrm/0001-amdgpu-Implement-SVM-v3.patch index 8fa6e851..a8f55071 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0001-amdgpu-Implement-SVM-v3.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0001-amdgpu-Implement-SVM-v3.patch @@ -33,17 +33,18 @@ Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - amdgpu/amdgpu.h | 50 +++++++++++++++- + amdgpu/amdgpu.h | 50 ++++++++++++++- amdgpu/amdgpu_internal.h | 3 + - amdgpu/amdgpu_vamgr.c | 145 ++++++++++++++++++++++++++++++++++++++++++++++- - 3 files changed, 193 insertions(+), 5 deletions(-) + amdgpu/amdgpu_vamgr.c | 179 ++++++++++++++++++++++++++++++++++++++++++++++++------ + 3 files changed, 212 insertions(+), 20 deletions(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 238b1aa..f63abdc 100644 +index 36f9105..e4f73c9 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -91,7 +91,9 @@ enum amdgpu_bo_handle_type { +@@ -91,7 +91,10 @@ enum amdgpu_bo_handle_type { enum amdgpu_gpu_va_range { /** Allocate from "normal"/general range */ @@ -51,18 +52,11 @@ index 238b1aa..f63abdc 100644 + amdgpu_gpu_va_range_general = 0, + /** Allocate from svm range */ + amdgpu_gpu_va_range_svm = 1 ++ }; - /*--------------------------------------------------------------------------*/ -@@ -1249,7 +1251,6 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, - * <0 - Negative POSIX Error code - * - */ -- - int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, - amdgpu_bo_handle bo, - uint64_t offset, -@@ -1259,6 +1260,51 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, + enum amdgpu_sw_info { +@@ -1294,6 +1297,51 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, uint32_t ops); /** @@ -115,78 +109,110 @@ index 238b1aa..f63abdc 100644 * * \param sem - \c [out] semaphore handle diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index e68246b..3577f64 100644 +index 99b8ce0..13a7359 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h -@@ -55,6 +55,7 @@ struct amdgpu_bo_va_hole { +@@ -49,6 +49,7 @@ struct amdgpu_bo_va_hole { + }; + struct amdgpu_bo_va_mgr { - /* the start virtual address */ - uint64_t va_offset; + uint64_t va_min; uint64_t va_max; struct list_head va_holes; pthread_mutex_t bo_va_mutex; -@@ -96,6 +97,8 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr vamgr_32; +@@ -87,6 +88,8 @@ struct amdgpu_device { + struct amdgpu_bo_va_mgr vamgr_high; + /** The VA manager for the 32bit high address space */ + struct amdgpu_bo_va_mgr vamgr_high_32; + /** The VA manager for SVM address space */ + struct amdgpu_bo_va_mgr *vamgr_svm; }; struct amdgpu_bo { diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 2b1388e..2a9f28a 100644 +index 1de9f95..95483cb 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c -@@ -36,18 +36,30 @@ - int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) +@@ -33,12 +33,23 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, + enum amdgpu_gpu_va_range type, + uint64_t *start, uint64_t *end) { -- if (type == amdgpu_gpu_va_range_general) { +- if (type != amdgpu_gpu_va_range_general) +- return -EINVAL; +- +- *start = dev->dev_info.virtual_address_offset; +- *end = dev->dev_info.virtual_address_max; +- return 0; + switch (type) { -+ case amdgpu_gpu_va_range_general: - *start = dev->dev_info.virtual_address_offset; - *end = dev->dev_info.virtual_address_max; - return 0; -+ case amdgpu_gpu_va_range_svm: -+ if (dev->vamgr_svm) { -+ *start = dev->vamgr_svm->va_min; -+ *end = dev->vamgr_svm->va_max; -+ } else { -+ *start = 0ULL; -+ *end = 0ULL; -+ } -+ return 0; -+ default: -+ return -EINVAL; - } -- return -EINVAL; ++ case amdgpu_gpu_va_range_general: ++ *start = dev->dev_info.virtual_address_offset; ++ *end = dev->dev_info.virtual_address_max; ++ return 0; ++ case amdgpu_gpu_va_range_svm: ++ if (dev->vamgr_svm) { ++ *start = dev->vamgr_svm->va_min; ++ *end = dev->vamgr_svm->va_max; ++ } else { ++ *start = 0ULL; ++ *end = 0ULL; ++ } ++ return 0; ++ default: ++ return -EINVAL; ++ } } drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, - uint64_t max, uint64_t alignment) - { - mgr->va_offset = start; -+ mgr->va_min = start; +@@ -47,6 +58,7 @@ drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, + struct amdgpu_bo_va_hole *n; + mgr->va_max = max; ++ mgr->va_min = start; mgr->va_alignment = alignment; -@@ -235,7 +247,12 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, + list_inithead(&mgr->va_holes); +@@ -197,20 +209,27 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, { struct amdgpu_bo_va_mgr *vamgr; -- if (flags & AMDGPU_VA_RANGE_32_BIT) +- /* Clear the flag when the high VA manager is not initialized */ +- if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max) +- flags &= ~AMDGPU_VA_RANGE_HIGH; + if (amdgpu_gpu_va_range_svm == va_range_type) { + vamgr = dev->vamgr_svm; + if (!vamgr) + return -EINVAL; + } -+ else if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = &dev->vamgr_32; - else - vamgr = &dev->vamgr; -@@ -285,3 +302,125 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) ++ else { ++ /* Clear the flag when the high VA manager is not initialized */ ++ if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max) ++ flags &= ~AMDGPU_VA_RANGE_HIGH; + +- if (flags & AMDGPU_VA_RANGE_HIGH) { +- if (flags & AMDGPU_VA_RANGE_32_BIT) +- vamgr = &dev->vamgr_high_32; +- else +- vamgr = &dev->vamgr_high; +- } else { +- if (flags & AMDGPU_VA_RANGE_32_BIT) +- vamgr = &dev->vamgr_32; +- else +- vamgr = &dev->vamgr; ++ if (flags & AMDGPU_VA_RANGE_HIGH) { ++ if (flags & AMDGPU_VA_RANGE_32_BIT) ++ vamgr = &dev->vamgr_high_32; ++ else ++ vamgr = &dev->vamgr_high; ++ } else { ++ if (flags & AMDGPU_VA_RANGE_32_BIT) ++ vamgr = &dev->vamgr_32; ++ else ++ vamgr = &dev->vamgr; ++ } + } + + va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); +@@ -261,3 +280,125 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) free(va_range_handle); return 0; } @@ -314,4 +340,3 @@ index 2b1388e..2a9f28a 100644 +} -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0002-amdgpu-SVM-test-v3.patch b/meta-v1000/recipes-graphics/drm/libdrm/0002-amdgpu-SVM-test-v3.patch index 8f8c92d8..5b541e96 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0002-amdgpu-SVM-test-v3.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0002-amdgpu-SVM-test-v3.patch @@ -26,26 +26,27 @@ Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - tests/amdgpu/basic_tests.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ + tests/amdgpu/basic_tests.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 8d5844b..b10aeb0 100644 +index 1adbddd..0a3a89d 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c -@@ -49,6 +49,7 @@ static void amdgpu_command_submission_multi_fence(void); - static void amdgpu_command_submission_sdma(void); - static void amdgpu_userptr_test(void); +@@ -48,6 +48,7 @@ static void amdgpu_userptr_test(void); static void amdgpu_semaphore_test(void); + static void amdgpu_sync_dependency_test(void); + static void amdgpu_bo_eviction_test(void); +static void amdgpu_svm_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); -@@ -63,9 +64,11 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence }, +@@ -69,9 +70,11 @@ CU_TestInfo basic_tests[] = { { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, { "SW semaphore Test", amdgpu_semaphore_test }, + { "Sync dependency Test", amdgpu_sync_dependency_test }, + { "SVM Test", amdgpu_svm_test }, CU_TEST_INFO_NULL, }; @@ -54,9 +55,9 @@ index 8d5844b..b10aeb0 100644 #define SDMA_PKT_HEADER_op_offset 0 #define SDMA_PKT_HEADER_op_mask 0x000000FF #define SDMA_PKT_HEADER_op_shift 0 -@@ -1329,3 +1332,54 @@ static void amdgpu_userptr_test(void) - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); +@@ -1822,3 +1825,54 @@ static void amdgpu_sync_dependency_test(void) + + free(ibs_request.dependencies); } + +static void amdgpu_svm_test(void) @@ -111,4 +112,3 @@ index 8d5844b..b10aeb0 100644 +} -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch b/meta-v1000/recipes-graphics/drm/libdrm/0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch index 7768230b..d7b9fb90 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch @@ -37,19 +37,20 @@ Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu_device.c | 2 ++ amdgpu/amdgpu_internal.h | 8 ++++-- - amdgpu/amdgpu_vamgr.c | 75 +++++++++++++++++++++++++++++++++++------------- + amdgpu/amdgpu_vamgr.c | 75 ++++++++++++++++++++++++++++++++++++++++--------------- 3 files changed, 63 insertions(+), 22 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index 9a238d9..74d6993 100644 +index d81efcf..6d5f632 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c -@@ -279,6 +279,8 @@ int amdgpu_device_initialize(int fd, - __func__, r); - } +@@ -284,6 +284,8 @@ int amdgpu_device_initialize(int fd, + + amdgpu_parse_asic_ids(dev); + dev->svm_allocated = false; + @@ -57,10 +58,10 @@ index 9a238d9..74d6993 100644 *minor_version = dev->minor_version; *device_handle = dev; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 3577f64..3251ff0 100644 +index 13a7359..4444e00 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h -@@ -60,6 +60,10 @@ struct amdgpu_bo_va_mgr { +@@ -54,6 +54,10 @@ struct amdgpu_bo_va_mgr { struct list_head va_holes; pthread_mutex_t bo_va_mutex; uint32_t va_alignment; @@ -71,10 +72,10 @@ index 3577f64..3251ff0 100644 }; struct amdgpu_va { -@@ -97,8 +101,8 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr vamgr_32; +@@ -88,8 +92,8 @@ struct amdgpu_device { + struct amdgpu_bo_va_mgr vamgr_high; + /** The VA manager for the 32bit high address space */ + struct amdgpu_bo_va_mgr vamgr_high_32; - /** The VA manager for SVM address space */ - struct amdgpu_bo_va_mgr *vamgr_svm; + /** svm range allocated */ @@ -83,10 +84,10 @@ index 3577f64..3251ff0 100644 struct amdgpu_bo { diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 2a9f28a..54711ee 100644 +index 95483cb..4a0431b 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c -@@ -33,6 +33,9 @@ +@@ -29,6 +29,9 @@ #include "amdgpu_internal.h" #include "util_math.h" @@ -94,22 +95,22 @@ index 2a9f28a..54711ee 100644 +static struct amdgpu_bo_va_mgr vamgr_svm; + int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) - { -@@ -42,9 +45,9 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, - *end = dev->dev_info.virtual_address_max; - return 0; - case amdgpu_gpu_va_range_svm: -- if (dev->vamgr_svm) { -- *start = dev->vamgr_svm->va_min; -- *end = dev->vamgr_svm->va_max; -+ if (vamgr_svm.valid) { -+ *start = vamgr_svm.va_min; -+ *end = vamgr_svm.va_max; - } else { - *start = 0ULL; - *end = 0ULL; -@@ -248,8 +251,8 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, + enum amdgpu_gpu_va_range type, + uint64_t *start, uint64_t *end) +@@ -39,9 +42,9 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, + *end = dev->dev_info.virtual_address_max; + return 0; + case amdgpu_gpu_va_range_svm: +- if (dev->vamgr_svm) { +- *start = dev->vamgr_svm->va_min; +- *end = dev->vamgr_svm->va_max; ++ if (vamgr_svm.valid) { ++ *start = vamgr_svm.va_min; ++ *end = vamgr_svm.va_max; + } else { + *start = 0ULL; + *end = 0ULL; +@@ -210,8 +213,8 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, struct amdgpu_bo_va_mgr *vamgr; if (amdgpu_gpu_va_range_svm == va_range_type) { @@ -119,8 +120,8 @@ index 2a9f28a..54711ee 100644 + if (!vamgr->valid) return -EINVAL; } - else if (flags & AMDGPU_VA_RANGE_32_BIT) -@@ -329,6 +332,27 @@ int amdgpu_svm_init(amdgpu_device_handle dev) + else { +@@ -307,6 +310,27 @@ int amdgpu_svm_init(amdgpu_device_handle dev) /* return value of this function. */ int ret; @@ -148,7 +149,7 @@ index 2a9f28a..54711ee 100644 ret = amdgpu_va_range_query(dev, amdgpu_gpu_va_range_general, &start, &end); if (ret) return ret; -@@ -356,16 +380,9 @@ int amdgpu_svm_init(amdgpu_device_handle dev) +@@ -334,16 +358,9 @@ int amdgpu_svm_init(amdgpu_device_handle dev) cpu_address = mmap((void *)start, size, PROT_NONE, MAP_PRIVATE | MAP_NORESERVE | MAP_ANONYMOUS, -1, 0); if (cpu_address == (void *)start) { @@ -163,12 +164,12 @@ index 2a9f28a..54711ee 100644 - ret = 0; - } + amdgpu_vamgr_init(&vamgr_svm, start, start + size, -+ dev->dev_info.virtual_address_alignment); ++ dev->dev_info.virtual_address_alignment); + ret = 0; break; } else if (cpu_address == MAP_FAILED) { /* Probably there is no space in this process's address space for -@@ -382,17 +399,35 @@ int amdgpu_svm_init(amdgpu_device_handle dev) +@@ -360,17 +377,35 @@ int amdgpu_svm_init(amdgpu_device_handle dev) } } @@ -188,7 +189,7 @@ index 2a9f28a..54711ee 100644 - dev->vamgr_svm->va_max - dev->vamgr_svm->va_min); - free(dev->vamgr_svm); + if (dev->svm_allocated) { -+ amdgpu_vamgr_free_va(&dev->vamgr, vamgr_svm.va_min, ++ amdgpu_vamgr_free_va(&dev->vamgr, vamgr_svm.va_min, + vamgr_svm.va_max - vamgr_svm.va_min); + dev->svm_allocated = false; + @@ -196,7 +197,7 @@ index 2a9f28a..54711ee 100644 + /* This is the last device referencing SVM. */ + amdgpu_vamgr_deinit(&vamgr_svm); + munmap((void *)vamgr_svm.va_min, -+ vamgr_svm.va_max - vamgr_svm.va_min); ++ vamgr_svm.va_max - vamgr_svm.va_min); + vamgr_svm.va_max = 0; + } } @@ -211,4 +212,3 @@ index 2a9f28a..54711ee 100644 int amdgpu_svm_commit(amdgpu_va_handle va_range_handle, -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch b/meta-v1000/recipes-graphics/drm/libdrm/0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch index bd48fd49..31166778 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch @@ -34,31 +34,33 @@ Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Change-Id: I481155784e7ebcfda3bfc7e68932a33d01d6843a + +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- tests/amdgpu/basic_tests.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index b10aeb0..7dfc0e2 100644 +index 0a3a89d..96e98e3 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c -@@ -50,6 +50,7 @@ static void amdgpu_command_submission_sdma(void); - static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); +@@ -49,6 +49,7 @@ static void amdgpu_semaphore_test(void); + static void amdgpu_sync_dependency_test(void); + static void amdgpu_bo_eviction_test(void); static void amdgpu_svm_test(void); +static void amdgpu_multi_svm_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); -@@ -65,6 +66,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, +@@ -71,6 +72,7 @@ CU_TestInfo basic_tests[] = { { "SW semaphore Test", amdgpu_semaphore_test }, + { "Sync dependency Test", amdgpu_sync_dependency_test }, { "SVM Test", amdgpu_svm_test }, + { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, CU_TEST_INFO_NULL, }; #define BUFFER_SIZE (8 * 1024) -@@ -1383,3 +1385,71 @@ static void amdgpu_svm_test(void) +@@ -1876,3 +1878,71 @@ static void amdgpu_svm_test(void) amdgpu_svm_deinit(device_handle); } @@ -132,4 +134,3 @@ index b10aeb0..7dfc0e2 100644 +} -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0005-amdgpu-add-query-for-aperture-va-range.patch b/meta-v1000/recipes-graphics/drm/libdrm/0005-amdgpu-add-query-for-aperture-va-range.patch index a8a4266c..dbce268d 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0005-amdgpu-add-query-for-aperture-va-range.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0005-amdgpu-add-query-for-aperture-va-range.patch @@ -8,6 +8,7 @@ Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 30 ++++++++++++++++++++++++++++++ amdgpu/amdgpu_gpu_info.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ @@ -15,10 +16,10 @@ Signed-off-by: Avinash M N <avimn@amd.com> 3 files changed, 93 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index f63abdc..f0eecb7 100644 +index e4f73c9..d2657fe 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -1106,6 +1106,36 @@ int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, +@@ -1141,6 +1141,36 @@ int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, unsigned size, void *value); /** @@ -109,12 +110,12 @@ index 1efffc6..697360b 100644 + end); +} diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index d9aa4a3..51b1d51 100644 +index a023b47..db80956 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -612,6 +612,9 @@ struct drm_amdgpu_cs_chunk_data { - /* Number of VRAM page faults on CPU access. */ +@@ -660,6 +660,9 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E + #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F +/* virtual range */ +#define AMDGPU_INFO_VIRTUAL_RANGE 0x51 @@ -122,7 +123,7 @@ index d9aa4a3..51b1d51 100644 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 -@@ -668,6 +671,11 @@ struct drm_amdgpu_info { +@@ -716,6 +719,11 @@ struct drm_amdgpu_info { __u32 flags; } read_mmr_reg; @@ -134,7 +135,7 @@ index d9aa4a3..51b1d51 100644 struct drm_amdgpu_query_fw query_fw; struct { -@@ -872,6 +880,16 @@ struct drm_amdgpu_info_vce_clock_table { +@@ -927,6 +935,16 @@ struct drm_amdgpu_info_vce_clock_table { #define AMDGPU_FAMILY_AI 141 /* Vega10 */ #define AMDGPU_FAMILY_RV 142 /* Raven */ @@ -153,4 +154,3 @@ index d9aa4a3..51b1d51 100644 #endif -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch index 09f73e0a..2e38cbce 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch @@ -19,25 +19,25 @@ Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 51b1d51..b3ce535 100644 +index 20de8ca..940bee8 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -88,6 +88,10 @@ extern "C" { - /* Flag that allocating the BO should use linear VRAM */ - #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) +@@ -96,6 +96,10 @@ extern "C" { + /* Flag that BO sharing will be explicitly synchronized */ + #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) +/* Hybrid specific */ +/* Flag that the memory allocation should be pinned */ -+#define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) ++#define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) + struct drm_amdgpu_gem_create_in { /** the requested memory size */ __u64 bo_size; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch index 9b4e7a0a..f9ee1531 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch @@ -10,23 +10,23 @@ update GEM flag bit for 64-bit extension Change-Id: Ie291d391d0f68e7ff9028b3713808c38002d84c6 Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Flora Cui <Flora.Cui@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index b3ce535..afacd62 100644 +index 940bee8..191c5c2 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -89,6 +89,8 @@ extern "C" { - #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) +@@ -97,6 +97,8 @@ extern "C" { + #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) /* Hybrid specific */ +/* Flag that the memory should be in SPARSE resource */ -+#define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) ++#define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) /* Flag that the memory allocation should be pinned */ - #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) + #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch index c2907a39..907bbcac 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch @@ -17,6 +17,7 @@ Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 20 ++++++++++++++++++++ amdgpu/amdgpu_gpu_info.c | 7 +++++++ @@ -24,7 +25,7 @@ Signed-off-by: Avinash M N <avimn@amd.com> 3 files changed, 39 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index f0eecb7..7669530 100644 +index d2657fe..10f458a 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -42,6 +42,7 @@ extern "C" { @@ -47,7 +48,7 @@ index f0eecb7..7669530 100644 /*--------------------------------------------------------------------------*/ /* ----------------------------- Enums ------------------------------------ */ /*--------------------------------------------------------------------------*/ -@@ -1075,6 +1081,20 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, +@@ -1093,6 +1099,20 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, unsigned size, void *value); /** @@ -65,9 +66,9 @@ index f0eecb7..7669530 100644 + struct drm_amdgpu_capability *cap); + +/** - * Query information about GDS + * Query hardware or driver information. * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * The return size is query-specific and depends on the "info_id" parameter. diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c index 697360b..dddf6e7 100644 --- a/amdgpu/amdgpu_gpu_info.c @@ -87,19 +88,19 @@ index 697360b..dddf6e7 100644 int32_t *result) { diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index afacd62..e76212b 100644 +index 4465eb4..616683e 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -618,6 +618,8 @@ struct drm_amdgpu_cs_chunk_data { - /* Number of VRAM page faults on CPU access. */ +@@ -666,6 +666,8 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E + #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F +/* gpu capability */ +#define AMDGPU_INFO_CAPABILITY 0x50 /* virtual range */ #define AMDGPU_INFO_VIRTUAL_RANGE 0x51 -@@ -896,6 +898,16 @@ struct drm_amdgpu_virtual_range { +@@ -951,6 +953,16 @@ struct drm_amdgpu_virtual_range { uint64_t end; }; @@ -118,4 +119,3 @@ index afacd62..e76212b 100644 #endif -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch b/meta-v1000/recipes-graphics/drm/libdrm/0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch index 19c9b676..291bf640 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch @@ -1,7 +1,7 @@ -From 3d9a1994c39c51c2d4471e1ae4c93ce421f9dbab Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 26 Nov 2015 17:01:07 +0800 -Subject: [PATCH 09/39] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface +From aab24091f243d7b73ad4252365d09254ad393106 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Mon, 18 Dec 2017 15:18:51 +0500 +Subject: [PATCH] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -13,6 +13,7 @@ Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Awais Belal <awais_belal@mentor.com> --- amdgpu/amdgpu.h | 24 ++++++++++++++++++++++++ amdgpu/amdgpu_bo.c | 37 +++++++++++++++++++++++++++++++++++++ @@ -20,7 +21,7 @@ Signed-off-by: Avinash M N <avimn@amd.com> 3 files changed, 75 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 7669530..755d746 100644 +index 8247f82a..0a54855b 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -677,6 +677,30 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, @@ -55,10 +56,10 @@ index 7669530..755d746 100644 * * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 5ac456b..9a110a0 100644 +index 3853fd03..3a8d08af 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -529,6 +529,43 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, +@@ -533,6 +533,43 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, } } @@ -103,28 +104,28 @@ index 5ac456b..9a110a0 100644 void *cpu, uint64_t size, diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index e76212b..1919c28 100644 +index 2563779c..9734e963 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -52,6 +52,8 @@ extern "C" { - #define DRM_AMDGPU_GEM_USERPTR 0x11 - #define DRM_AMDGPU_WAIT_FENCES 0x12 +@@ -54,6 +54,8 @@ extern "C" { #define DRM_AMDGPU_VM 0x13 + #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 + #define DRM_AMDGPU_SCHED 0x15 +/* hybrid specific ioctls */ +#define DRM_AMDGPU_GEM_FIND_BO 0x5f #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -67,6 +69,8 @@ extern "C" { - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) +@@ -71,6 +73,8 @@ extern "C" { #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) + #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) + #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) +/* hybrid specific ioctls */ +#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -237,6 +241,16 @@ struct drm_amdgpu_gem_userptr { +@@ -269,6 +273,16 @@ struct drm_amdgpu_gem_userptr { __u32 handle; }; @@ -142,5 +143,5 @@ index e76212b..1919c28 100644 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 -- -2.7.4 +2.11.1 diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0010-amdgpu-support-alloc-va-from-range-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0010-amdgpu-support-alloc-va-from-range-v2.patch index 84675e1f..55ebb0be 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0010-amdgpu-support-alloc-va-from-range-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0010-amdgpu-support-alloc-va-from-range-v2.patch @@ -15,16 +15,17 @@ Change-Id: I05f24e44863aeffa7bcd735bf787a5328d587044 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: David Mao <david.mao@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - amdgpu/amdgpu.h | 51 ++++++++++++++ - amdgpu/amdgpu_vamgr.c | 179 ++++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 230 insertions(+) + amdgpu/amdgpu.h | 51 +++++++++++++++++ + amdgpu/amdgpu_vamgr.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 203 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 755d746..8bcb808 100644 +index 56a5a0d..9e3ce7f 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -1251,6 +1251,57 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, +@@ -1287,6 +1287,57 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, uint64_t flags); /** @@ -83,11 +84,11 @@ index 755d746..8bcb808 100644 * * diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 54711ee..63124a4 100644 +index 0177bfb..906303b 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c -@@ -169,6 +169,104 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - return offset; +@@ -149,6 +149,77 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, + return AMDGPU_INVALID_VA_ADDRESS; } +static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint64_t size, @@ -157,41 +158,14 @@ index 54711ee..63124a4 100644 + } + } + -+ if (mgr->va_offset > range_max) { -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return AMDGPU_INVALID_VA_ADDRESS; -+ } else if (mgr->va_offset > range_min) { -+ offset = mgr->va_offset; -+ waste = offset % alignment; -+ waste = waste ? alignment - waste : 0; -+ if (offset + waste + size > range_max) { -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return AMDGPU_INVALID_VA_ADDRESS; -+ } -+ } else { -+ offset = mgr->va_offset; -+ waste = range_min % alignment; -+ waste = waste ? alignment - waste : 0; -+ waste += range_min - offset ; -+ } -+ -+ if (waste) { -+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); -+ n->size = waste; -+ n->offset = offset; -+ list_add(&n->list, &mgr->va_holes); -+ } -+ -+ offset += waste; -+ mgr->va_offset = size + offset; + pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; ++ return AMDGPU_INVALID_VA_ADDRESS; +} + - drm_private void + static drm_private void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) { -@@ -294,6 +392,87 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, +@@ -276,6 +347,87 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, return 0; } @@ -281,4 +255,3 @@ index 54711ee..63124a4 100644 if(!va_range_handle || !va_range_handle->address) -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch index 50dfc03b..f5a477f9 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch @@ -12,31 +12,32 @@ move va_range_test above svm_test Change-Id: Ie430345b42da6884d5296f057d4214b2d3f12788 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- tests/amdgpu/basic_tests.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 7dfc0e2..41a702d 100644 +index 96e98e3..0d9a810 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c -@@ -51,6 +51,7 @@ static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); +@@ -50,6 +50,7 @@ static void amdgpu_sync_dependency_test(void); + static void amdgpu_bo_eviction_test(void); static void amdgpu_svm_test(void); static void amdgpu_multi_svm_test(void); +static void amdgpu_va_range_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); -@@ -65,6 +66,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence }, +@@ -71,6 +72,7 @@ CU_TestInfo basic_tests[] = { { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, { "SW semaphore Test", amdgpu_semaphore_test }, + { "Sync dependency Test", amdgpu_sync_dependency_test }, + { "VA range Test", amdgpu_va_range_test}, { "SVM Test", amdgpu_svm_test }, { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, CU_TEST_INFO_NULL, -@@ -1453,3 +1455,55 @@ static void amdgpu_multi_svm_test(void) +@@ -1946,3 +1948,55 @@ static void amdgpu_multi_svm_test(void) amdgpu_svm_deinit(device_handles[0]); } @@ -94,4 +95,3 @@ index 7dfc0e2..41a702d 100644 +} -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch index 2b340bb3..ace4bc1f 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch @@ -14,6 +14,7 @@ Fix memory leak in amdgpu_get_fb_id Change-Id: I336fab1585bbdcf6f789c4bab533e4d1f01842ec Signed-off-by: jqdeng <Emily.Deng@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu-symbol-check | 1 + amdgpu/amdgpu.h | 15 +++++++++++++ @@ -21,29 +22,29 @@ Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> 3 files changed, 68 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index c5b85b5..f5cf9ff 100755 +index 90b7a1d..cf03353 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check -@@ -59,6 +59,7 @@ amdgpu_read_mm_registers - amdgpu_va_range_alloc - amdgpu_va_range_free +@@ -70,6 +70,7 @@ amdgpu_va_range_free amdgpu_va_range_query + amdgpu_vm_reserve_vmid + amdgpu_vm_unreserve_vmid +amdgpu_get_fb_id EOF done) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 6786007..9483080 100644 +index 1eca68f..1f1b120 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -642,6 +642,21 @@ int amdgpu_bo_import(amdgpu_device_handle dev, +@@ -647,6 +647,21 @@ int amdgpu_bo_import(amdgpu_device_handle dev, struct amdgpu_bo_import_result *output); /** + * Allow others to get access to crtc's framebuffer + * + * \param dev - \c [in] Device handle. -+ * See #amdgpu_device_initialize() ++ * See #amdgpu_device_initialize() + * \param fb_id - \c [out] the first crtc's framebuffer's buffer_id + * + * \return 0 on success\n @@ -59,10 +60,10 @@ index 6786007..9483080 100644 * * \param dev - [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 0760be9..aa37462 100644 +index 5ffda7e..80c4e95 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -43,6 +43,7 @@ +@@ -39,6 +39,7 @@ #include "amdgpu_internal.h" #include "util_hash_table.h" #include "util_math.h" @@ -70,7 +71,7 @@ index 0760be9..aa37462 100644 static void amdgpu_close_kms_handle(amdgpu_device_handle dev, uint32_t handle) -@@ -417,6 +418,57 @@ int amdgpu_bo_import(amdgpu_device_handle dev, +@@ -391,6 +392,57 @@ int amdgpu_bo_import(amdgpu_device_handle dev, return 0; } @@ -127,7 +128,6 @@ index 0760be9..aa37462 100644 + int amdgpu_bo_free(amdgpu_bo_handle buf_handle) { - /* Just drop the reference. */ + struct amdgpu_device *dev; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch index 8766f2de..856be722 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch @@ -14,6 +14,7 @@ Fix memory leak in amdgpu_get_bo_from_fb_id Change-Id: Id315a05147035b4ce16f72d627881c5166015473 Signed-off-by: jqdeng <Emily.Deng@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu-symbol-check | 1 + amdgpu/amdgpu.h | 17 ++++++++ @@ -21,22 +22,22 @@ Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> 3 files changed, 119 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index f5cf9ff..82ff12c 100755 +index cf03353..a84ba7e 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check -@@ -60,6 +60,7 @@ amdgpu_va_range_alloc - amdgpu_va_range_free - amdgpu_va_range_query +@@ -71,6 +71,7 @@ amdgpu_va_range_query + amdgpu_vm_reserve_vmid + amdgpu_vm_unreserve_vmid amdgpu_get_fb_id +amdgpu_get_bo_from_fb_id EOF done) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 9483080..38b3597 100644 +index 01cad97..0ded2cb 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -657,6 +657,23 @@ int amdgpu_bo_import(amdgpu_device_handle dev, +@@ -662,6 +662,23 @@ int amdgpu_bo_import(amdgpu_device_handle dev, int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id); /** @@ -61,10 +62,10 @@ index 9483080..38b3597 100644 * * \param dev - [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index aa37462..fef6152 100644 +index 86d39f9..3031d37 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -469,6 +469,107 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) +@@ -446,6 +446,107 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) return r; } @@ -171,7 +172,6 @@ index aa37462..fef6152 100644 + int amdgpu_bo_free(amdgpu_bo_handle buf_handle) { - /* Just drop the reference. */ + struct amdgpu_device *dev; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch b/meta-v1000/recipes-graphics/drm/libdrm/0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch index 856abdf1..3cc26e32 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch @@ -12,36 +12,35 @@ stop fb_id test for ASIC without output Signed-off-by: jqdeng <Emily.Deng@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - tests/amdgpu/bo_tests.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) + tests/amdgpu/bo_tests.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 74b5e77..83f42a9 100644 +index 9d4da4a..2ab31c1 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c -@@ -46,6 +46,8 @@ static amdgpu_va_handle va_handle; - static void amdgpu_bo_export_import(void); - static void amdgpu_bo_metadata(void); +@@ -44,6 +44,7 @@ static void amdgpu_bo_metadata(void); static void amdgpu_bo_map_unmap(void); + static void amdgpu_memory_alloc(void); + static void amdgpu_mem_fail_alloc(void); +static void amdgpu_get_fb_id_and_handle(void); -+ CU_TestInfo bo_tests[] = { { "Export/Import", amdgpu_bo_export_import }, -@@ -53,6 +55,7 @@ CU_TestInfo bo_tests[] = { - { "Metadata", amdgpu_bo_metadata }, - #endif +@@ -51,6 +52,7 @@ CU_TestInfo bo_tests[] = { { "CPU map/unmap", amdgpu_bo_map_unmap }, + { "Memory alloc Test", amdgpu_memory_alloc }, + { "Memory fail alloc Test", amdgpu_mem_fail_alloc }, + { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, CU_TEST_INFO_NULL, }; -@@ -195,3 +198,22 @@ static void amdgpu_bo_map_unmap(void) - r = amdgpu_bo_cpu_unmap(buffer_handle); +@@ -194,6 +196,25 @@ static void amdgpu_bo_map_unmap(void) CU_ASSERT_EQUAL(r, 0); } -+ + +static void amdgpu_get_fb_id_and_handle(void) +{ + uint32_t *ptr; @@ -60,6 +59,9 @@ index 74b5e77..83f42a9 100644 + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); +} ++ + static void amdgpu_memory_alloc(void) + { + amdgpu_bo_handle bo; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0019-drm-amdgpu-add-freesync-ioctl-defines.patch b/meta-v1000/recipes-graphics/drm/libdrm/0019-drm-amdgpu-add-freesync-ioctl-defines.patch index 7ac4a6e1..9e10fea2 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0019-drm-amdgpu-add-freesync-ioctl-defines.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0019-drm-amdgpu-add-freesync-ioctl-defines.patch @@ -7,31 +7,32 @@ Change-Id: Id5d607fee4ae119015ca685a508a2ee140a8e331 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 1919c28..bd34a86 100644 +index 982dd22..0598a47 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -53,6 +53,7 @@ extern "C" { - #define DRM_AMDGPU_WAIT_FENCES 0x12 - #define DRM_AMDGPU_VM 0x13 +@@ -55,6 +55,7 @@ extern "C" { + #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 + #define DRM_AMDGPU_SCHED 0x15 /* hybrid specific ioctls */ -+#define DRM_AMDGPU_FREESYNC 0x5d ++#define DRM_AMDGPU_FREESYNC 0x5d #define DRM_AMDGPU_GEM_FIND_BO 0x5f #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) -@@ -71,6 +72,7 @@ extern "C" { - #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) +@@ -75,6 +76,7 @@ extern "C" { + #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) /* hybrid specific ioctls */ #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -+#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) ++#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -922,6 +924,19 @@ struct drm_amdgpu_capability { +@@ -992,6 +994,19 @@ struct drm_amdgpu_capability { uint32_t direct_gma_size; }; @@ -39,13 +40,13 @@ index 1919c28..bd34a86 100644 + * Definition of free sync enter and exit signals + * We may have more options in the future + */ -+#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 -+#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 ++#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 ++#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 + +struct drm_amdgpu_freesync { -+ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ -+ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ -+ __u32 spare[7]; ++ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ ++ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ ++ __u32 spare[7]; +}; + #if defined(__cplusplus) @@ -53,4 +54,3 @@ index 1919c28..bd34a86 100644 #endif -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch b/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch index 529fee1d..d589b7d5 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0020-amdgpu-implement-direct-gma.patch @@ -6,6 +6,7 @@ Subject: [PATCH 20/39] amdgpu: implement direct gma Change-Id: I37a6a0f79a91b8e793fc90eb3955045bebf24848 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 43 +++++++++++++++++++++++++++++++++++++ amdgpu/amdgpu_bo.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++- @@ -13,10 +14,10 @@ Signed-off-by: Avinash M N <avimn@amd.com> 3 files changed, 109 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 38b3597..e7a566f 100644 +index f2baa26..423ad28 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -731,6 +731,49 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, +@@ -736,6 +736,49 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, amdgpu_bo_handle *buf_handle, uint64_t *offset_in_bo); @@ -47,8 +48,8 @@ index 38b3597..e7a566f 100644 + * It is responsibility of caller to correctly specify physical_address +*/ +int amdgpu_create_bo_from_phys_mem(amdgpu_device_handle dev, -+ uint64_t phys_address, uint64_t size, -+ amdgpu_bo_handle *buf_handle); ++ uint64_t phys_address, uint64_t size, ++ amdgpu_bo_handle *buf_handle); + +/** + * Get physical address from BO @@ -62,25 +63,25 @@ index 38b3597..e7a566f 100644 + * +*/ +int amdgpu_bo_get_phys_address(amdgpu_bo_handle buf_handle, -+ uint64_t *phys_address); ++ uint64_t *phys_address); /** * Free previosuly allocated memory diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index fef6152..5a9cdbe2 100644 +index 8737d51..8f32d8d 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -87,7 +87,8 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev, +@@ -60,7 +60,8 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev, int r = 0; /* It's an error if the heap is not specified */ - if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM))) + if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM -+ | AMDGPU_GEM_DOMAIN_DGMA))) ++ | AMDGPU_GEM_DOMAIN_DGMA))) return -EINVAL; bo = calloc(1, sizeof(struct amdgpu_bo)); -@@ -570,6 +571,58 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc +@@ -544,6 +545,58 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc return r; } @@ -138,28 +139,28 @@ index fef6152..5a9cdbe2 100644 + int amdgpu_bo_free(amdgpu_bo_handle buf_handle) { - /* Just drop the reference. */ + struct amdgpu_device *dev; diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index bd34a86..b515809 100644 +index 0598a47..088cb3f 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -53,6 +53,7 @@ extern "C" { - #define DRM_AMDGPU_WAIT_FENCES 0x12 - #define DRM_AMDGPU_VM 0x13 +@@ -55,6 +55,7 @@ extern "C" { + #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 + #define DRM_AMDGPU_SCHED 0x15 /* hybrid specific ioctls */ -+#define DRM_AMDGPU_GEM_DGMA 0x5c - #define DRM_AMDGPU_FREESYNC 0x5d ++#define DRM_AMDGPU_GEM_DGMA 0x5c + #define DRM_AMDGPU_FREESYNC 0x5d #define DRM_AMDGPU_GEM_FIND_BO 0x5f -@@ -71,6 +72,7 @@ extern "C" { - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) +@@ -75,6 +76,7 @@ extern "C" { + #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) + #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) /* hybrid specific ioctls */ -+#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) ++#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) + #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) -@@ -80,6 +82,7 @@ extern "C" { +@@ -84,6 +86,7 @@ extern "C" { #define AMDGPU_GEM_DOMAIN_GDS 0x8 #define AMDGPU_GEM_DOMAIN_GWS 0x10 #define AMDGPU_GEM_DOMAIN_OA 0x20 @@ -167,17 +168,17 @@ index bd34a86..b515809 100644 /* Flag that CPU access will be required for the case of VRAM domain */ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) -@@ -243,6 +246,15 @@ struct drm_amdgpu_gem_userptr { +@@ -283,6 +286,15 @@ struct drm_amdgpu_gem_userptr { __u32 handle; }; -+#define AMDGPU_GEM_DGMA_IMPORT 0 -+#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 ++#define AMDGPU_GEM_DGMA_IMPORT 0 ++#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 +struct drm_amdgpu_gem_dgma { -+ uint64_t addr; -+ uint64_t size; -+ uint32_t op; -+ uint32_t handle; ++ uint64_t addr; ++ uint64_t size; ++ uint32_t op; ++ uint32_t handle; +}; + struct drm_amdgpu_gem_find_bo { @@ -185,4 +186,3 @@ index bd34a86..b515809 100644 uint64_t size; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0021-tests-amdgpu-add-direct-gma-test.patch b/meta-v1000/recipes-graphics/drm/libdrm/0021-tests-amdgpu-add-direct-gma-test.patch index 076e4137..cbec2bb8 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0021-tests-amdgpu-add-direct-gma-test.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0021-tests-amdgpu-add-direct-gma-test.patch @@ -5,12 +5,13 @@ Subject: [PATCH 21/39] tests/amdgpu: add direct gma test Change-Id: Ib00252eff16a84f16f01039ff39f957bff903bae Signed-off-by: Flora Cui <Flora.Cui@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - tests/amdgpu/bo_tests.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 63 insertions(+), 1 deletion(-) + tests/amdgpu/bo_tests.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 83f42a9..930a073 100644 +index 2c03fd2..58a00ec 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c @@ -26,6 +26,7 @@ @@ -21,28 +22,26 @@ index 83f42a9..930a073 100644 #include "CUnit/Basic.h" -@@ -47,7 +48,7 @@ static void amdgpu_bo_export_import(void); - static void amdgpu_bo_metadata(void); - static void amdgpu_bo_map_unmap(void); +@@ -49,6 +50,7 @@ static void amdgpu_bo_map_unmap(void); + static void amdgpu_memory_alloc(void); + static void amdgpu_mem_fail_alloc(void); static void amdgpu_get_fb_id_and_handle(void); -- +static void amdgpu_bo_direct_gma(void); CU_TestInfo bo_tests[] = { { "Export/Import", amdgpu_bo_export_import }, -@@ -56,6 +57,7 @@ CU_TestInfo bo_tests[] = { - #endif - { "CPU map/unmap", amdgpu_bo_map_unmap }, +@@ -57,6 +59,7 @@ CU_TestInfo bo_tests[] = { + { "Memory alloc Test", amdgpu_memory_alloc }, + { "Memory fail alloc Test", amdgpu_mem_fail_alloc }, { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, + { "Direct GMA", amdgpu_bo_direct_gma }, CU_TEST_INFO_NULL, }; -@@ -217,3 +219,63 @@ static void amdgpu_get_fb_id_and_handle(void) - CU_ASSERT_EQUAL(r, 0); +@@ -219,6 +222,66 @@ static void amdgpu_get_fb_id_and_handle(void) CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); } -+ + +#define TEST_LOOP 20 +static void amdgpu_bo_direct_gma(void) +{ @@ -102,6 +101,9 @@ index 83f42a9..930a073 100644 + } + } +} ++ + static void amdgpu_memory_alloc(void) + { + amdgpu_bo_handle bo; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0022-amdgpu-add-new-semaphore-support-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0022-amdgpu-add-new-semaphore-support-v2.patch index 090147da..43b37a98 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0022-amdgpu-add-new-semaphore-support-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0022-amdgpu-add-new-semaphore-support-v2.patch @@ -1,7 +1,7 @@ -From 64a09d85da3869bf77a0b70fd1709f654ba3582d Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 22 Sep 2016 14:50:16 +0800 -Subject: [PATCH 22/39] amdgpu: add new semaphore support v2 +From c18acb08e7d948c3bb06d1737a4121b77acb46a6 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Mon, 18 Dec 2017 15:32:27 +0500 +Subject: [PATCH] amdgpu: add new semaphore support v2 v2: 612336476adaffdd715fcc74c5aabceee8d53add @@ -19,17 +19,19 @@ Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Awais Belal <awais_belal@mentor.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 74 +++++++++++++++++++++++++++++++++++++++ amdgpu/amdgpu_cs.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 30 ++++++++++++++++ - 3 files changed, 195 insertions(+) + include/drm/amdgpu_drm.h | 31 +++++++++++++++++ + 3 files changed, 196 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index e7a566f..bff3252 100644 +index 423ad28..5247498 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -141,6 +141,12 @@ typedef struct amdgpu_va *amdgpu_va_handle; +@@ -146,6 +146,12 @@ typedef struct amdgpu_va *amdgpu_va_handle; */ typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; @@ -42,7 +44,7 @@ index e7a566f..bff3252 100644 /*--------------------------------------------------------------------------*/ /* -------------------------- Structures ---------------------------------- */ /*--------------------------------------------------------------------------*/ -@@ -1578,6 +1584,74 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, +@@ -1616,6 +1622,74 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); /** @@ -118,7 +120,7 @@ index e7a566f..bff3252 100644 * * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index dfba875..8675806 100644 +index 46dffe1..9f21681 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -25,6 +25,8 @@ @@ -130,7 +132,7 @@ index dfba875..8675806 100644 #include <stdlib.h> #include <stdio.h> #include <string.h> -@@ -597,6 +599,95 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) +@@ -606,6 +608,95 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) return amdgpu_cs_unreference_sem(sem); } @@ -223,33 +225,37 @@ index dfba875..8675806 100644 + return 0; +} + - int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, - uint32_t *handle) - { + int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, + uint32_t flags, + uint32_t *handle) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index b515809..6cf8c1b 100644 +index 43bb2f5..910f200 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -52,7 +52,9 @@ extern "C" { - #define DRM_AMDGPU_GEM_USERPTR 0x11 - #define DRM_AMDGPU_WAIT_FENCES 0x12 +@@ -54,7 +54,9 @@ extern "C" { #define DRM_AMDGPU_VM 0x13 + #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 + #define DRM_AMDGPU_SCHED 0x15 + /* hybrid specific ioctls */ -+#define DRM_AMDGPU_SEM 0x5b - #define DRM_AMDGPU_GEM_DGMA 0x5c - #define DRM_AMDGPU_FREESYNC 0x5d ++#define DRM_AMDGPU_SEM 0x5b + #define DRM_AMDGPU_GEM_DGMA 0x5c + #define DRM_AMDGPU_FREESYNC 0x5d #define DRM_AMDGPU_GEM_FIND_BO 0x5f -@@ -74,6 +76,7 @@ extern "C" { +@@ -75,9 +77,11 @@ extern "C" { + #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) + #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) + #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) ++ /* hybrid specific ioctls */ - #define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) + #define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -+#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) ++#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) + #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) #define AMDGPU_GEM_DOMAIN_CPU 0x1 -@@ -227,6 +230,33 @@ union drm_amdgpu_vm { - struct drm_amdgpu_vm_out out; +@@ -259,6 +263,33 @@ union drm_amdgpu_sched { + struct drm_amdgpu_sched_in in; }; +/* sync file related */ @@ -284,4 +290,3 @@ index b515809..6cf8c1b 100644 * number of reasons and have fallback path that do not use userptr to -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0024-test-case-for-export-import-sem.patch b/meta-v1000/recipes-graphics/drm/libdrm/0024-test-case-for-export-import-sem.patch index 5c11dc9d..fbf31d82 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0024-test-case-for-export-import-sem.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0024-test-case-for-export-import-sem.patch @@ -1,7 +1,7 @@ -From f7384045361d01f28ccf1c2772680a1630fc5d6d Mon Sep 17 00:00:00 2001 -From: David Mao <david.mao@amd.com> -Date: Mon, 23 Jan 2017 11:31:58 +0800 -Subject: [PATCH 24/39] test case for export/import sem +From 317f44faa8c3a645134147f1fafb5805a4d98159 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Mon, 18 Dec 2017 15:37:24 +0500 +Subject: [PATCH] test case for export/import sem Test covers basic functionality includes create/destroy/import/export/wait/signal @@ -9,28 +9,29 @@ Change-Id: I8a8d767e5ef1889f8ac214fef98befba83969d8d Signed-off-by: David Mao <david.mao@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> + +Signed-off-by: Awais Belal <awais_belal@mentor.com> --- - tests/amdgpu/basic_tests.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) + tests/amdgpu/basic_tests.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 59 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 41a702d..1807538 100644 +index 520f1c96..9f6331f2 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c -@@ -504,6 +504,8 @@ static void amdgpu_semaphore_test(void) - uint32_t expired; +@@ -545,6 +545,8 @@ static void amdgpu_semaphore_test(void) + uint32_t sdma_nop, gfx_nop; amdgpu_bo_list_handle bo_list[2]; amdgpu_va_handle va_handle[2]; + amdgpu_sem_handle sem_handle, sem_handle_import; + int fd; int r, i; - r = amdgpu_cs_create_semaphore(&sem); -@@ -604,6 +606,64 @@ static void amdgpu_semaphore_test(void) - 500000000, 0, &expired); + if (family_id == AMDGPU_FAMILY_SI) { +@@ -654,6 +656,63 @@ static void amdgpu_semaphore_test(void) CU_ASSERT_EQUAL(r, 0); CU_ASSERT_EQUAL(expired, true); -+ + + /* 3. export/import sem test */ + r = amdgpu_cs_create_sem(device_handle, &sem_handle); + CU_ASSERT_EQUAL(r, 0); @@ -92,5 +93,5 @@ index 41a702d..1807538 100644 r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i], ib_result_mc_address[i], 4096); -- -2.7.4 +2.11.1 diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch index 2a8c1721..60cb6cd9 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch @@ -29,19 +29,20 @@ Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- amdgpu/amdgpu.h | 22 +++++++++++ - amdgpu/amdgpu_bo.c | 101 +++++++++++++++++++++++++++++++++++++++++++++++ + amdgpu/amdgpu_bo.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++ amdgpu/amdgpu_device.c | 11 ++++++ amdgpu/amdgpu_internal.h | 11 ++++++ amdgpu/amdgpu_vamgr.c | 29 ++++++++++++++ - 5 files changed, 174 insertions(+) + 5 files changed, 173 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index a9ef5ca..ade6d37 100644 +index f373be0..df0d88c 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -1479,6 +1479,28 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, +@@ -1517,6 +1517,28 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, uint32_t ops); /** @@ -59,22 +60,22 @@ index a9ef5ca..ade6d37 100644 + * <0 - Negative POSIX Error code + */ +int amdgpu_bo_va_op_refcounted(amdgpu_device_handle dev, -+ amdgpu_bo_handle bo, -+ uint64_t offset, -+ uint64_t size, -+ uint64_t addr, -+ uint64_t flags, -+ uint32_t ops); ++ amdgpu_bo_handle bo, ++ uint64_t offset, ++ uint64_t size, ++ uint64_t addr, ++ uint64_t flags, ++ uint32_t ops); + +/** * Reserve the virtual address range for SVM support * * \param amdgpu_device_handle diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 5a9cdbe2..9534c40 100644 +index 2ea9a0f..bfcdd07 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c -@@ -968,3 +968,104 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, +@@ -972,3 +972,103 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, return r; } @@ -178,15 +179,14 @@ index 5a9cdbe2..9534c40 100644 + pthread_mutex_unlock(&dev->remap_mutex); + return r; +} -+ diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index f95f163..03843b6 100644 +index e21ee8e..854c8f3 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c -@@ -131,11 +131,19 @@ int amdgpu_get_auth(int fd, int *auth) +@@ -130,11 +130,19 @@ int amdgpu_get_auth(int fd, int *auth) + static void amdgpu_device_free_internal(amdgpu_device_handle dev) { - const struct amdgpu_asic_id *id; + struct amdgpu_va_remap* vao; amdgpu_vamgr_deinit(&dev->vamgr_32); amdgpu_vamgr_deinit(&dev->vamgr); @@ -196,14 +196,14 @@ index f95f163..03843b6 100644 + + pthread_mutex_destroy(&dev->remap_mutex); + LIST_FOR_EACH_ENTRY(vao, &dev->remap_list, list) { -+ list_del(&vao->list); -+ free(vao); ++ list_del(&vao->list); ++ free(vao); + } + util_hash_table_remove(fd_tab, UINT_TO_PTR(dev->fd)); close(dev->fd); if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd)) -@@ -281,6 +289,9 @@ int amdgpu_device_initialize(int fd, +@@ -290,6 +298,9 @@ int amdgpu_device_initialize(int fd, dev->svm_allocated = false; @@ -214,11 +214,11 @@ index f95f163..03843b6 100644 *minor_version = dev->minor_version; *device_handle = dev; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 3d83c1a..b39f47a 100644 +index e284d91..64e9062 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h -@@ -80,6 +80,14 @@ struct amdgpu_asic_id { - char *marketing_name; +@@ -72,6 +72,14 @@ struct amdgpu_va { + struct amdgpu_bo_va_mgr *vamgr; }; +struct amdgpu_va_remap{ @@ -232,8 +232,8 @@ index 3d83c1a..b39f47a 100644 struct amdgpu_device { atomic_t refcount; int fd; -@@ -103,6 +111,9 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr vamgr_32; +@@ -98,6 +106,9 @@ struct amdgpu_device { + struct amdgpu_bo_va_mgr vamgr_high_32; /** svm range allocated */ bool svm_allocated; + /** The VA remapped list*/ @@ -243,10 +243,10 @@ index 3d83c1a..b39f47a 100644 struct amdgpu_bo { diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 63124a4..5c91d58 100644 +index 2af0989..9bdb52e 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c -@@ -475,9 +475,38 @@ int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, +@@ -457,9 +457,38 @@ int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) { @@ -287,4 +287,3 @@ index 63124a4..5c91d58 100644 va_range_handle->size); -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0026-tests-amdgpu-add-uvd-enc-unit-tests-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0026-tests-amdgpu-add-uvd-enc-unit-tests-v2.patch deleted file mode 100644 index 63fcd42b..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0026-tests-amdgpu-add-uvd-enc-unit-tests-v2.patch +++ /dev/null @@ -1,387 +0,0 @@ -From 71b1a43633da6dd72be6aba64aa615917d378d16 Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Wed, 11 Jan 2017 14:03:03 -0500 -Subject: [PATCH 26/39] tests/amdgpu: add uvd enc unit tests v2 - -v2: -2fc4b7adae824313a169fc33e80aa62c1105be99 -[Ken Wang] -fix test failure on pre-vega10 card (part) - -Signed-off-by: Leo Liu <leo.liu@amd.com> -Acked-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> -Signed-off-by: Avinash M N <avimn@amd.com> ---- - tests/amdgpu/Makefile.am | 1 + - tests/amdgpu/amdgpu_test.c | 6 + - tests/amdgpu/amdgpu_test.h | 15 +++ - tests/amdgpu/uvd_enc_tests.c | 303 +++++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 325 insertions(+) - create mode 100644 tests/amdgpu/uvd_enc_tests.c - -diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am -index 9e08578..13b3dc8 100644 ---- a/tests/amdgpu/Makefile.am -+++ b/tests/amdgpu/Makefile.am -@@ -27,4 +27,5 @@ amdgpu_test_SOURCES = \ - vce_tests.c \ - vce_ib.h \ - frame.h \ -+ uvd_enc_tests.c \ - vcn_tests.c -diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c -index 1d44b09..032cc0d 100644 ---- a/tests/amdgpu/amdgpu_test.c -+++ b/tests/amdgpu/amdgpu_test.c -@@ -86,6 +86,12 @@ static CU_SuiteInfo suites[] = { - .pTests = vce_tests, - }, - { -+ .pName = "UVD ENC Tests", -+ .pInitFunc = suite_uvd_enc_tests_init, -+ .pCleanupFunc = suite_uvd_enc_tests_clean, -+ .pTests = uvd_enc_tests, -+ }, -+ { - .pName = "VCN Tests", - .pInitFunc = suite_vcn_tests_init, - .pCleanupFunc = suite_vcn_tests_clean, -diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h -index c75a07a..042672f 100644 ---- a/tests/amdgpu/amdgpu_test.h -+++ b/tests/amdgpu/amdgpu_test.h -@@ -105,6 +105,21 @@ int suite_vce_tests_clean(); - extern CU_TestInfo vce_tests[]; - - /** -+ * Initialize uvd enc test suite -+ */ -+int suite_uvd_enc_tests_init(); -+ -+/** -+ * Deinitialize uvd enc test suite -+ */ -+int suite_uvd_enc_tests_clean(); -+ -+/** -+ * Tests in uvd enc test suite -+ */ -+extern CU_TestInfo uvd_enc_tests[]; -+ -+/** - + * Initialize vcn test suite - + */ - int suite_vcn_tests_init(); -diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c -new file mode 100644 -index 0000000..81318df ---- /dev/null -+++ b/tests/amdgpu/uvd_enc_tests.c -@@ -0,0 +1,303 @@ -+/* -+ * Copyright 2017 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+*/ -+ -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif -+ -+#include <stdio.h> -+#include <inttypes.h> -+ -+#include "CUnit/Basic.h" -+ -+#include "util_math.h" -+ -+#include "amdgpu_test.h" -+#include "amdgpu_drm.h" -+#include "amdgpu_internal.h" -+ -+#define IB_SIZE 4096 -+#define MAX_RESOURCES 16 -+ -+struct amdgpu_uvd_enc_bo { -+ amdgpu_bo_handle handle; -+ amdgpu_va_handle va_handle; -+ uint64_t addr; -+ uint64_t size; -+ uint8_t *ptr; -+}; -+ -+static amdgpu_device_handle device_handle; -+static uint32_t major_version; -+static uint32_t minor_version; -+static uint32_t family_id; -+ -+static amdgpu_context_handle context_handle; -+static amdgpu_bo_handle ib_handle; -+static amdgpu_va_handle ib_va_handle; -+static uint64_t ib_mc_address; -+static uint32_t *ib_cpu; -+ -+static amdgpu_bo_handle resources[MAX_RESOURCES]; -+static unsigned num_resources; -+ -+static void amdgpu_cs_uvd_enc_create(void); -+static void amdgpu_cs_uvd_enc_encode(void); -+static void amdgpu_cs_uvd_enc_destroy(void); -+ -+CU_TestInfo uvd_enc_tests[] = { -+ { "UVD ENC create", amdgpu_cs_uvd_enc_create }, -+ { "UVD ENC encode", amdgpu_cs_uvd_enc_encode }, -+ { "UVD ENC destroy", amdgpu_cs_uvd_enc_destroy }, -+ CU_TEST_INFO_NULL, -+}; -+ -+int suite_uvd_enc_tests_init(void) -+{ -+ int r; -+ -+ r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, -+ &minor_version, &device_handle); -+ if (r) -+ return CUE_SINIT_FAILED; -+ -+ family_id = device_handle->info.family_id; -+ -+ if (family_id < AMDGPU_FAMILY_AI) { -+ -+ printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n"); -+ -+ return CUE_SUCCESS; -+ } -+ -+ r = amdgpu_cs_ctx_create(device_handle, &context_handle); -+ if (r) -+ return CUE_SINIT_FAILED; -+ -+ r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, -+ AMDGPU_GEM_DOMAIN_GTT, 0, -+ &ib_handle, (void**)&ib_cpu, -+ &ib_mc_address, &ib_va_handle); -+ if (r) -+ return CUE_SINIT_FAILED; -+ -+ return CUE_SUCCESS; -+} -+ -+int suite_uvd_enc_tests_clean(void) -+{ -+ int r; -+ -+ if (family_id < AMDGPU_FAMILY_AI) { -+ -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ return CUE_SUCCESS; -+ } else { -+ -+ r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -+ ib_mc_address, IB_SIZE); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_cs_ctx_free(context_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } -+ -+ return CUE_SUCCESS; -+} -+ -+static int submit(unsigned ndw, unsigned ip) -+{ -+ struct amdgpu_cs_request ibs_request = {0}; -+ struct amdgpu_cs_ib_info ib_info = {0}; -+ struct amdgpu_cs_fence fence_status = {0}; -+ uint32_t expired; -+ int r; -+ -+ ib_info.ib_mc_address = ib_mc_address; -+ ib_info.size = ndw; -+ -+ ibs_request.ip_type = ip; -+ -+ r = amdgpu_bo_list_create(device_handle, num_resources, resources, -+ NULL, &ibs_request.resources); -+ if (r) -+ return r; -+ -+ ibs_request.number_of_ibs = 1; -+ ibs_request.ibs = &ib_info; -+ ibs_request.fence_info.handle = NULL; -+ -+ r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); -+ if (r) -+ return r; -+ -+ r = amdgpu_bo_list_destroy(ibs_request.resources); -+ if (r) -+ return r; -+ -+ fence_status.context = context_handle; -+ fence_status.ip_type = ip; -+ fence_status.fence = ibs_request.seq_no; -+ -+ r = amdgpu_cs_query_fence_status(&fence_status, -+ AMDGPU_TIMEOUT_INFINITE, -+ 0, &expired); -+ if (r) -+ return r; -+ -+ return 0; -+} -+ -+static void alloc_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo, -+ unsigned size, unsigned domain) -+{ -+ struct amdgpu_bo_alloc_request req = {0}; -+ amdgpu_bo_handle buf_handle; -+ amdgpu_va_handle va_handle; -+ uint64_t va = 0; -+ int r; -+ -+ req.alloc_size = ALIGN(size, 4096); -+ req.preferred_heap = domain; -+ r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_va_range_alloc(device_handle, -+ amdgpu_gpu_va_range_general, -+ req.alloc_size, 1, 0, &va, -+ &va_handle, 0); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, -+ AMDGPU_VA_OP_MAP); -+ CU_ASSERT_EQUAL(r, 0); -+ uvd_enc_bo->addr = va; -+ uvd_enc_bo->handle = buf_handle; -+ uvd_enc_bo->size = req.alloc_size; -+ uvd_enc_bo->va_handle = va_handle; -+ r = amdgpu_bo_cpu_map(uvd_enc_bo->handle, (void **)&uvd_enc_bo->ptr); -+ CU_ASSERT_EQUAL(r, 0); -+ memset(uvd_enc_bo->ptr, 0, size); -+ r = amdgpu_bo_cpu_unmap(uvd_enc_bo->handle); -+ CU_ASSERT_EQUAL(r, 0); -+} -+ -+static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) -+{ -+ int r; -+ -+ r = amdgpu_bo_va_op(uvd_enc_bo->handle, 0, uvd_enc_bo->size, -+ uvd_enc_bo->addr, 0, AMDGPU_VA_OP_UNMAP); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_va_range_free(uvd_enc_bo->va_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_free(uvd_enc_bo->handle); -+ CU_ASSERT_EQUAL(r, 0); -+ memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo)); -+} -+ -+static void amdgpu_cs_uvd_enc_create(void) -+{ -+ struct amdgpu_uvd_enc_bo sw_ctx; -+ int len, r; -+ -+ if (family_id < AMDGPU_FAMILY_AI) -+ return; -+ -+ num_resources = 0; -+ alloc_resource(&sw_ctx, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -+ resources[num_resources++] = sw_ctx.handle; -+ resources[num_resources++] = ib_handle; -+ -+ len = 0; -+ ib_cpu[len++] = 0x00000018; -+ ib_cpu[len++] = 0x00000001; /* session info */ -+ ib_cpu[len++] = 0x00000001; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = sw_ctx.addr >> 32; -+ ib_cpu[len++] = sw_ctx.addr; -+ -+ ib_cpu[len++] = 0x00000014; -+ ib_cpu[len++] = 0x00000002; /* task info */ -+ ib_cpu[len++] = 0x0000001c; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = 0x00000000; -+ -+ ib_cpu[len++] = 0x00000008; -+ ib_cpu[len++] = 0x08000001; /* op initialize */ -+ -+ r = submit(len, AMDGPU_HW_IP_UVD_ENC); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ free_resource(&sw_ctx); -+} -+ -+static void amdgpu_cs_uvd_enc_encode(void) -+{ -+ /* TODO */ -+} -+ -+static void amdgpu_cs_uvd_enc_destroy(void) -+{ -+ struct amdgpu_uvd_enc_bo sw_ctx; -+ int len, r; -+ -+ if (family_id < AMDGPU_FAMILY_AI) -+ return; -+ -+ num_resources = 0; -+ alloc_resource(&sw_ctx, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -+ resources[num_resources++] = sw_ctx.handle; -+ resources[num_resources++] = ib_handle; -+ -+ len = 0; -+ ib_cpu[len++] = 0x00000018; -+ ib_cpu[len++] = 0x00000001; /* session info */ -+ ib_cpu[len++] = 0x00000001; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = sw_ctx.addr >> 32; -+ ib_cpu[len++] = sw_ctx.addr; -+ -+ ib_cpu[len++] = 0x00000014; -+ ib_cpu[len++] = 0x00000002; /* task info */ -+ ib_cpu[len++] = 0xffffffff; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = 0x00000000; -+ -+ ib_cpu[len++] = 0x00000008; -+ ib_cpu[len++] = 0x08000002; /* op close session */ -+ -+ r = submit(len, AMDGPU_HW_IP_UVD_ENC); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ free_resource(&sw_ctx); -+} --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0027-tests-amdgpu-add-uve-ib-header.patch b/meta-v1000/recipes-graphics/drm/libdrm/0027-tests-amdgpu-add-uve-ib-header.patch deleted file mode 100644 index 154ce142..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0027-tests-amdgpu-add-uve-ib-header.patch +++ /dev/null @@ -1,344 +0,0 @@ -From 0af63ae477629806586c8e26480e48febf4fa4f9 Mon Sep 17 00:00:00 2001 -From: Boyuan Zhang <boyuan.zhang@amd.com> -Date: Mon, 13 Feb 2017 09:43:42 -0500 -Subject: [PATCH 27/39] tests/amdgpu: add uve ib header - -Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> -Reviewed-by: Leo Liu <leo.liu@amd.com> ---- - tests/amdgpu/uve_ib.h | 323 ++++++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 323 insertions(+) - create mode 100644 tests/amdgpu/uve_ib.h - -diff --git a/tests/amdgpu/uve_ib.h b/tests/amdgpu/uve_ib.h -new file mode 100644 -index 0000000..c24b9e8 ---- /dev/null -+++ b/tests/amdgpu/uve_ib.h -@@ -0,0 +1,323 @@ -+/* -+ * Copyright 2017 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+*/ -+ -+#ifndef _uve_ib_h_ -+#define _uve_ib_h_ -+ -+static const uint32_t uve_session_info[] = { -+ 0x00000018, -+ 0x00000001, -+ 0x00000001, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_task_info[] = { -+ 0x00000014, -+ 0x00000002, -+}; -+ -+static const uint32_t uve_session_init[] = { -+ 0x00000068, -+ 0x00000003, -+ 0x00000000, -+ 0x000000c0, -+ 0x00000080, -+ 0x00000000, -+ 0x00000000, -+ 0x00000001, -+ 0x00000002, -+ 0x000000c0, -+ 0x00000080, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_layer_ctrl[] = { -+ 0x00000010, -+ 0x00000004, -+ 0x00000001, -+ 0x00000001, -+}; -+ -+static const uint32_t uve_layer_select[] = { -+ 0x0000000c, -+ 0x00000005, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_slice_ctrl[] = { -+ 0x00000014, -+ 0x00000006, -+ 0x00000000, -+ 0x00000008, -+ 0x00000008, -+}; -+ -+static const uint32_t uve_spec_misc[] = { -+ 0x00000024, -+ 0x00000007, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000004, -+ 0x00000000, -+ 0x00000005, -+}; -+ -+static const uint32_t uve_rc_session_init[] = { -+ 0x00000010, -+ 0x00000008, -+ 0x00000000, -+ 0x00000040, -+}; -+ -+static const uint32_t uve_rc_layer_init[] = { -+ 0x00000028, -+ 0x00000009, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_hw_spec[] = { -+ 0x0000007c, -+ 0x0000000b, -+ 0x00000002, -+ 0x00000000, -+ 0x00000001, -+ 0x00000001, -+ 0x00000001, -+ 0x00000001, -+ 0x00000001, -+ 0x00000010, -+ 0x00000010, -+ 0x00000010, -+ 0x00000010, -+ 0x00000008, -+ 0x00000008, -+ 0x00000010, -+ 0x00000010, -+ 0x00000000, -+ 0x00000002, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000001, -+ 0x00000001, -+}; -+ -+static const uint32_t uve_deblocking_filter[] = { -+ 0x00000020, -+ 0x0000000f, -+ 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_feedback_buffer[] = { -+ 0x00000014, -+ 0x00000014, -+}; -+ -+/* TODO - Slice Header*/ -+static const uint32_t uve_slice_header[] = { -+ 0x000000c8, -+ 0x0000000c, -+ 0x26010000, -+ 0x40000000, -+ 0x60000000, -+ 0x80000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000002, -+ 0x00000010, -+ 0x00000003, -+ 0x00000000, -+ 0x00000002, -+ 0x00000002, -+ 0x00000004, -+ 0x00000000, -+ 0x00000001, -+ 0x00000000, -+ 0x00000002, -+ 0x00000003, -+ 0x00000005, -+ 0x00000000, -+ 0x00000002, -+ 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_encode_param[] = { -+ 0x00000000, -+ 0x00000000, -+ 0x000000a0, -+ 0x00000080, -+ 0x00000000, -+ 0x00000000, -+ 0x00000002, -+ 0xffffffff, -+ 0xffffffff, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_quality_param[] = { -+ 0x00000014, -+ 0x0000000e, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_intra_refresh[] = { -+ 0x00000014, -+ 0x00000010, -+ 0x00000000, -+ 0x00000000, -+ 0x00000004, -+}; -+ -+static const uint32_t uve_reconstructed_pic_output[] = { -+ 0x00000020, -+ 0x00000011, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_ctx_buffer[] = { -+ 0x00000010, -+ 0x00000012, -+}; -+ -+static const uint32_t uve_bitstream_buffer[] = { -+ 0x00000014, -+ 0x00000013, -+}; -+ -+static const uint32_t uve_rc_per_pic[] = { -+ 0x00000024, -+ 0x0000000a, -+ 0x0000001a, -+ 0x00000014, -+ 0x0000002D, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_op_init[] = { -+ 0x00000008, -+ 0x08000001, -+}; -+ -+static const uint32_t uve_op_close[] = { -+ 0x00000008, -+ 0x08000002, -+}; -+ -+static const uint32_t uve_op_encode[] = { -+ 0x00000008, -+ 0x08000003, -+}; -+ -+static const uint32_t uve_op_init_rc[] = { -+ 0x00000008, -+ 0x08000004, -+}; -+#endif /*_uve_ib_h*/ --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0028-tests-amdgpu-implement-hevc-encode-test-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0028-tests-amdgpu-implement-hevc-encode-test-v2.patch deleted file mode 100644 index e3adfe55..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0028-tests-amdgpu-implement-hevc-encode-test-v2.patch +++ /dev/null @@ -1,375 +0,0 @@ -From b37b4f050ed21e52cb2a3e14105d4f4a7bb7be15 Mon Sep 17 00:00:00 2001 -From: Boyuan Zhang <boyuan.zhang@amd.com> -Date: Mon, 13 Feb 2017 09:54:32 -0500 -Subject: [PATCH 28/39] tests/amdgpu: implement hevc encode test v2 - -v2: -2fc4b7adae824313a169fc33e80aa62c1105be99 -[Ken Wang] -fix test failure on pre-vega10 card (part) - -Change-Id: I3d77e1e7f60b2b806a9134f94ba851cee699f4a9 -Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> -Reviewed-by: Leo Liu <leo.liu@amd.com> -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> ---- - tests/amdgpu/frame.h | 2 +- - tests/amdgpu/uvd_enc_tests.c | 261 ++++++++++++++++++++++++++++++++++++++----- - 2 files changed, 233 insertions(+), 30 deletions(-) - -diff --git a/tests/amdgpu/frame.h b/tests/amdgpu/frame.h -index 4c946c2..335401c 100644 ---- a/tests/amdgpu/frame.h -+++ b/tests/amdgpu/frame.h -@@ -24,7 +24,7 @@ - #ifndef _frame_h_ - #define _frame_h_ - --const uint8_t frame[] = { -+static const uint8_t frame[] = { - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, -diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c -index 81318df..fee0112 100644 ---- a/tests/amdgpu/uvd_enc_tests.c -+++ b/tests/amdgpu/uvd_enc_tests.c -@@ -35,6 +35,8 @@ - #include "amdgpu_test.h" - #include "amdgpu_drm.h" - #include "amdgpu_internal.h" -+#include "frame.h" -+#include "uve_ib.h" - - #define IB_SIZE 4096 - #define MAX_RESOURCES 16 -@@ -47,6 +49,16 @@ struct amdgpu_uvd_enc_bo { - uint8_t *ptr; - }; - -+struct amdgpu_uvd_enc { -+ unsigned width; -+ unsigned height; -+ struct amdgpu_uvd_enc_bo session; -+ struct amdgpu_uvd_enc_bo vbuf; -+ struct amdgpu_uvd_enc_bo bs; -+ struct amdgpu_uvd_enc_bo fb; -+ struct amdgpu_uvd_enc_bo cpb; -+}; -+ - static amdgpu_device_handle device_handle; - static uint32_t major_version; - static uint32_t minor_version; -@@ -58,15 +70,18 @@ static amdgpu_va_handle ib_va_handle; - static uint64_t ib_mc_address; - static uint32_t *ib_cpu; - -+static struct amdgpu_uvd_enc enc; - static amdgpu_bo_handle resources[MAX_RESOURCES]; - static unsigned num_resources; - - static void amdgpu_cs_uvd_enc_create(void); -+static void amdgpu_cs_uvd_enc_session_init(void); - static void amdgpu_cs_uvd_enc_encode(void); - static void amdgpu_cs_uvd_enc_destroy(void); - - CU_TestInfo uvd_enc_tests[] = { - { "UVD ENC create", amdgpu_cs_uvd_enc_create }, -+ { "UVD ENC session init", amdgpu_cs_uvd_enc_session_init }, - { "UVD ENC encode", amdgpu_cs_uvd_enc_encode }, - { "UVD ENC destroy", amdgpu_cs_uvd_enc_destroy }, - CU_TEST_INFO_NULL, -@@ -227,43 +242,235 @@ static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) - - static void amdgpu_cs_uvd_enc_create(void) - { -- struct amdgpu_uvd_enc_bo sw_ctx; - int len, r; - - if (family_id < AMDGPU_FAMILY_AI) - return; - -+ enc.width = 160; -+ enc.height = 128; -+ - num_resources = 0; -- alloc_resource(&sw_ctx, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -- resources[num_resources++] = sw_ctx.handle; -+ alloc_resource(&enc.session, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -+ resources[num_resources++] = enc.session.handle; - resources[num_resources++] = ib_handle; - - len = 0; -- ib_cpu[len++] = 0x00000018; -- ib_cpu[len++] = 0x00000001; /* session info */ -- ib_cpu[len++] = 0x00000001; -- ib_cpu[len++] = 0x00000000; -- ib_cpu[len++] = sw_ctx.addr >> 32; -- ib_cpu[len++] = sw_ctx.addr; -+ memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -+ len += sizeof(uve_session_info) / 4; -+ ib_cpu[len++] = enc.session.addr >> 32; -+ ib_cpu[len++] = enc.session.addr; - -- ib_cpu[len++] = 0x00000014; -- ib_cpu[len++] = 0x00000002; /* task info */ -+ memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -+ len += sizeof(uve_task_info) / 4; - ib_cpu[len++] = 0x0000001c; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - -- ib_cpu[len++] = 0x00000008; -- ib_cpu[len++] = 0x08000001; /* op initialize */ -+ memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init)); -+ len += sizeof(uve_op_init) / 4; -+ -+ r = submit(len, AMDGPU_HW_IP_UVD_ENC); -+ CU_ASSERT_EQUAL(r, 0); -+} -+ -+static void check_result(struct amdgpu_uvd_enc *enc) -+{ -+ uint64_t sum; -+ uint32_t s = 20626; -+ uint32_t *ptr, size; -+ int i, j, r; -+ -+ r = amdgpu_bo_cpu_map(enc->fb.handle, (void **)&enc->fb.ptr); -+ CU_ASSERT_EQUAL(r, 0); -+ ptr = (uint32_t *)enc->fb.ptr; -+ size = ptr[6]; -+ r = amdgpu_bo_cpu_unmap(enc->fb.handle); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_bo_cpu_map(enc->bs.handle, (void **)&enc->bs.ptr); -+ CU_ASSERT_EQUAL(r, 0); -+ for (j = 0, sum = 0; j < size; ++j) -+ sum += enc->bs.ptr[j]; -+ CU_ASSERT_EQUAL(sum, s); -+ r = amdgpu_bo_cpu_unmap(enc->bs.handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+} -+ -+static void amdgpu_cs_uvd_enc_session_init(void) -+{ -+ int len, r; -+ -+ if (family_id < AMDGPU_FAMILY_AI) -+ return; -+ -+ num_resources = 0; -+ alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_GTT); -+ resources[num_resources++] = enc.fb.handle; -+ resources[num_resources++] = ib_handle; -+ -+ len = 0; -+ memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -+ len += sizeof(uve_session_info) / 4; -+ ib_cpu[len++] = enc.session.addr >> 32; -+ ib_cpu[len++] = enc.session.addr; -+ -+ memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -+ len += sizeof(uve_task_info) / 4; -+ ib_cpu[len++] = 0x000001c0; -+ ib_cpu[len++] = 0x00000001; -+ ib_cpu[len++] = 0x00000001; -+ -+ memcpy((ib_cpu + len), uve_session_init, sizeof(uve_session_init)); -+ len += sizeof(uve_session_init) / 4; -+ -+ memcpy((ib_cpu + len), uve_layer_ctrl, sizeof(uve_layer_ctrl)); -+ len += sizeof(uve_layer_ctrl) / 4; -+ -+ memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); -+ len += sizeof(uve_layer_select) / 4; -+ -+ memcpy((ib_cpu + len), uve_slice_ctrl, sizeof(uve_slice_ctrl)); -+ len += sizeof(uve_slice_ctrl) / 4; -+ -+ memcpy((ib_cpu + len), uve_spec_misc, sizeof(uve_spec_misc)); -+ len += sizeof(uve_spec_misc) / 4; -+ -+ memcpy((ib_cpu + len), uve_rc_session_init, sizeof(uve_rc_session_init)); -+ len += sizeof(uve_rc_session_init) / 4; -+ -+ memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init)); -+ len += sizeof(uve_rc_layer_init) / 4; -+ -+ memcpy((ib_cpu + len), uve_hw_spec, sizeof(uve_hw_spec)); -+ len += sizeof(uve_hw_spec) / 4; -+ -+ memcpy((ib_cpu + len), uve_deblocking_filter, sizeof(uve_deblocking_filter)); -+ len += sizeof(uve_deblocking_filter) / 4; -+ -+ memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); -+ len += sizeof(uve_feedback_buffer) / 4; -+ ib_cpu[len++] = enc.fb.addr >> 32; -+ ib_cpu[len++] = enc.fb.addr; -+ ib_cpu[len++] = 0x00000003; -+ -+ memcpy((ib_cpu + len), uve_op_init_rc, sizeof(uve_op_init_rc)); -+ len += sizeof(uve_op_init_rc) / 4; - - r = submit(len, AMDGPU_HW_IP_UVD_ENC); - CU_ASSERT_EQUAL(r, 0); - -- free_resource(&sw_ctx); -+ free_resource(&enc.fb); - } - - static void amdgpu_cs_uvd_enc_encode(void) - { -- /* TODO */ -+ int len, r, i; -+ uint64_t luma_offset, chroma_offset; -+ uint32_t vbuf_size, bs_size = 0x154000, cpb_size; -+ unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; -+ vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; -+ cpb_size = vbuf_size * 10; -+ -+ if (family_id < AMDGPU_FAMILY_AI) -+ return; -+ -+ num_resources = 0; -+ alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM); -+ resources[num_resources++] = enc.fb.handle; -+ alloc_resource(&enc.bs, bs_size, AMDGPU_GEM_DOMAIN_VRAM); -+ resources[num_resources++] = enc.bs.handle; -+ alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); -+ resources[num_resources++] = enc.vbuf.handle; -+ alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); -+ resources[num_resources++] = enc.cpb.handle; -+ resources[num_resources++] = ib_handle; -+ -+ r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ memset(enc.vbuf.ptr, 0, vbuf_size); -+ for (i = 0; i < enc.height; ++i) { -+ memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width); -+ enc.vbuf.ptr += ALIGN(enc.width, align); -+ } -+ for (i = 0; i < enc.height / 2; ++i) { -+ memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width); -+ enc.vbuf.ptr += ALIGN(enc.width, align); -+ } -+ -+ r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ len = 0; -+ memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -+ len += sizeof(uve_session_info) / 4; -+ ib_cpu[len++] = enc.session.addr >> 32; -+ ib_cpu[len++] = enc.session.addr; -+ -+ memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -+ len += sizeof(uve_task_info) / 4; -+ ib_cpu[len++] = 0x00000210; -+ ib_cpu[len++] = 0x00000002; -+ ib_cpu[len++] = 0x00000001; -+ -+ memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header)); -+ len += sizeof(uve_slice_header) / 4; -+ -+ unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16); -+ luma_offset = enc.vbuf.addr; -+ chroma_offset = luma_offset + luma_size; -+ ib_cpu[len++] = 0x00000088; -+ ib_cpu[len++] = 0x0000000d; -+ ib_cpu[len++] = 0x00018000; -+ ib_cpu[len++] = luma_offset >> 32; -+ ib_cpu[len++] = luma_offset; -+ ib_cpu[len++] = chroma_offset >> 32; -+ ib_cpu[len++] = chroma_offset; -+ memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); -+ len += sizeof(uve_encode_param) / 4; -+ -+ memcpy((ib_cpu + len), uve_quality_param, sizeof(uve_quality_param)); -+ len += sizeof(uve_quality_param) / 4; -+ -+ memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh)); -+ len += sizeof(uve_intra_refresh) / 4; -+ -+ memcpy((ib_cpu + len), uve_reconstructed_pic_output, sizeof(uve_reconstructed_pic_output)); -+ len += sizeof(uve_reconstructed_pic_output) / 4; -+ -+ memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer)); -+ len += sizeof(uve_ctx_buffer) / 4; -+ ib_cpu[len++] = enc.cpb.addr >> 32; -+ ib_cpu[len++] = enc.cpb.addr; -+ -+ memcpy((ib_cpu + len), uve_bitstream_buffer, sizeof(uve_bitstream_buffer)); -+ len += sizeof(uve_bitstream_buffer) / 4; -+ ib_cpu[len++] = enc.bs.addr >> 32; -+ ib_cpu[len++] = enc.bs.addr; -+ ib_cpu[len++] = 0x00030000; -+ -+ memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); -+ len += sizeof(uve_feedback_buffer) / 4; -+ ib_cpu[len++] = enc.fb.addr >> 32; -+ ib_cpu[len++] = enc.fb.addr; -+ ib_cpu[len++] = 0x00000003; -+ -+ memcpy((ib_cpu + len), uve_rc_per_pic, sizeof(uve_rc_per_pic)); -+ len += sizeof(uve_rc_per_pic) / 4; -+ -+ memcpy((ib_cpu + len), uve_op_encode, sizeof(uve_op_encode)); -+ len += sizeof(uve_op_encode) / 4; -+ -+ r = submit(len, AMDGPU_HW_IP_UVD_ENC); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ check_result(&enc); -+ -+ free_resource(&enc.fb); -+ free_resource(&enc.bs); -+ free_resource(&enc.vbuf); -+ free_resource(&enc.cpb); - } - - static void amdgpu_cs_uvd_enc_destroy(void) -@@ -275,29 +482,25 @@ static void amdgpu_cs_uvd_enc_destroy(void) - return; - - num_resources = 0; -- alloc_resource(&sw_ctx, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); -- resources[num_resources++] = sw_ctx.handle; - resources[num_resources++] = ib_handle; - - len = 0; -- ib_cpu[len++] = 0x00000018; -- ib_cpu[len++] = 0x00000001; /* session info */ -- ib_cpu[len++] = 0x00000001; -- ib_cpu[len++] = 0x00000000; -- ib_cpu[len++] = sw_ctx.addr >> 32; -- ib_cpu[len++] = sw_ctx.addr; -+ memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -+ len += sizeof(uve_session_info) / 4; -+ ib_cpu[len++] = enc.session.addr >> 32; -+ ib_cpu[len++] = enc.session.addr; - -- ib_cpu[len++] = 0x00000014; -- ib_cpu[len++] = 0x00000002; /* task info */ -+ memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -+ len += sizeof(uve_task_info) / 4; - ib_cpu[len++] = 0xffffffff; -- ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = 0x00000004; - ib_cpu[len++] = 0x00000000; - -- ib_cpu[len++] = 0x00000008; -- ib_cpu[len++] = 0x08000002; /* op close session */ -+ memcpy((ib_cpu + len), uve_op_close, sizeof(uve_op_close)); -+ len += sizeof(uve_op_close) / 4; - - r = submit(len, AMDGPU_HW_IP_UVD_ENC); - CU_ASSERT_EQUAL(r, 0); - -- free_resource(&sw_ctx); -+ free_resource(&enc.session); - } --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch b/meta-v1000/recipes-graphics/drm/libdrm/0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch index 99f2f024..c0eeab0e 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch @@ -7,23 +7,23 @@ Subject: [PATCH 30/39] amdgpu: [hybrid] add a flag of memory allcation from Change-Id: I740c9f93a483b9cb728892963c7a0d6577819d59 Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 216caa2..dfa7837 100644 +index a8f0c14..eb6f00e 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -103,6 +103,8 @@ extern "C" { +@@ -112,6 +112,8 @@ extern "C" { /* Hybrid specific */ /* Flag that the memory should be in SPARSE resource */ - #define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) + #define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) +/* Flag that the memory allocation should be from top of domain */ -+#define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) ++#define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) /* Flag that the memory allocation should be pinned */ - #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) + #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch index 19fa1f93..31b235fd 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch @@ -10,20 +10,20 @@ Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- - amdgpu/amdgpu.h | 13 +++++++++++++ + amdgpu/amdgpu.h | 14 ++++++++++++++ amdgpu/amdgpu_cs.c | 28 ++++++++++++++++++++++++++++ - 2 files changed, 41 insertions(+) + 2 files changed, 42 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 0a3063f..ddd250f 100644 +index 3ca923d..220663a 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h -@@ -1645,6 +1645,19 @@ int amdgpu_cs_signal_sem(amdgpu_device_handle dev, - uint32_t ip_instance, - uint32_t ring, +@@ -1685,6 +1685,20 @@ int amdgpu_cs_signal_sem(amdgpu_device_handle dev, amdgpu_sem_handle sem); -+/** + + /** + * reserve vmid for this process + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() @@ -36,14 +36,16 @@ index 0a3063f..ddd250f 100644 + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + */ +int amdgpu_cs_unreserved_vmid(amdgpu_device_handle dev); - - /** ++ ++/** * wait sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 8570714..e38ecab 100644 +index c23ff24..6e6db0e 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c -@@ -730,6 +730,34 @@ int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, +@@ -739,6 +739,34 @@ int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, return 0; } @@ -75,9 +77,8 @@ index 8570714..e38ecab 100644 + return r; +} + - int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, - uint32_t *handle) - { + int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, + uint32_t flags, + uint32_t *handle) -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch b/meta-v1000/recipes-graphics/drm/libdrm/0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch index 4075363f..3babe504 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch @@ -9,23 +9,23 @@ Change-Id: Id52286984c8a43b77ad443799b267a6d0b23df54 Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- include/drm/amdgpu_drm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index dfa7837..8ced57d 100644 +index 4192dca..71261ab 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h -@@ -964,6 +964,8 @@ struct drm_amdgpu_virtual_range { +@@ -1020,6 +1020,8 @@ struct drm_amdgpu_virtual_range { #define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) /* query direct gma capability */ #define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1) +/* query ssg capability */ -+#define AMDGPU_CAPABILITY_SSG_FLAG (1 << 2) ++#define AMDGPU_CAPABILITY_SSG_FLAG (1 << 2) struct drm_amdgpu_capability { uint32_t flag; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0034-tests-amdgpu-bypass-UVD-CS-tests-on-raven.patch b/meta-v1000/recipes-graphics/drm/libdrm/0034-tests-amdgpu-bypass-UVD-CS-tests-on-raven.patch deleted file mode 100644 index 21f00d15..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0034-tests-amdgpu-bypass-UVD-CS-tests-on-raven.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 61e501aaf6fd4545d7242b829f25b984fabc787c Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Sat, 27 May 2017 13:40:45 +0800 -Subject: [PATCH 34/39] tests/amdgpu: bypass UVD CS tests on raven - -raven doesn't support UVD decode - -Change-Id: Ibc3a3a1b1007aaf7cf8de8b6ccd2457167f11fcb -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> ---- - tests/amdgpu/cs_tests.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index 081ec9c..df55c70 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -90,6 +90,11 @@ int suite_cs_tests_init(void) - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; - -+ if (family_id >= AMDGPU_FAMILY_RV) { -+ printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n"); -+ return CUE_SUCCESS; -+ } -+ - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; -@@ -114,6 +119,9 @@ int suite_cs_tests_clean(void) - { - int r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return CUE_SUCCESS; -+ - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) -@@ -192,6 +200,9 @@ static void amdgpu_cs_uvd_create(void) - void *msg; - int i, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - req.alloc_size = 4*1024; - req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - -@@ -263,6 +274,9 @@ static void amdgpu_cs_uvd_decode(void) - uint8_t *ptr; - int i, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - req.alloc_size = 4*1024; /* msg */ - req.alloc_size += 4*1024; /* fb */ - if (family_id >= AMDGPU_FAMILY_VI) -@@ -402,6 +416,9 @@ static void amdgpu_cs_uvd_destroy(void) - void *msg; - int i, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - req.alloc_size = 4*1024; - req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0035-tests-amdgpu-bypass-UVD-ENC-tests-on-raven.patch b/meta-v1000/recipes-graphics/drm/libdrm/0035-tests-amdgpu-bypass-UVD-ENC-tests-on-raven.patch deleted file mode 100644 index 40b49190..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0035-tests-amdgpu-bypass-UVD-ENC-tests-on-raven.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 609397c048f572c618756a8379eb6b7fda7228da Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Sat, 27 May 2017 14:13:51 +0800 -Subject: [PATCH 35/39] tests/amdgpu: bypass UVD ENC tests on raven - -raven doesn't support UVD encode - -Change-Id: Ib880f767ead72b8c7f392c20c01b756600c5eee7 -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> ---- - tests/amdgpu/uvd_enc_tests.c | 14 ++++++-------- - 1 file changed, 6 insertions(+), 8 deletions(-) - -diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c -index fee0112..f976443 100644 ---- a/tests/amdgpu/uvd_enc_tests.c -+++ b/tests/amdgpu/uvd_enc_tests.c -@@ -98,10 +98,8 @@ int suite_uvd_enc_tests_init(void) - - family_id = device_handle->info.family_id; - -- if (family_id < AMDGPU_FAMILY_AI) { -- -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { - printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n"); -- - return CUE_SUCCESS; - } - -@@ -123,7 +121,7 @@ int suite_uvd_enc_tests_clean(void) - { - int r; - -- if (family_id < AMDGPU_FAMILY_AI) { -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { - - r = amdgpu_device_deinitialize(device_handle); - if (r) -@@ -244,7 +242,7 @@ static void amdgpu_cs_uvd_enc_create(void) - { - int len, r; - -- if (family_id < AMDGPU_FAMILY_AI) -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - - enc.width = 160; -@@ -301,7 +299,7 @@ static void amdgpu_cs_uvd_enc_session_init(void) - { - int len, r; - -- if (family_id < AMDGPU_FAMILY_AI) -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - - num_resources = 0; -@@ -372,7 +370,7 @@ static void amdgpu_cs_uvd_enc_encode(void) - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; - cpb_size = vbuf_size * 10; - -- if (family_id < AMDGPU_FAMILY_AI) -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - - num_resources = 0; -@@ -478,7 +476,7 @@ static void amdgpu_cs_uvd_enc_destroy(void) - struct amdgpu_uvd_enc_bo sw_ctx; - int len, r; - -- if (family_id < AMDGPU_FAMILY_AI) -+ if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - - num_resources = 0; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0036-tests-amdgpu-bypass-VCE-tests-on-raven.patch b/meta-v1000/recipes-graphics/drm/libdrm/0036-tests-amdgpu-bypass-VCE-tests-on-raven.patch deleted file mode 100644 index 860c842b..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0036-tests-amdgpu-bypass-VCE-tests-on-raven.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 3e67d0660c38c0fc71287e92fc47ea228294e09f Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Sat, 27 May 2017 14:49:19 +0800 -Subject: [PATCH 36/39] tests/amdgpu: bypass VCE tests on raven - -raven doesn't support VCE - -Change-Id: I5f511cd0ca4bcd8114eba16bc35892385453f98b -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> ---- - tests/amdgpu/vce_tests.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c -index b03807b..8d61a3b 100644 ---- a/tests/amdgpu/vce_tests.c -+++ b/tests/amdgpu/vce_tests.c -@@ -106,6 +106,11 @@ int suite_vce_tests_init(void) - family_id = device_handle->info.family_id; - vce_harvest_config = device_handle->info.vce_harvest_config; - -+ if (family_id >= AMDGPU_FAMILY_RV) { -+ printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n"); -+ return CUE_SUCCESS; -+ } -+ - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; -@@ -126,6 +131,9 @@ int suite_vce_tests_clean(void) - { - int r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return CUE_SUCCESS; -+ - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) -@@ -237,6 +245,9 @@ static void amdgpu_cs_vce_create(void) - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int len, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - enc.width = vce_create[6]; - enc.height = vce_create[7]; - -@@ -430,6 +441,9 @@ static void amdgpu_cs_vce_encode(void) - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int i, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; - cpb_size = vbuf_size * 10; - num_resources = 0; -@@ -508,6 +522,9 @@ static void amdgpu_cs_vce_destroy(void) - { - int len, r; - -+ if (family_id >= AMDGPU_FAMILY_RV) -+ return; -+ - num_resources = 0; - alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.fb[0].handle; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch b/meta-v1000/recipes-graphics/drm/libdrm/0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch index b9c2a334..77db36a1 100644 --- a/meta-v1000/recipes-graphics/drm/libdrm/0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch +++ b/meta-v1000/recipes-graphics/drm/libdrm/0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch @@ -7,12 +7,13 @@ Change-Id: I75c5a189a5046b0f56808a60da2f3b34f45e5dab Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> --- tests/amdgpu/bo_tests.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 930a073..52c9fae 100644 +index 58a00ec..8a7baed 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c @@ -27,6 +27,9 @@ @@ -25,27 +26,26 @@ index 930a073..52c9fae 100644 #include "CUnit/Basic.h" -@@ -49,6 +52,7 @@ static void amdgpu_bo_metadata(void); - static void amdgpu_bo_map_unmap(void); +@@ -51,6 +54,7 @@ static void amdgpu_memory_alloc(void); + static void amdgpu_mem_fail_alloc(void); static void amdgpu_get_fb_id_and_handle(void); static void amdgpu_bo_direct_gma(void); +static void amdgpu_bo_ssg(void); CU_TestInfo bo_tests[] = { { "Export/Import", amdgpu_bo_export_import }, -@@ -58,6 +62,7 @@ CU_TestInfo bo_tests[] = { - { "CPU map/unmap", amdgpu_bo_map_unmap }, +@@ -60,6 +64,7 @@ CU_TestInfo bo_tests[] = { + { "Memory fail alloc Test", amdgpu_mem_fail_alloc }, { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, { "Direct GMA", amdgpu_bo_direct_gma }, + { "SSG", amdgpu_bo_ssg }, CU_TEST_INFO_NULL, }; -@@ -279,3 +284,105 @@ static void amdgpu_bo_direct_gma(void) - } +@@ -282,6 +287,108 @@ static void amdgpu_bo_direct_gma(void) } } -+ + +static void amdgpu_bo_ssg(void) +{ + struct drm_amdgpu_capability cap; @@ -147,6 +147,9 @@ index 930a073..52c9fae 100644 + + amdgpu_bo_free(buf_handle); +} ++ + static void amdgpu_memory_alloc(void) + { + amdgpu_bo_handle bo; -- 2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0038-amdgpu-Add-gpu-always-on-cu-bitmap.patch b/meta-v1000/recipes-graphics/drm/libdrm/0038-amdgpu-Add-gpu-always-on-cu-bitmap.patch deleted file mode 100644 index 19657f5b..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0038-amdgpu-Add-gpu-always-on-cu-bitmap.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 23eabb22a441292a989a6d60bf806b9a655659f2 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Wed, 28 Jun 2017 13:31:57 +0800 -Subject: [PATCH 38/39] amdgpu: Add gpu always on cu bitmap -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I8353678c3f74e71af4928dc863b41c92d4dff2ab -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - include/drm/amdgpu_drm.h | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 8ced57d..8881a4e 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -842,6 +842,7 @@ struct drm_amdgpu_info_device { - __u64 max_memory_clock; - /* cu information */ - __u32 cu_active_number; -+ /* NOTE: cu_ao_mask is INVALID, DON'T use it */ - __u32 cu_ao_mask; - __u32 cu_bitmap[4][4]; - /** Render backend pipe mask. One render backend is CB+DB. */ -@@ -896,6 +897,8 @@ struct drm_amdgpu_info_device { - /* max gs wavefront per vgt*/ - __u32 max_gs_waves_per_vgt; - __u32 _pad1; -+ /* always on cu bitmap */ -+ __u32 cu_ao_bitmap[4][4]; - }; - - struct drm_amdgpu_info_hw_ip { --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0039-test-amdgpu-fix-test-failure-for-SI.patch b/meta-v1000/recipes-graphics/drm/libdrm/0039-test-amdgpu-fix-test-failure-for-SI.patch deleted file mode 100644 index 0d2872b9..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0039-test-amdgpu-fix-test-failure-for-SI.patch +++ /dev/null @@ -1,675 +0,0 @@ -From 66f95d615faca3ce857e59e3c06ee9469be942a8 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Wed, 19 Jul 2017 10:52:33 +0800 -Subject: [PATCH 39/39] test/amdgpu: fix test failure for SI - -Change-Id: I646f1bf844bd92962b9f71aa287f90173ae233c6 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - tests/amdgpu/basic_tests.c | 273 ++++++++++++++++++++++++++++++--------------- - tests/amdgpu/cs_tests.c | 41 +++---- - tests/amdgpu/vce_tests.c | 41 +++---- - 3 files changed, 229 insertions(+), 126 deletions(-) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 1807538..c767f7e 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -40,6 +40,7 @@ - static amdgpu_device_handle device_handle; - static uint32_t major_version; - static uint32_t minor_version; -+static uint32_t family_id; - - static void amdgpu_query_info_test(void); - static void amdgpu_memory_alloc(void); -@@ -206,22 +207,56 @@ CU_TestInfo basic_tests[] = { - # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) - # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) - -+#define SDMA_PACKET_SI(op, b, t, s, cnt) ((((op) & 0xF) << 28) | \ -+ (((b) & 0x1) << 26) | \ -+ (((t) & 0x1) << 23) | \ -+ (((s) & 0x1) << 22) | \ -+ (((cnt) & 0xFFFFF) << 0)) -+#define SDMA_OPCODE_COPY_SI 3 -+#define SDMA_OPCODE_CONSTANT_FILL_SI 13 -+#define SDMA_NOP_SI 0xf -+#define GFX_COMPUTE_NOP_SI 0x80000000 -+#define PACKET3_DMA_DATA_SI 0x41 -+# define PACKET3_DMA_DATA_SI_ENGINE(x) ((x) << 27) -+ /* 0 - ME -+ * 1 - PFP -+ */ -+# define PACKET3_DMA_DATA_SI_DST_SEL(x) ((x) << 20) -+ /* 0 - DST_ADDR using DAS -+ * 1 - GDS -+ * 3 - DST_ADDR using L2 -+ */ -+# define PACKET3_DMA_DATA_SI_SRC_SEL(x) ((x) << 29) -+ /* 0 - SRC_ADDR using SAS -+ * 1 - GDS -+ * 2 - DATA -+ * 3 - SRC_ADDR using L2 -+ */ -+# define PACKET3_DMA_DATA_SI_CP_SYNC (1 << 31) -+ - int suite_basic_tests_init(void) - { -+ struct amdgpu_gpu_info gpu_info = {0}; - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - -- if (r == 0) -- return CUE_SUCCESS; -- else { -+ if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - return CUE_SINIT_FAILED; - } -+ -+ r = amdgpu_query_gpu_info(device_handle, &gpu_info); -+ if (r) -+ return CUE_SINIT_FAILED; -+ -+ family_id = gpu_info.family_id; -+ -+ return CUE_SUCCESS; - } - - int suite_basic_tests_clean(void) -@@ -308,7 +343,7 @@ static void amdgpu_command_submission_gfx_separate_ibs(void) - uint32_t expired; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle, va_handle_ce; -- int r; -+ int r, i = 0; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); -@@ -333,12 +368,14 @@ static void amdgpu_command_submission_gfx_separate_ibs(void) - - /* IT_SET_CE_DE_COUNTERS */ - ptr = ib_result_ce_cpu; -- ptr[0] = 0xc0008900; -- ptr[1] = 0; -- ptr[2] = 0xc0008400; -- ptr[3] = 1; -+ if (family_id != AMDGPU_FAMILY_SI) { -+ ptr[i++] = 0xc0008900; -+ ptr[i++] = 0; -+ } -+ ptr[i++] = 0xc0008400; -+ ptr[i++] = 1; - ib_info[0].ib_mc_address = ib_result_ce_mc_address; -- ib_info[0].size = 4; -+ ib_info[0].size = i; - ib_info[0].flags = AMDGPU_IB_FLAG_CE; - - /* IT_WAIT_ON_CE_COUNTER */ -@@ -397,7 +434,7 @@ static void amdgpu_command_submission_gfx_shared_ib(void) - uint32_t expired; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; -- int r; -+ int r, i = 0; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); -@@ -416,12 +453,14 @@ static void amdgpu_command_submission_gfx_shared_ib(void) - - /* IT_SET_CE_DE_COUNTERS */ - ptr = ib_result_cpu; -- ptr[0] = 0xc0008900; -- ptr[1] = 0; -- ptr[2] = 0xc0008400; -- ptr[3] = 1; -+ if (family_id != AMDGPU_FAMILY_SI) { -+ ptr[i++] = 0xc0008900; -+ ptr[i++] = 0; -+ } -+ ptr[i++] = 0xc0008400; -+ ptr[i++] = 1; - ib_info[0].ib_mc_address = ib_result_mc_address; -- ib_info[0].size = 4; -+ ib_info[0].size = i; - ib_info[0].flags = AMDGPU_IB_FLAG_CE; - - ptr = (uint32_t *)ib_result_cpu + 4; -@@ -502,12 +541,21 @@ static void amdgpu_semaphore_test(void) - struct amdgpu_cs_fence fence_status = {0}; - uint32_t *ptr; - uint32_t expired; -+ uint32_t sdma_nop, gfx_nop; - amdgpu_bo_list_handle bo_list[2]; - amdgpu_va_handle va_handle[2]; - amdgpu_sem_handle sem_handle, sem_handle_import; - int fd; - int r, i; - -+ if (family_id == AMDGPU_FAMILY_SI) { -+ sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0); -+ gfx_nop = GFX_COMPUTE_NOP_SI; -+ } else { -+ sdma_nop = SDMA_PKT_HEADER_OP(SDMA_NOP); -+ gfx_nop = GFX_COMPUTE_NOP; -+ } -+ - r = amdgpu_cs_create_semaphore(&sem); - CU_ASSERT_EQUAL(r, 0); - for (i = 0; i < 2; i++) { -@@ -527,7 +575,7 @@ static void amdgpu_semaphore_test(void) - - /* 1. same context different engine */ - ptr = ib_result_cpu[0]; -- ptr[0] = SDMA_NOP; -+ ptr[0] = sdma_nop; - ib_info[0].ib_mc_address = ib_result_mc_address[0]; - ib_info[0].size = 1; - -@@ -544,7 +592,7 @@ static void amdgpu_semaphore_test(void) - r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); - CU_ASSERT_EQUAL(r, 0); - ptr = ib_result_cpu[1]; -- ptr[0] = GFX_COMPUTE_NOP; -+ ptr[0] = gfx_nop; - ib_info[1].ib_mc_address = ib_result_mc_address[1]; - ib_info[1].size = 1; - -@@ -568,7 +616,7 @@ static void amdgpu_semaphore_test(void) - - /* 2. same engine different context */ - ptr = ib_result_cpu[0]; -- ptr[0] = GFX_COMPUTE_NOP; -+ ptr[0] = gfx_nop; - ib_info[0].ib_mc_address = ib_result_mc_address[0]; - ib_info[0].size = 1; - -@@ -585,7 +633,7 @@ static void amdgpu_semaphore_test(void) - r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem); - CU_ASSERT_EQUAL(r, 0); - ptr = ib_result_cpu[1]; -- ptr[0] = GFX_COMPUTE_NOP; -+ ptr[0] = gfx_nop; - ib_info[1].ib_mc_address = ib_result_mc_address[1]; - ib_info[1].size = 1; - -@@ -612,7 +660,7 @@ static void amdgpu_semaphore_test(void) - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu[0]; -- ptr[0] = SDMA_NOP; -+ ptr[0] = sdma_nop; - ib_info[0].ib_mc_address = ib_result_mc_address[0]; - ib_info[0].size = 1; - -@@ -639,7 +687,7 @@ static void amdgpu_semaphore_test(void) - r = amdgpu_cs_wait_sem(device_handle, context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem_handle_import); - CU_ASSERT_EQUAL(r, 0); - ptr = ib_result_cpu[1]; -- ptr[0] = GFX_COMPUTE_NOP; -+ ptr[0] = gfx_nop; - ib_info[1].ib_mc_address = ib_result_mc_address[1]; - ib_info[1].size = 1; - -@@ -694,11 +742,15 @@ static void amdgpu_command_submission_compute_nop(void) - int i, r, instance; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; -+ struct drm_amdgpu_info_hw_ip info; -+ -+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info); -+ CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - -- for (instance = 0; instance < 8; instance++) { -+ for (instance = 0; (1 << instance) & info.available_rings; instance++) { - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, -@@ -710,8 +762,8 @@ static void amdgpu_command_submission_compute_nop(void) - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; -- for (i = 0; i < 16; ++i) -- ptr[i] = 0xffff1000; -+ memset(ptr, 0, 16); -+ ptr[0]=PACKET3(PACKET3_NOP, 14); - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; -@@ -872,16 +924,12 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; -- struct amdgpu_gpu_info gpu_info = {0}; - uint64_t bo_mc; - volatile uint32_t *bo_cpu; - int i, j, r, loop; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle va_handle; - -- r = amdgpu_query_gpu_info(device_handle, &gpu_info); -- CU_ASSERT_EQUAL(r, 0); -- - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - -@@ -917,13 +965,17 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) - /* fulfill PM4: test DMA write-linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { -- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, -- SDMA_WRITE_SUB_OPCODE_LINEAR, 0); -+ if (family_id == AMDGPU_FAMILY_SI) -+ pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, -+ sdma_write_length); -+ else -+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, -+ SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -- if (gpu_info.family_id >= AMDGPU_FAMILY_AI) -+ if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; -- else -+ else if (family_id != AMDGPU_FAMILY_SI) - pm4[i++] = sdma_write_length; - while(j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; -@@ -980,16 +1032,12 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; -- struct amdgpu_gpu_info gpu_info = {0}; - uint64_t bo_mc; - volatile uint32_t *bo_cpu; - int i, j, r, loop; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle va_handle; - -- r = amdgpu_query_gpu_info(device_handle, &gpu_info); -- CU_ASSERT_EQUAL(r, 0); -- - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - -@@ -1024,27 +1072,47 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) - /* fulfill PM4: test DMA const fill */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { -- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, -- SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); -- pm4[i++] = 0xffffffff & bo_mc; -- pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -- pm4[i++] = 0xdeadbeaf; -- if (gpu_info.family_id >= AMDGPU_FAMILY_AI) -- pm4[i++] = sdma_write_length - 1; -- else -- pm4[i++] = sdma_write_length; -+ if (family_id == AMDGPU_FAMILY_SI) { -+ pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI, 0, 0, 0, -+ sdma_write_length / 4); -+ pm4[i++] = 0xfffffffc & bo_mc; -+ pm4[i++] = 0xdeadbeaf; -+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16; -+ } else { -+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, -+ SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); -+ pm4[i++] = 0xffffffff & bo_mc; -+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -+ pm4[i++] = 0xdeadbeaf; -+ if (family_id >= AMDGPU_FAMILY_AI) -+ pm4[i++] = sdma_write_length - 1; -+ else -+ pm4[i++] = sdma_write_length; -+ } - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { -- pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); -- pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | -- PACKET3_DMA_DATA_DST_SEL(0) | -- PACKET3_DMA_DATA_SRC_SEL(2) | -- PACKET3_DMA_DATA_CP_SYNC; -- pm4[i++] = 0xdeadbeaf; -- pm4[i++] = 0; -- pm4[i++] = 0xfffffffc & bo_mc; -- pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -- pm4[i++] = sdma_write_length; -+ if (family_id == AMDGPU_FAMILY_SI) { -+ pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); -+ pm4[i++] = 0xdeadbeaf; -+ pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | -+ PACKET3_DMA_DATA_SI_DST_SEL(0) | -+ PACKET3_DMA_DATA_SI_SRC_SEL(2) | -+ PACKET3_DMA_DATA_SI_CP_SYNC; -+ pm4[i++] = 0xffffffff & bo_mc; -+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -+ pm4[i++] = sdma_write_length; -+ } else { -+ pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); -+ pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | -+ PACKET3_DMA_DATA_DST_SEL(0) | -+ PACKET3_DMA_DATA_SRC_SEL(2) | -+ PACKET3_DMA_DATA_CP_SYNC; -+ pm4[i++] = 0xdeadbeaf; -+ pm4[i++] = 0; -+ pm4[i++] = 0xfffffffc & bo_mc; -+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -+ pm4[i++] = sdma_write_length; -+ } - } - - amdgpu_test_exec_cs_helper(context_handle, -@@ -1090,16 +1158,12 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; -- struct amdgpu_gpu_info gpu_info = {0}; - uint64_t bo1_mc, bo2_mc; - volatile unsigned char *bo1_cpu, *bo2_cpu; - int i, j, r, loop1, loop2; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle bo1_va_handle, bo2_va_handle; - -- r = amdgpu_query_gpu_info(device_handle, &gpu_info); -- CU_ASSERT_EQUAL(r, 0); -- - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - -@@ -1150,28 +1214,51 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) - /* fulfill PM4: test DMA copy linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { -- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); -- if (gpu_info.family_id >= AMDGPU_FAMILY_AI) -- pm4[i++] = sdma_write_length - 1; -- else -- pm4[i++] = sdma_write_length; -- pm4[i++] = 0; -- pm4[i++] = 0xffffffff & bo1_mc; -- pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -- pm4[i++] = 0xffffffff & bo2_mc; -- pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ if (family_id == AMDGPU_FAMILY_SI) { -+ pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, -+ sdma_write_length); -+ pm4[i++] = 0xffffffff & bo2_mc; -+ pm4[i++] = 0xffffffff & bo1_mc; -+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -+ } else { -+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); -+ if (family_id >= AMDGPU_FAMILY_AI) -+ pm4[i++] = sdma_write_length - 1; -+ else -+ pm4[i++] = sdma_write_length; -+ pm4[i++] = 0; -+ pm4[i++] = 0xffffffff & bo1_mc; -+ pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -+ pm4[i++] = 0xffffffff & bo2_mc; -+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ } -+ - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { -- pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); -- pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | -- PACKET3_DMA_DATA_DST_SEL(0) | -- PACKET3_DMA_DATA_SRC_SEL(0) | -- PACKET3_DMA_DATA_CP_SYNC; -- pm4[i++] = 0xfffffffc & bo1_mc; -- pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -- pm4[i++] = 0xfffffffc & bo2_mc; -- pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -- pm4[i++] = sdma_write_length; -+ if (family_id == AMDGPU_FAMILY_SI) { -+ pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); -+ pm4[i++] = 0xfffffffc & bo1_mc; -+ pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | -+ PACKET3_DMA_DATA_SI_DST_SEL(0) | -+ PACKET3_DMA_DATA_SI_SRC_SEL(0) | -+ PACKET3_DMA_DATA_SI_CP_SYNC | -+ (0xffff00000000 & bo1_mc) >> 32; -+ pm4[i++] = 0xfffffffc & bo2_mc; -+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ pm4[i++] = sdma_write_length; -+ } else { -+ pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); -+ pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | -+ PACKET3_DMA_DATA_DST_SEL(0) | -+ PACKET3_DMA_DATA_SRC_SEL(0) | -+ PACKET3_DMA_DATA_CP_SYNC; -+ pm4[i++] = 0xfffffffc & bo1_mc; -+ pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -+ pm4[i++] = 0xfffffffc & bo2_mc; -+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; -+ pm4[i++] = sdma_write_length; -+ } - } - - amdgpu_test_exec_cs_helper(context_handle, -@@ -1232,7 +1319,7 @@ static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle, va_handle_ce; - int r; -- int i, ib_cs_num = 2; -+ int i = 0, ib_cs_num = 2; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); -@@ -1257,12 +1344,14 @@ static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) - - /* IT_SET_CE_DE_COUNTERS */ - ptr = ib_result_ce_cpu; -- ptr[0] = 0xc0008900; -- ptr[1] = 0; -- ptr[2] = 0xc0008400; -- ptr[3] = 1; -+ if (family_id != AMDGPU_FAMILY_SI) { -+ ptr[i++] = 0xc0008900; -+ ptr[i++] = 0; -+ } -+ ptr[i++] = 0xc0008400; -+ ptr[i++] = 1; - ib_info[0].ib_mc_address = ib_result_ce_mc_address; -- ib_info[0].size = 4; -+ ib_info[0].size = i; - ib_info[0].flags = AMDGPU_IB_FLAG_CE; - - /* IT_WAIT_ON_CE_COUNTER */ -@@ -1363,11 +1452,19 @@ static void amdgpu_userptr_test(void) - handle = buf_handle; - - j = i = 0; -- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, -- SDMA_WRITE_SUB_OPCODE_LINEAR, 0); -+ -+ if (family_id == AMDGPU_FAMILY_SI) -+ pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, -+ sdma_write_length); -+ else -+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, -+ SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; -- pm4[i++] = sdma_write_length; -+ if (family_id >= AMDGPU_FAMILY_AI) -+ pm4[i++] = sdma_write_length - 1; -+ else if (family_id != AMDGPU_FAMILY_SI) -+ pm4[i++] = sdma_write_length; - - while (j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index df55c70..3b2f17d 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -90,7 +90,7 @@ int suite_cs_tests_init(void) - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; - -- if (family_id >= AMDGPU_FAMILY_RV) { -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { - printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n"); - return CUE_SUCCESS; - } -@@ -119,21 +119,24 @@ int suite_cs_tests_clean(void) - { - int r; - -- if (family_id >= AMDGPU_FAMILY_RV) -- return CUE_SUCCESS; -- -- r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -- ib_mc_address, IB_SIZE); -- if (r) -- return CUE_SCLEAN_FAILED; -- -- r = amdgpu_cs_ctx_free(context_handle); -- if (r) -- return CUE_SCLEAN_FAILED; -- -- r = amdgpu_device_deinitialize(device_handle); -- if (r) -- return CUE_SCLEAN_FAILED; -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } else { -+ r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -+ ib_mc_address, IB_SIZE); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_cs_ctx_free(context_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } - - return CUE_SUCCESS; - } -@@ -200,7 +203,7 @@ static void amdgpu_cs_uvd_create(void) - void *msg; - int i, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - req.alloc_size = 4*1024; -@@ -274,7 +277,7 @@ static void amdgpu_cs_uvd_decode(void) - uint8_t *ptr; - int i, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - req.alloc_size = 4*1024; /* msg */ -@@ -416,7 +419,7 @@ static void amdgpu_cs_uvd_destroy(void) - void *msg; - int i, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - req.alloc_size = 4*1024; -diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c -index 8d61a3b..cf44c13 100644 ---- a/tests/amdgpu/vce_tests.c -+++ b/tests/amdgpu/vce_tests.c -@@ -106,7 +106,7 @@ int suite_vce_tests_init(void) - family_id = device_handle->info.family_id; - vce_harvest_config = device_handle->info.vce_harvest_config; - -- if (family_id >= AMDGPU_FAMILY_RV) { -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { - printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n"); - return CUE_SUCCESS; - } -@@ -131,21 +131,24 @@ int suite_vce_tests_clean(void) - { - int r; - -- if (family_id >= AMDGPU_FAMILY_RV) -- return CUE_SUCCESS; -- -- r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -- ib_mc_address, IB_SIZE); -- if (r) -- return CUE_SCLEAN_FAILED; -- -- r = amdgpu_cs_ctx_free(context_handle); -- if (r) -- return CUE_SCLEAN_FAILED; -- -- r = amdgpu_device_deinitialize(device_handle); -- if (r) -- return CUE_SCLEAN_FAILED; -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } else { -+ r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, -+ ib_mc_address, IB_SIZE); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_cs_ctx_free(context_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ -+ r = amdgpu_device_deinitialize(device_handle); -+ if (r) -+ return CUE_SCLEAN_FAILED; -+ } - - return CUE_SUCCESS; - } -@@ -245,7 +248,7 @@ static void amdgpu_cs_vce_create(void) - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int len, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - enc.width = vce_create[6]; -@@ -441,7 +444,7 @@ static void amdgpu_cs_vce_encode(void) - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int i, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; -@@ -522,7 +525,7 @@ static void amdgpu_cs_vce_destroy(void) - { - int len, r; - -- if (family_id >= AMDGPU_FAMILY_RV) -+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - - num_resources = 0; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0040-drm-fix-missing-mutex-unlock-before-return.patch b/meta-v1000/recipes-graphics/drm/libdrm/0040-drm-fix-missing-mutex-unlock-before-return.patch deleted file mode 100644 index 8420eee4..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0040-drm-fix-missing-mutex-unlock-before-return.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 8649ecc02c75f70bcc7bcc38fa2bd55da43c86f3 Mon Sep 17 00:00:00 2001 -From: Monk Liu <monk.liu@amd.com> -Date: Mon, 7 Aug 2017 22:25:35 +0800 -Subject: [PATCH 40/46] drm: fix missing mutex unlock before return -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I377dde976648d53bc9a3a2d5ba294c284910b109 -Signed-off-by: Monk Liu <monk.liu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> -Acked-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_bo.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 9534c40..76126a2 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -304,6 +304,7 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - /* Get a KMS handle. */ - r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle); - if (r) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); - return r; - } - --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0041-drm-fix-race-issue-between-two-bo-functions-v2.patch b/meta-v1000/recipes-graphics/drm/libdrm/0041-drm-fix-race-issue-between-two-bo-functions-v2.patch deleted file mode 100644 index 26d8af22..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0041-drm-fix-race-issue-between-two-bo-functions-v2.patch +++ /dev/null @@ -1,83 +0,0 @@ -From ce2f6104799cca43993e831c889ded27af877a25 Mon Sep 17 00:00:00 2001 -From: Monk Liu <monk.liu@amd.com> -Date: Mon, 7 Aug 2017 22:27:10 +0800 -Subject: [PATCH 41/46] drm:fix race issue between two bo functions(v2) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -there is race issue between two threads on amdgpu_bo_reference and -amdgpu_bo_import, this patch tends to fix it by moving the -pthread_mutex_lock out of bo_free_internal and move to bo_reference -to cover the update_reference part. - -The mutex_unlock in bo_import should also cover bo refcount -increasement. - -Change-Id: I1f65eacf74cd28cc0d3a71ef2f7a19b890d63c29 -Signed-off-by: Monk Liu <monk.liu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> -Acked-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_bo.c | 5 +---- - amdgpu/amdgpu_internal.h | 13 +++++++++++-- - 2 files changed, 12 insertions(+), 6 deletions(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 76126a2..09028c7 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -57,14 +57,12 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle dev, - drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo) - { - /* Remove the buffer from the hash tables. */ -- pthread_mutex_lock(&bo->dev->bo_table_mutex); - util_hash_table_remove(bo->dev->bo_handles, - (void*)(uintptr_t)bo->handle); - if (bo->flink_name) { - util_hash_table_remove(bo->dev->bo_flink_names, - (void*)(uintptr_t)bo->flink_name); - } -- pthread_mutex_unlock(&bo->dev->bo_table_mutex); - - /* Release CPU access. */ - if (bo->cpu_map_count > 0) { -@@ -344,10 +342,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - } - - if (bo) { -- pthread_mutex_unlock(&dev->bo_table_mutex); -- - /* The buffer already exists, just bump the refcount. */ - atomic_inc(&bo->refcount); -+ pthread_mutex_unlock(&dev->bo_table_mutex); - - output->buf_handle = bo; - output->alloc_size = bo->alloc_size; -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index b39f47a..d7a3d50 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -238,8 +238,17 @@ static inline bool update_references(atomic_t *dst, atomic_t *src) - static inline void amdgpu_bo_reference(struct amdgpu_bo **dst, - struct amdgpu_bo *src) - { -- if (update_references(&(*dst)->refcount, &src->refcount)) -- amdgpu_bo_free_internal(*dst); -+ pthread_mutex_t *mlock; -+ struct amdgpu_bo* bo = *dst; -+ -+ assert(bo != NULL); -+ mlock = &bo->dev->bo_table_mutex; -+ pthread_mutex_lock(mlock); -+ -+ if (update_references(&bo->refcount, src ? &src->refcount : NULL)) -+ amdgpu_bo_free_internal(bo); -+ -+ pthread_mutex_unlock(mlock); - *dst = src; - } - --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0042-amdgpu-fix-potential-deadlock.patch b/meta-v1000/recipes-graphics/drm/libdrm/0042-amdgpu-fix-potential-deadlock.patch deleted file mode 100644 index 0f8ba2f9..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0042-amdgpu-fix-potential-deadlock.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 9f8b9e8733f123afd7589314cdb6afc9944b19ae Mon Sep 17 00:00:00 2001 -From: Monk Liu <Monk.Liu@amd.com> -Date: Tue, 8 Aug 2017 16:16:29 +0800 -Subject: [PATCH 42/46] amdgpu:fix potential deadlock - -deadlock could occure between cpu mutex lock and -bo table mutex lock, this patch avoid it. - -Change-Id: I083e402dde48f02a8ee196e59aa0cab80849fc18 -Signed-off-by: Monk Liu <Monk.Liu@amd.com> -Acked-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_bo.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 09028c7..c973a0d 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -673,10 +673,10 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) - pthread_mutex_unlock(&bo->cpu_access_mutex); - return -errno; - } -- amdgpu_add_handle_to_table(bo); - bo->cpu_ptr = ptr; - bo->cpu_map_count = 1; - pthread_mutex_unlock(&bo->cpu_access_mutex); -+ amdgpu_add_handle_to_table(bo); - - *cpu = ptr; - return 0; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0043-Revert-amdgpu-fix-potential-deadlock.patch b/meta-v1000/recipes-graphics/drm/libdrm/0043-Revert-amdgpu-fix-potential-deadlock.patch deleted file mode 100644 index 1048cf31..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0043-Revert-amdgpu-fix-potential-deadlock.patch +++ /dev/null @@ -1,33 +0,0 @@ -From b470ecceb52b526260b0e34ee0017332a77b283c Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Thu, 10 Aug 2017 15:13:07 +0800 -Subject: [PATCH 43/46] Revert "amdgpu:fix potential deadlock" - -This reverts commit eaea24b7acfb8d2cb1db8baa8f353d9fcc69a2b6. - -The reverted commit is submitted by mistaken. - -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_bo.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index c973a0d..09028c7 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -673,10 +673,10 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) - pthread_mutex_unlock(&bo->cpu_access_mutex); - return -errno; - } -+ amdgpu_add_handle_to_table(bo); - bo->cpu_ptr = ptr; - bo->cpu_map_count = 1; - pthread_mutex_unlock(&bo->cpu_access_mutex); -- amdgpu_add_handle_to_table(bo); - - *cpu = ptr; - return 0; --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0045-amdgpu-merge-and-cleanup-amdgpu_bo_free.patch b/meta-v1000/recipes-graphics/drm/libdrm/0045-amdgpu-merge-and-cleanup-amdgpu_bo_free.patch deleted file mode 100644 index 60a3b53f..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0045-amdgpu-merge-and-cleanup-amdgpu_bo_free.patch +++ /dev/null @@ -1,143 +0,0 @@ -From 9cdb2d8f7e3a3ea21a677a8c9160c69dc968ad0b Mon Sep 17 00:00:00 2001 -From: Monk Liu <monk.liu@amd.com> -Date: Tue, 8 Aug 2017 12:09:07 -0400 -Subject: [PATCH 45/46] amdgpu: merge and cleanup amdgpu_bo_free -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -since bo_reference and bo_internal_free are -all only used by bo_free, so we just merge them -together - -Change-Id: I01355e7d450b075458b946717d5bddfa0a0c2d3c -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Monk Liu <monk.liu@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - amdgpu/amdgpu_bo.c | 52 +++++++++++++++++++++++++++--------------------- - amdgpu/amdgpu_internal.h | 33 ------------------------------ - 2 files changed, 29 insertions(+), 56 deletions(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 1d90e5e..57aaf97 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -54,27 +54,6 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle dev, - drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &args); - } - --drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo) --{ -- /* Remove the buffer from the hash tables. */ -- util_hash_table_remove(bo->dev->bo_handles, -- (void*)(uintptr_t)bo->handle); -- if (bo->flink_name) { -- util_hash_table_remove(bo->dev->bo_flink_names, -- (void*)(uintptr_t)bo->flink_name); -- } -- -- /* Release CPU access. */ -- if (bo->cpu_map_count > 0) { -- bo->cpu_map_count = 1; -- amdgpu_bo_cpu_unmap(bo); -- } -- -- amdgpu_close_kms_handle(bo->dev, bo->handle); -- pthread_mutex_destroy(&bo->cpu_access_mutex); -- free(bo); --} -- - int amdgpu_bo_alloc(amdgpu_device_handle dev, - struct amdgpu_bo_alloc_request *alloc_buffer, - amdgpu_bo_handle *buf_handle) -@@ -623,8 +602,35 @@ int amdgpu_bo_get_phys_address(amdgpu_bo_handle buf_handle, - - int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - { -- /* Just drop the reference. */ -- amdgpu_bo_reference(&buf_handle, NULL); -+ struct amdgpu_device *dev; -+ struct amdgpu_bo *bo = buf_handle; -+ -+ assert(bo != NULL); -+ dev = bo->dev; -+ pthread_mutex_lock(&dev->bo_table_mutex); -+ -+ if (update_references(&bo->refcount, NULL)) { -+ /* Remove the buffer from the hash tables. */ -+ util_hash_table_remove(dev->bo_handles, -+ (void*)(uintptr_t)bo->handle); -+ -+ if (bo->flink_name) { -+ util_hash_table_remove(dev->bo_flink_names, -+ (void*)(uintptr_t)bo->flink_name); -+ } -+ -+ /* Release CPU access. */ -+ if (bo->cpu_map_count > 0) { -+ bo->cpu_map_count = 1; -+ amdgpu_bo_cpu_unmap(bo); -+ } -+ -+ amdgpu_close_kms_handle(dev, bo->handle); -+ pthread_mutex_destroy(&bo->cpu_access_mutex); -+ free(bo); -+ } -+ -+ pthread_mutex_unlock(&dev->bo_table_mutex); - return 0; - } - -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index d7a3d50..fd522f3 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -161,8 +161,6 @@ struct amdgpu_semaphore { - * Functions. - */ - --drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo); -- - drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, - uint64_t max, uint64_t alignment); - -@@ -221,35 +219,4 @@ static inline bool update_references(atomic_t *dst, atomic_t *src) - return false; - } - --/** -- * Assignment between two amdgpu_bo pointers with reference counting. -- * -- * Usage: -- * struct amdgpu_bo *dst = ... , *src = ...; -- * -- * dst = src; -- * // No reference counting. Only use this when you need to move -- * // a reference from one pointer to another. -- * -- * amdgpu_bo_reference(&dst, src); -- * // Reference counters are updated. dst is decremented and src is -- * // incremented. dst is freed if its reference counter is 0. -- */ --static inline void amdgpu_bo_reference(struct amdgpu_bo **dst, -- struct amdgpu_bo *src) --{ -- pthread_mutex_t *mlock; -- struct amdgpu_bo* bo = *dst; -- -- assert(bo != NULL); -- mlock = &bo->dev->bo_table_mutex; -- pthread_mutex_lock(mlock); -- -- if (update_references(&bo->refcount, src ? &src->refcount : NULL)) -- amdgpu_bo_free_internal(bo); -- -- pthread_mutex_unlock(mlock); -- *dst = src; --} -- - #endif --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm/0046-tests-amdgpu-update-uvd-enc-test-for-new-fw.patch b/meta-v1000/recipes-graphics/drm/libdrm/0046-tests-amdgpu-update-uvd-enc-test-for-new-fw.patch deleted file mode 100644 index 41765153..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm/0046-tests-amdgpu-update-uvd-enc-test-for-new-fw.patch +++ /dev/null @@ -1,765 +0,0 @@ -From 3b1134521e5ca5ad1b5cb5212171b3702b70b886 Mon Sep 17 00:00:00 2001 -From: Boyuan Zhang <boyuan.zhang@amd.com> -Date: Fri, 4 Aug 2017 14:49:13 -0400 -Subject: [PATCH 46/46] tests/amdgpu: update uvd enc test for new fw - -uvd hevc enc test failed due to firmware interface changes. -re-write the test based on the new firmware interface. - -Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> -Acked-by: Alex Deucher <alexander.deucher at amd.com> ---- - tests/amdgpu/uvd_enc_tests.c | 138 ++++++++-------- - tests/amdgpu/uve_ib.h | 378 +++++++++++++++++++++++++++++++++---------- - 2 files changed, 358 insertions(+), 158 deletions(-) - -diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c -index f976443..6c19f7b 100644 ---- a/tests/amdgpu/uvd_enc_tests.c -+++ b/tests/amdgpu/uvd_enc_tests.c -@@ -252,30 +252,12 @@ static void amdgpu_cs_uvd_enc_create(void) - alloc_resource(&enc.session, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.session.handle; - resources[num_resources++] = ib_handle; -- -- len = 0; -- memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); -- len += sizeof(uve_session_info) / 4; -- ib_cpu[len++] = enc.session.addr >> 32; -- ib_cpu[len++] = enc.session.addr; -- -- memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); -- len += sizeof(uve_task_info) / 4; -- ib_cpu[len++] = 0x0000001c; -- ib_cpu[len++] = 0x00000000; -- ib_cpu[len++] = 0x00000000; -- -- memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init)); -- len += sizeof(uve_op_init) / 4; -- -- r = submit(len, AMDGPU_HW_IP_UVD_ENC); -- CU_ASSERT_EQUAL(r, 0); - } - - static void check_result(struct amdgpu_uvd_enc *enc) - { - uint64_t sum; -- uint32_t s = 20626; -+ uint32_t s = 26382; - uint32_t *ptr, size; - int i, j, r; - -@@ -302,11 +284,6 @@ static void amdgpu_cs_uvd_enc_session_init(void) - if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) - return; - -- num_resources = 0; -- alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_GTT); -- resources[num_resources++] = enc.fb.handle; -- resources[num_resources++] = ib_handle; -- - len = 0; - memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); - len += sizeof(uve_session_info) / 4; -@@ -315,9 +292,12 @@ static void amdgpu_cs_uvd_enc_session_init(void) - - memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); - len += sizeof(uve_task_info) / 4; -- ib_cpu[len++] = 0x000001c0; -- ib_cpu[len++] = 0x00000001; -- ib_cpu[len++] = 0x00000001; -+ ib_cpu[len++] = 0x000000d8; -+ ib_cpu[len++] = 0x00000000; -+ ib_cpu[len++] = 0x00000000; -+ -+ memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init)); -+ len += sizeof(uve_op_init) / 4; - - memcpy((ib_cpu + len), uve_session_init, sizeof(uve_session_init)); - len += sizeof(uve_session_init) / 4; -@@ -325,9 +305,6 @@ static void amdgpu_cs_uvd_enc_session_init(void) - memcpy((ib_cpu + len), uve_layer_ctrl, sizeof(uve_layer_ctrl)); - len += sizeof(uve_layer_ctrl) / 4; - -- memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); -- len += sizeof(uve_layer_select) / 4; -- - memcpy((ib_cpu + len), uve_slice_ctrl, sizeof(uve_slice_ctrl)); - len += sizeof(uve_slice_ctrl) / 4; - -@@ -337,35 +314,27 @@ static void amdgpu_cs_uvd_enc_session_init(void) - memcpy((ib_cpu + len), uve_rc_session_init, sizeof(uve_rc_session_init)); - len += sizeof(uve_rc_session_init) / 4; - -- memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init)); -- len += sizeof(uve_rc_layer_init) / 4; -- -- memcpy((ib_cpu + len), uve_hw_spec, sizeof(uve_hw_spec)); -- len += sizeof(uve_hw_spec) / 4; -- - memcpy((ib_cpu + len), uve_deblocking_filter, sizeof(uve_deblocking_filter)); - len += sizeof(uve_deblocking_filter) / 4; - -- memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); -- len += sizeof(uve_feedback_buffer) / 4; -- ib_cpu[len++] = enc.fb.addr >> 32; -- ib_cpu[len++] = enc.fb.addr; -- ib_cpu[len++] = 0x00000003; -+ memcpy((ib_cpu + len), uve_quality_params, sizeof(uve_quality_params)); -+ len += sizeof(uve_quality_params) / 4; - - memcpy((ib_cpu + len), uve_op_init_rc, sizeof(uve_op_init_rc)); - len += sizeof(uve_op_init_rc) / 4; - -+ memcpy((ib_cpu + len), uve_op_init_rc_vbv_level, sizeof(uve_op_init_rc_vbv_level)); -+ len += sizeof(uve_op_init_rc_vbv_level) / 4; -+ - r = submit(len, AMDGPU_HW_IP_UVD_ENC); - CU_ASSERT_EQUAL(r, 0); -- -- free_resource(&enc.fb); - } - - static void amdgpu_cs_uvd_enc_encode(void) - { - int len, r, i; - uint64_t luma_offset, chroma_offset; -- uint32_t vbuf_size, bs_size = 0x154000, cpb_size; -+ uint32_t vbuf_size, bs_size = 0x003f4800, cpb_size; - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; - cpb_size = vbuf_size * 10; -@@ -408,55 +377,82 @@ static void amdgpu_cs_uvd_enc_encode(void) - - memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); - len += sizeof(uve_task_info) / 4; -- ib_cpu[len++] = 0x00000210; -- ib_cpu[len++] = 0x00000002; -+ ib_cpu[len++] = 0x000005e0; -+ ib_cpu[len++] = 0x00000001; - ib_cpu[len++] = 0x00000001; - -- memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header)); -- len += sizeof(uve_slice_header) / 4; -+ memcpy((ib_cpu + len), uve_nalu_buffer_1, sizeof(uve_nalu_buffer_1)); -+ len += sizeof(uve_nalu_buffer_1) / 4; - -- unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16); -- luma_offset = enc.vbuf.addr; -- chroma_offset = luma_offset + luma_size; -- ib_cpu[len++] = 0x00000088; -- ib_cpu[len++] = 0x0000000d; -- ib_cpu[len++] = 0x00018000; -- ib_cpu[len++] = luma_offset >> 32; -- ib_cpu[len++] = luma_offset; -- ib_cpu[len++] = chroma_offset >> 32; -- ib_cpu[len++] = chroma_offset; -- memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); -- len += sizeof(uve_encode_param) / 4; -+ memcpy((ib_cpu + len), uve_nalu_buffer_2, sizeof(uve_nalu_buffer_2)); -+ len += sizeof(uve_nalu_buffer_2) / 4; - -- memcpy((ib_cpu + len), uve_quality_param, sizeof(uve_quality_param)); -- len += sizeof(uve_quality_param) / 4; -+ memcpy((ib_cpu + len), uve_nalu_buffer_3, sizeof(uve_nalu_buffer_3)); -+ len += sizeof(uve_nalu_buffer_3) / 4; - -- memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh)); -- len += sizeof(uve_intra_refresh) / 4; -+ memcpy((ib_cpu + len), uve_nalu_buffer_4, sizeof(uve_nalu_buffer_4)); -+ len += sizeof(uve_nalu_buffer_4) / 4; - -- memcpy((ib_cpu + len), uve_reconstructed_pic_output, sizeof(uve_reconstructed_pic_output)); -- len += sizeof(uve_reconstructed_pic_output) / 4; -+ memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header)); -+ len += sizeof(uve_slice_header) / 4; - -- memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer)); -- len += sizeof(uve_ctx_buffer) / 4; -+ ib_cpu[len++] = 0x00000254; -+ ib_cpu[len++] = 0x00000010; - ib_cpu[len++] = enc.cpb.addr >> 32; - ib_cpu[len++] = enc.cpb.addr; -+ memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer)); -+ len += sizeof(uve_ctx_buffer) / 4; - - memcpy((ib_cpu + len), uve_bitstream_buffer, sizeof(uve_bitstream_buffer)); - len += sizeof(uve_bitstream_buffer) / 4; -+ ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = enc.bs.addr >> 32; - ib_cpu[len++] = enc.bs.addr; -- ib_cpu[len++] = 0x00030000; -+ ib_cpu[len++] = 0x003f4800; -+ ib_cpu[len++] = 0x00000000; - - memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); - len += sizeof(uve_feedback_buffer) / 4; - ib_cpu[len++] = enc.fb.addr >> 32; - ib_cpu[len++] = enc.fb.addr; -- ib_cpu[len++] = 0x00000003; -+ ib_cpu[len++] = 0x00000010; -+ ib_cpu[len++] = 0x00000028; -+ -+ memcpy((ib_cpu + len), uve_feedback_buffer_additional, sizeof(uve_feedback_buffer_additional)); -+ len += sizeof(uve_feedback_buffer_additional) / 4; -+ -+ memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh)); -+ len += sizeof(uve_intra_refresh) / 4; -+ -+ memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); -+ len += sizeof(uve_layer_select) / 4; -+ -+ memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init)); -+ len += sizeof(uve_rc_layer_init) / 4; -+ -+ memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); -+ len += sizeof(uve_layer_select) / 4; - - memcpy((ib_cpu + len), uve_rc_per_pic, sizeof(uve_rc_per_pic)); - len += sizeof(uve_rc_per_pic) / 4; - -+ unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16); -+ luma_offset = enc.vbuf.addr; -+ chroma_offset = luma_offset + luma_size; -+ ib_cpu[len++] = 0x00000054; -+ ib_cpu[len++] = 0x0000000c; -+ ib_cpu[len++] = 0x00000002; -+ ib_cpu[len++] = 0x003f4800; -+ ib_cpu[len++] = luma_offset >> 32; -+ ib_cpu[len++] = luma_offset; -+ ib_cpu[len++] = chroma_offset >> 32; -+ ib_cpu[len++] = chroma_offset; -+ memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); -+ len += sizeof(uve_encode_param) / 4; -+ -+ memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode)); -+ len += sizeof(uve_op_speed_enc_mode) / 4; -+ - memcpy((ib_cpu + len), uve_op_encode, sizeof(uve_op_encode)); - len += sizeof(uve_op_encode) / 4; - -@@ -491,7 +487,7 @@ static void amdgpu_cs_uvd_enc_destroy(void) - memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); - len += sizeof(uve_task_info) / 4; - ib_cpu[len++] = 0xffffffff; -- ib_cpu[len++] = 0x00000004; -+ ib_cpu[len++] = 0x00000002; - ib_cpu[len++] = 0x00000000; - - memcpy((ib_cpu + len), uve_op_close, sizeof(uve_op_close)); -diff --git a/tests/amdgpu/uve_ib.h b/tests/amdgpu/uve_ib.h -index c24b9e8..9abd406 100644 ---- a/tests/amdgpu/uve_ib.h -+++ b/tests/amdgpu/uve_ib.h -@@ -27,8 +27,8 @@ - static const uint32_t uve_session_info[] = { - 0x00000018, - 0x00000001, -- 0x00000001, - 0x00000000, -+ 0x00010000, - }; - - static const uint32_t uve_task_info[] = { -@@ -37,29 +37,11 @@ static const uint32_t uve_task_info[] = { - }; - - static const uint32_t uve_session_init[] = { -- 0x00000068, -+ 0x00000020, - 0x00000003, -- 0x00000000, -- 0x000000c0, -- 0x00000080, -- 0x00000000, -- 0x00000000, -- 0x00000001, -- 0x00000002, - 0x000000c0, - 0x00000080, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -- 0x00000000, -+ 0x00000020, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -82,8 +64,8 @@ static const uint32_t uve_slice_ctrl[] = { - 0x00000014, - 0x00000006, - 0x00000000, -- 0x00000008, -- 0x00000008, -+ 0x00000006, -+ 0x00000006, - }; - - static const uint32_t uve_spec_misc[] = { -@@ -93,9 +75,9 @@ static const uint32_t uve_spec_misc[] = { - 0x00000000, - 0x00000000, - 0x00000000, -- 0x00000004, - 0x00000000, -- 0x00000005, -+ 0x00000001, -+ 0x00000001, - }; - - static const uint32_t uve_rc_session_init[] = { -@@ -108,54 +90,103 @@ static const uint32_t uve_rc_session_init[] = { - static const uint32_t uve_rc_layer_init[] = { - 0x00000028, - 0x00000009, -+ 0x001e8480, -+ 0x001e8480, -+ 0x0000001e, -+ 0x00000001, -+ 0x0001046a, -+ 0x0001046a, -+ 0x0001046a, -+ 0xaaaaaaaa, -+}; -+ -+static const uint32_t uve_deblocking_filter[] = { -+ 0x00000020, -+ 0x0000000e, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -+}; -+ -+static const uint32_t uve_quality_params[] = { -+ 0x00000014, -+ 0x0000000d, - 0x00000000, - 0x00000000, - 0x00000000, - }; - --static const uint32_t uve_hw_spec[] = { -- 0x0000007c, -- 0x0000000b, -- 0x00000002, -+static const uint32_t uve_feedback_buffer[] = { -+ 0x0000001c, -+ 0x00000012, - 0x00000000, -+}; -+ -+static const uint32_t uve_feedback_buffer_additional[] = { -+ 0x00000108, -+ 0x00000014, - 0x00000001, -- 0x00000001, -- 0x00000001, -- 0x00000001, -- 0x00000001, -- 0x00000010, -- 0x00000010, -- 0x00000010, -- 0x00000010, -- 0x00000008, -- 0x00000008, -- 0x00000010, - 0x00000010, - 0x00000000, -- 0x00000002, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -- 0x00000001, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -- 0x00000001, -- 0x00000001, --}; -- --static const uint32_t uve_deblocking_filter[] = { -- 0x00000020, -- 0x0000000f, -- 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -163,19 +194,62 @@ static const uint32_t uve_deblocking_filter[] = { - 0x00000000, - }; - --static const uint32_t uve_feedback_buffer[] = { -- 0x00000014, -- 0x00000014, -+static const uint32_t uve_nalu_buffer_1[] = { -+ 0x00000018, -+ 0x00000013, -+ 0x00000001, -+ 0x00000007, -+ 0x00000001, -+ 0x46011000, -+}; -+ -+static const uint32_t uve_nalu_buffer_2[] = { -+ 0x0000002c, -+ 0x00000013, -+ 0x00000002, -+ 0x0000001b, -+ 0x00000001, -+ 0x40010c01, -+ 0xffff0160, -+ 0x00000300, -+ 0xb0000003, -+ 0x00000300, -+ 0x962c0900, -+}; -+ -+static const uint32_t uve_nalu_buffer_3[] = { -+ 0x00000034, -+ 0x00000013, -+ 0x00000003, -+ 0x00000023, -+ 0x00000001, -+ 0x42010101, -+ 0x60000003, -+ 0x00b00000, -+ 0x03000003, -+ 0x0096a018, -+ 0x2020708f, -+ 0xcb924295, -+ 0x12e08000, -+}; -+ -+static const uint32_t uve_nalu_buffer_4[] = { -+ 0x0000001c, -+ 0x00000013, -+ 0x00000004, -+ 0x0000000b, -+ 0x00000001, -+ 0x4401e0f1, -+ 0x80992000, - }; - --/* TODO - Slice Header*/ - static const uint32_t uve_slice_header[] = { - 0x000000c8, -- 0x0000000c, -- 0x26010000, -+ 0x0000000b, -+ 0x28010000, - 0x40000000, - 0x60000000, -- 0x80000000, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -203,7 +277,7 @@ static const uint32_t uve_slice_header[] = { - 0x00000005, - 0x00000000, - 0x00000002, -- 0x00000001, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -223,15 +297,146 @@ static const uint32_t uve_slice_header[] = { - }; - - static const uint32_t uve_encode_param[] = { -- 0x00000000, -- 0x00000000, - 0x000000a0, - 0x00000080, - 0x00000000, - 0x00000000, -- 0x00000002, -- 0xffffffff, - 0xffffffff, -+ 0x00000001, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+}; -+ -+static const uint32_t uve_intra_refresh[] = { -+ 0x00000014, -+ 0x0000000f, -+ 0x00000000, -+ 0x00000000, -+ 0x00000001, -+}; -+ -+static const uint32_t uve_ctx_buffer[] = { -+ 0x00000000, -+ 0x00000000, -+ 0x000000a0, -+ 0x000000a0, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, -+ 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -@@ -250,55 +455,34 @@ static const uint32_t uve_encode_param[] = { - 0x00000000, - 0x00000000, - 0x00000000, --}; -- --static const uint32_t uve_quality_param[] = { -- 0x00000014, -- 0x0000000e, - 0x00000000, - 0x00000000, - 0x00000000, --}; -- --static const uint32_t uve_intra_refresh[] = { -- 0x00000014, -- 0x00000010, - 0x00000000, - 0x00000000, -- 0x00000004, --}; -- --static const uint32_t uve_reconstructed_pic_output[] = { -- 0x00000020, -- 0x00000011, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, --}; -- --static const uint32_t uve_ctx_buffer[] = { -- 0x00000010, -- 0x00000012, - }; - - static const uint32_t uve_bitstream_buffer[] = { -- 0x00000014, -- 0x00000013, -+ 0x0000001c, -+ 0x00000011, - }; - - static const uint32_t uve_rc_per_pic[] = { - 0x00000024, - 0x0000000a, - 0x0000001a, -- 0x00000014, -- 0x0000002D, - 0x00000000, -+ 0x00000033, - 0x00000000, - 0x00000000, - 0x00000000, -+ 0x00000001, - }; - - static const uint32_t uve_op_init[] = { -@@ -320,4 +504,24 @@ static const uint32_t uve_op_init_rc[] = { - 0x00000008, - 0x08000004, - }; -+ -+static const uint32_t uve_op_init_rc_vbv_level[] = { -+ 0x00000008, -+ 0x08000005, -+}; -+ -+static const uint32_t uve_op_speed_enc_mode[] = { -+ 0x00000008, -+ 0x08000006, -+}; -+ -+static const uint32_t uve_op_balance_enc_mode[] = { -+ 0x00000008, -+ 0x08000007, -+}; -+ -+static const uint32_t uve_op_quality_enc_mode[] = { -+ 0x00000008, -+ 0x08000008, -+}; - #endif /*_uve_ib_h*/ --- -2.7.4 - diff --git a/meta-v1000/recipes-graphics/drm/libdrm_2.4.%.bbappend b/meta-v1000/recipes-graphics/drm/libdrm_2.4.%.bbappend new file mode 100644 index 00000000..b17f5c62 --- /dev/null +++ b/meta-v1000/recipes-graphics/drm/libdrm_2.4.%.bbappend @@ -0,0 +1,52 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}:" + +SRC_URI_append = " file://0001-amdgpu-Implement-SVM-v3.patch \ + file://0002-amdgpu-SVM-test-v3.patch \ + file://0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch \ + file://0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch \ + file://0005-amdgpu-add-query-for-aperture-va-range.patch \ + file://0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch \ + file://0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch \ + file://0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch \ + file://0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch \ + file://0010-amdgpu-support-alloc-va-from-range-v2.patch \ + file://0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch \ + file://0012-amdgpu-change-max-allocation.patch \ + file://0013-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch \ + file://0014-amdgpu-add-amdgpu_bo_inc_ref-function.patch \ + file://0015-amdgpu-Make-amdgpu_get_auth-to-non-static.patch \ + file://0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch \ + file://0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch \ + file://0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch \ + file://0019-drm-amdgpu-add-freesync-ioctl-defines.patch \ + file://0020-amdgpu-implement-direct-gma.patch \ + file://0021-tests-amdgpu-add-direct-gma-test.patch \ + file://0022-amdgpu-add-new-semaphore-support-v2.patch \ + file://0023-implement-import-export-sem.patch \ + file://0024-test-case-for-export-import-sem.patch \ + file://0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch \ + file://0029-amdgpu-support-16-ibs-per-submit-for-PAL-SRIOV.patch \ + file://0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch \ + file://0031-amdgpu-unify-dk-drm-header-changes.patch \ + file://0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch \ + file://0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch \ + file://0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch \ + file://0044-amdgpu-HYBRID-change-to-use-amdgpu_bo_free.patch \ + file://amdgpu.ids \ +" + +EXTRA_OECONF = "--disable-cairo-tests \ + --enable-omap-experimental-api \ + --enable-install-test-programs \ + --disable-manpages \ + --disable-valgrind \ + --enable-amdgpu \ + --enable-radeon \ + " + +do_install_append() { + cp ${S}/include/drm/amdgpu_drm.h ${D}/usr/include/libdrm + install -vd ${D}/usr/share/libdrm + cp ${WORKDIR}/amdgpu.ids ${D}/usr/share/libdrm +} + diff --git a/meta-v1000/recipes-graphics/drm/libdrm_git.bb b/meta-v1000/recipes-graphics/drm/libdrm_git.bb deleted file mode 100644 index a69f15c2..00000000 --- a/meta-v1000/recipes-graphics/drm/libdrm_git.bb +++ /dev/null @@ -1,101 +0,0 @@ -SUMMARY = "Userspace interface to the kernel DRM services" -DESCRIPTION = "The runtime library for accessing the kernel DRM services. DRM \ -stands for \"Direct Rendering Manager\", which is the kernel portion of the \ -\"Direct Rendering Infrastructure\" (DRI). DRI is required for many hardware \ -accelerated OpenGL drivers." - -HOMEPAGE = "http://dri.freedesktop.org" -SECTION = "x11/base" -LICENSE = "MIT" -LIC_FILES_CHKSUM_amd = "file://xf86drm.c;beginline=9;endline=32;md5=c8a3b961af7667c530816761e949dc71" -PROVIDES = "drm" -PV = "git" - -inherit autotools pkgconfig - -SRCREV = "23e234a3503f51b9d9c585123d33b936f522808d" -DEPENDS = "libpthread-stubs udev libpciaccess freetype libxext cairo fontconfig libxrender libpng pixman" - -SRC_URI = "git://anongit.freedesktop.org/mesa/drm;branch=master \ - file://0001-amdgpu-Implement-SVM-v3.patch \ - file://0002-amdgpu-SVM-test-v3.patch \ - file://0003-amdgpu-Implement-multiGPU-SVM-support-v3.patch \ - file://0004-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v4.patch \ - file://0005-amdgpu-add-query-for-aperture-va-range.patch \ - file://0006-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag-v2.patch \ - file://0007-amdgpu-add-sparse-flag-for-bo-creatation-v2.patch \ - file://0008-amdgpu-add-amdgpu_query_capability-interface-v2.patch \ - file://0009-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch \ - file://0010-amdgpu-support-alloc-va-from-range-v2.patch \ - file://0011-tests-amdgpu-add-alloc-va-from-range-test-v2.patch \ - file://0012-amdgpu-change-max-allocation.patch \ - file://0013-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch \ - file://0014-amdgpu-add-amdgpu_bo_inc_ref-function.patch \ - file://0015-amdgpu-Make-amdgpu_get_auth-to-non-static.patch \ - file://0016-amdgpu-Add-interface-amdgpu_get_fb_id-v2.patch \ - file://0017-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id-v2.patch \ - file://0018-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch \ - file://0019-drm-amdgpu-add-freesync-ioctl-defines.patch \ - file://0020-amdgpu-implement-direct-gma.patch \ - file://0021-tests-amdgpu-add-direct-gma-test.patch \ - file://0022-amdgpu-add-new-semaphore-support-v2.patch \ - file://0023-implement-import-export-sem.patch \ - file://0024-test-case-for-export-import-sem.patch \ - file://0025-amdgpu-Sparse-resource-support-for-Vulkan-v2.patch \ - file://0026-tests-amdgpu-add-uvd-enc-unit-tests-v2.patch \ - file://0027-tests-amdgpu-add-uve-ib-header.patch \ - file://0028-tests-amdgpu-implement-hevc-encode-test-v2.patch \ - file://0029-amdgpu-support-16-ibs-per-submit-for-PAL-SRIOV.patch \ - file://0030-amdgpu-hybrid-add-a-flag-of-memory-allcation-from-to.patch \ - file://0031-amdgpu-unify-dk-drm-header-changes.patch \ - file://0032-amdgpu-add-interface-for-reserve-unserve-vmid-v2.patch \ - file://0033-amdgpu-HYBRID-add-AMDGPU_CAPABILITY_SSG_FLAG.patch \ - file://0034-tests-amdgpu-bypass-UVD-CS-tests-on-raven.patch \ - file://0035-tests-amdgpu-bypass-UVD-ENC-tests-on-raven.patch \ - file://0036-tests-amdgpu-bypass-VCE-tests-on-raven.patch \ - file://0037-tests-amdgpu-HYBRID-add-SSG-unit-test.patch \ - file://0038-amdgpu-Add-gpu-always-on-cu-bitmap.patch \ - file://0039-test-amdgpu-fix-test-failure-for-SI.patch \ - file://0040-drm-fix-missing-mutex-unlock-before-return.patch \ - file://0041-drm-fix-race-issue-between-two-bo-functions-v2.patch \ - file://0042-amdgpu-fix-potential-deadlock.patch \ - file://0043-Revert-amdgpu-fix-potential-deadlock.patch \ - file://0044-amdgpu-HYBRID-change-to-use-amdgpu_bo_free.patch \ - file://0045-amdgpu-merge-and-cleanup-amdgpu_bo_free.patch \ - file://0046-tests-amdgpu-update-uvd-enc-test-for-new-fw.patch \ - file://amdgpu.ids \ -" - -S = "${WORKDIR}/git" - -EXTRA_OECONF = "--disable-cairo-tests \ - --enable-omap-experimental-api \ - --enable-install-test-programs \ - --disable-manpages \ - --disable-valgrind \ - --enable-amdgpu \ - --enable-radeon \ - " - -ALLOW_EMPTY_${PN}-drivers = "1" -PACKAGES =+ "${PN}-tests ${PN}-drivers ${PN}-radeon ${PN}-nouveau ${PN}-omap \ - ${PN}-intel ${PN}-exynos ${PN}-kms ${PN}-freedreno ${PN}-amdgpu" - -RRECOMMENDS_${PN}-drivers = "${PN}-radeon ${PN}-nouveau ${PN}-omap ${PN}-intel \ - ${PN}-exynos ${PN}-freedreno ${PN}-amdgpu" - -FILES_${PN}-tests = "${bindir}/dr* ${bindir}/mode* ${bindir}/*test" -FILES_${PN}-radeon = "${libdir}/libdrm_radeon.so.*" -FILES_${PN}-nouveau = "${libdir}/libdrm_nouveau.so.*" -FILES_${PN}-omap = "${libdir}/libdrm_omap.so.*" -FILES_${PN}-intel = "${libdir}/libdrm_intel.so.*" -FILES_${PN}-exynos = "${libdir}/libdrm_exynos.so.*" -FILES_${PN}-kms = "${libdir}/libkms*.so.*" -FILES_${PN}-freedreno = "${libdir}/libdrm_freedreno.so.*" -FILES_${PN}-amdgpu = "${libdir}/libdrm_amdgpu.so.*" - -do_install_append() { - cp ${S}/include/drm/amdgpu_drm.h ${D}/usr/include/libdrm - install -vd ${D}/usr/share/libdrm - cp ${WORKDIR}/amdgpu.ids ${D}/usr/share/libdrm -} diff --git a/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-samples_1.0.65.bb b/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-samples_1.0.65.bb index 5611cd63..3a58fbf8 100644 --- a/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-samples_1.0.65.bb +++ b/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-samples_1.0.65.bb @@ -3,7 +3,7 @@ DESCRIPTION = "This project is a collection \ of Vulkan C++ sample applications." SECTION = "graphics" HOMEPAGE = "https://github.com/LunarG/VulkanSamples" -DEPENDS = "vulkan-loader-layers glslang" +DEPENDS = "vulkan-loader-layers glslang glslang-native libxkbcommon" inherit cmake python3native diff --git a/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.65.bb b/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.65.bb index d26d7862..0e41c56d 100644 --- a/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.65.bb +++ b/meta-v1000/recipes-graphics/lunarg-sdk/vulkan-tools_1.0.65.bb @@ -48,8 +48,8 @@ INSANE_SKIP_${PN}-layer-libs = "ldflags" # Conditional building of vktraceviewer QTBITS ?= "${@bb.utils.contains('BBFILE_COLLECTIONS', 'qt5-layer', 'cmake_qt5', '',d)}" inherit ${QTBITS} -DEPENDS += "${@base_conditional('QTBITS', '', '', 'libxcb qtsvg', d)}" -RDEPENDS_${PN}_append = " ${@base_conditional('QTBITS', '', '', 'qtsvg', d)}" +DEPENDS += "${@oe.utils.conditional('QTBITS', '', '', 'libxcb qtsvg', d)}" +RDEPENDS_${PN}_append = " ${@oe.utils.conditional('QTBITS', '', '', 'qtsvg', d)}" do_install_append() { if [ "${QTBITS}" != "" ] then diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0001-st-omx-enc-Correct-the-timestamping.patch b/meta-v1000/recipes-graphics/mesa/mesa/0001-st-omx-enc-Correct-the-timestamping.patch index 6542098c..41e06404 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0001-st-omx-enc-Correct-the-timestamping.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0001-st-omx-enc-Correct-the-timestamping.patch @@ -8,13 +8,13 @@ while pushing bitstrema buffer to the omx client. Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com> --- - src/gallium/state_trackers/omx/vid_enc.c | 3 +++ + src/gallium/state_trackers/omx_bellagio/vid_enc.c | 3 +++ 1 file changed, 3 insertions(+) -diff --git a/src/gallium/state_trackers/omx/vid_enc.c b/src/gallium/state_trackers/omx/vid_enc.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c b/src/gallium/state_trackers/omx_bellagio/vid_enc.c index 1a4fb62..9004ddd 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.c -+++ b/src/gallium/state_trackers/omx/vid_enc.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c @@ -58,6 +58,7 @@ struct encode_task { struct list_head list; diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0002-st-omx-enc-Modularize-the-Encoding-task.patch b/meta-v1000/recipes-graphics/mesa/mesa/0002-st-omx-enc-Modularize-the-Encoding-task.patch index c692b70a..1e58435c 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0002-st-omx-enc-Modularize-the-Encoding-task.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0002-st-omx-enc-Modularize-the-Encoding-task.patch @@ -7,13 +7,13 @@ Prepare for integrating the FRC logic in encoder Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com> --- - src/gallium/state_trackers/omx/vid_enc.c | 78 ++++++++++++++++++-------------- + src/gallium/state_trackers/omx_bellagio/vid_enc.c | 78 ++++++++++++++++++-------------- 1 file changed, 44 insertions(+), 34 deletions(-) -diff --git a/src/gallium/state_trackers/omx/vid_enc.c b/src/gallium/state_trackers/omx/vid_enc.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c b/src/gallium/state_trackers/omx_bellagio/vid_enc.c index 9004ddd..a6502ce 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.c -+++ b/src/gallium/state_trackers/omx/vid_enc.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c @@ -1138,44 +1138,13 @@ static void enc_ClearBframes(omx_base_PortType *port, struct input_buf_private * enc_MoveTasks(&priv->b_frames, &inp->tasks); } diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0003-st-omx-enc-Support-framerate-conversion.patch b/meta-v1000/recipes-graphics/mesa/mesa/0003-st-omx-enc-Support-framerate-conversion.patch index 89f1348a..0cf39d96 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0003-st-omx-enc-Support-framerate-conversion.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0003-st-omx-enc-Support-framerate-conversion.patch @@ -18,14 +18,14 @@ timestamps. Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com> --- - src/gallium/state_trackers/omx/vid_enc.c | 194 +++++++++++++++++++++++++++++-- - src/gallium/state_trackers/omx/vid_enc.h | 7 ++ + src/gallium/state_trackers/omx_bellagio/vid_enc.c | 194 +++++++++++++++++++++++++++++-- + src/gallium/state_trackers/omx_bellagio/vid_enc.h | 7 ++ 2 files changed, 192 insertions(+), 9 deletions(-) -diff --git a/src/gallium/state_trackers/omx/vid_enc.c b/src/gallium/state_trackers/omx/vid_enc.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c b/src/gallium/state_trackers/omx_bellagio/vid_enc.c index a6502ce..ec3b281 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.c -+++ b/src/gallium/state_trackers/omx/vid_enc.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c @@ -54,11 +54,19 @@ #include "entrypoint.h" #include "vid_enc.h" @@ -311,10 +311,10 @@ index a6502ce..ec3b281 100644 - output->nFlags = OMX_BUFFERFLAG_ENDOFFRAME; + output->nFlags = OMX_BUFFERFLAG_ENDOFFRAME; } -diff --git a/src/gallium/state_trackers/omx/vid_enc.h b/src/gallium/state_trackers/omx/vid_enc.h +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.h b/src/gallium/state_trackers/omx_bellagio/vid_enc.h index a833744..4b73f68 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.h -+++ b/src/gallium/state_trackers/omx/vid_enc.h +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.h ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.h @@ -74,6 +74,13 @@ DERIVEDCLASS(vid_enc_PrivateType, omx_base_filter_PrivateType) struct list_head used_tasks; \ struct list_head b_frames; \ diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch b/meta-v1000/recipes-graphics/mesa/mesa/0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch index e06e2750..d9904b63 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch @@ -1,7 +1,7 @@ -From e286b9139834d21c6d3e13e62535f7a7d627cbcb Mon Sep 17 00:00:00 2001 -From: Indrajit Das <indrajit-kumar.das@amd.com> -Date: Tue, 1 Aug 2017 10:49:01 +0530 -Subject: [PATCH] st/mesa: Reverting patches that solved perf issues with mesa +From 345436540fbba97a22170c7fff4bed1d461d7fd7 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Fri, 15 Dec 2017 15:35:08 +0500 +Subject: [PATCH] st/mesa: Reverting patches that solved perf issues with mesa 12.0.3 This patch reverts below patches to solve performance issue @@ -19,6 +19,7 @@ patch4: Subject: st/mesa: fix reference counting bug in st_vdpau Signed-off-by: Avinash M N <avimn@amd.com> +Signed-off-by: Awais Belal <awais_belal@mentor.com> --- src/gallium/state_trackers/vdpau/output.c | 2 +- src/mesa/state_tracker/st_texture.h | 6 + @@ -39,10 +40,10 @@ index 8ef8268..c13bbaf 100644 mtx_lock(&dev->mutex); diff --git a/src/mesa/state_tracker/st_texture.h b/src/mesa/state_tracker/st_texture.h -index 8448f4c..8bcca89 100644 +index 8b549b8..6ed4294 100644 --- a/src/mesa/state_tracker/st_texture.h +++ b/src/mesa/state_tracker/st_texture.h -@@ -84,6 +84,12 @@ struct st_texture_object +@@ -97,6 +97,12 @@ struct st_texture_object */ GLuint lastLevel; @@ -56,7 +57,7 @@ index 8448f4c..8bcca89 100644 unsigned int validated_last_level; diff --git a/src/mesa/state_tracker/st_vdpau.c b/src/mesa/state_tracker/st_vdpau.c -index 0273815..827e1f0 100644 +index 19611e7..aeb66df 100644 --- a/src/mesa/state_tracker/st_vdpau.c +++ b/src/mesa/state_tracker/st_vdpau.c @@ -38,6 +38,7 @@ @@ -276,7 +277,7 @@ index 0273815..827e1f0 100644 return; } -@@ -235,18 +133,20 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, +@@ -235,19 +133,21 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, st_texture_release_all_sampler_views(st, stObj); pipe_resource_reference(&stImage->pt, res); @@ -284,6 +285,7 @@ index 0273815..827e1f0 100644 + stObj->height0 = res->height0; + stObj->depth0 = 1; stObj->surface_format = res->format; + stObj->level_override = 0; stObj->layer_override = layer_override; _mesa_dirty_texobj(ctx, texObj); @@ -300,5 +302,5 @@ index 0273815..827e1f0 100644 struct st_context *st = st_context(ctx); struct st_texture_object *stObj = st_texture_object(texObj); -- -2.7.4 +2.11.1 diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0006-st-omx-handle-invalid-timestamps-better-for-frc.patch b/meta-v1000/recipes-graphics/mesa/mesa/0006-st-omx-handle-invalid-timestamps-better-for-frc.patch index 21c0fa25..38da60c5 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0006-st-omx-handle-invalid-timestamps-better-for-frc.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0006-st-omx-handle-invalid-timestamps-better-for-frc.patch @@ -7,14 +7,14 @@ Handle buffers with 0 timestamps better by keeping track of the en time of the previous buffer and assuming the 0 timestamp buffer goes right after the previous one. --- - src/gallium/state_trackers/omx/vid_dec.c | 1 + - src/gallium/state_trackers/omx/vid_enc.c | 4 ++++ + src/gallium/state_trackers/omx_bellagio/vid_dec.c | 1 + + src/gallium/state_trackers/omx_bellagio/vid_enc.c | 4 ++++ 2 files changed, 5 insertions(+) -diff --git a/src/gallium/state_trackers/omx/vid_dec.c b/src/gallium/state_trackers/omx/vid_dec.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_dec.c b/src/gallium/state_trackers/omx_bellagio/vid_dec.c index 313bc0a..e0d3043 100644 ---- a/src/gallium/state_trackers/omx/vid_dec.c -+++ b/src/gallium/state_trackers/omx/vid_dec.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_dec.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_dec.c @@ -656,6 +656,7 @@ static void vid_dec_FrameDecoded(OMX_COMPONENTTYPE *comp, OMX_BUFFERHEADERTYPE* } output->nFilledLen = output->nAllocLen; @@ -23,10 +23,10 @@ index 313bc0a..e0d3043 100644 } if (eos && input->pInputPortPrivate) -diff --git a/src/gallium/state_trackers/omx/vid_enc.c b/src/gallium/state_trackers/omx/vid_enc.c +diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c b/src/gallium/state_trackers/omx_bellagio/vid_enc.c index ec3b281..c80dcd5 100644 ---- a/src/gallium/state_trackers/omx/vid_enc.c -+++ b/src/gallium/state_trackers/omx/vid_enc.c +--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c ++++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c @@ -1332,6 +1332,10 @@ static OMX_ERRORTYPE vid_enc_EncodeFrame(omx_base_PortType *port, OMX_BUFFERHEAD /* Two frames are available to make a choice */ diff --git a/meta-v1000/recipes-graphics/mesa/mesa/0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch b/meta-v1000/recipes-graphics/mesa/mesa/0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch index 8a5dc15f..96fecf77 100644 --- a/meta-v1000/recipes-graphics/mesa/mesa/0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch +++ b/meta-v1000/recipes-graphics/mesa/mesa/0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch @@ -1,10 +1,13 @@ -From 543a654b9ad9016c0e01a33a6f2b41a0935e1d80 Mon Sep 17 00:00:00 2001 -From: Indrajit Das <indrajit-kumar.das@amd.com> -Date: Thu, 21 Sep 2017 11:49:32 +0530 -Subject: [PATCH 7/7] Revert "st/mesa: Reverting patches that solved perf - issues with mesa 12.0.3" +From f9affcd19f4f4695084399aeaaa2d1e1344e7b94 Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Fri, 15 Dec 2017 15:40:52 +0500 +Subject: [PATCH] Revert "st/mesa: Reverting patches that solved perf issues + with mesa 12.0.3" This reverts commit 6102e577d8f2816771920a014c5d80ca62dafb8d. + +Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com> +Signed-off-by: Awais Belal <awais_belal@mentor.com> --- src/gallium/state_trackers/vdpau/output.c | 2 +- src/mesa/state_tracker/st_texture.h | 6 - @@ -25,10 +28,10 @@ index c13bbaf..8ef8268 100644 mtx_lock(&dev->mutex); diff --git a/src/mesa/state_tracker/st_texture.h b/src/mesa/state_tracker/st_texture.h -index 8bcca89..8448f4c 100644 +index 6ed4294..8b549b8 100644 --- a/src/mesa/state_tracker/st_texture.h +++ b/src/mesa/state_tracker/st_texture.h -@@ -84,12 +84,6 @@ struct st_texture_object +@@ -97,12 +97,6 @@ struct st_texture_object */ GLuint lastLevel; @@ -42,7 +45,7 @@ index 8bcca89..8448f4c 100644 unsigned int validated_last_level; diff --git a/src/mesa/state_tracker/st_vdpau.c b/src/mesa/state_tracker/st_vdpau.c -index 827e1f0..0273815 100644 +index aeb66df..19611e7 100644 --- a/src/mesa/state_tracker/st_vdpau.c +++ b/src/mesa/state_tracker/st_vdpau.c @@ -38,7 +38,6 @@ @@ -262,7 +265,7 @@ index 827e1f0..0273815 100644 return; } -@@ -133,20 +235,18 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, +@@ -133,21 +235,19 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, GLenum access, st_texture_release_all_sampler_views(st, stObj); pipe_resource_reference(&stImage->pt, res); @@ -270,6 +273,7 @@ index 827e1f0..0273815 100644 - stObj->height0 = res->height0; - stObj->depth0 = 1; stObj->surface_format = res->format; + stObj->level_override = 0; stObj->layer_override = layer_override; _mesa_dirty_texobj(ctx, texObj); @@ -286,5 +290,5 @@ index 827e1f0..0273815 100644 struct st_context *st = st_context(ctx); struct st_texture_object *stObj = st_texture_object(texObj); -- -2.7.4 +2.11.1 diff --git a/meta-v1000/recipes-graphics/mesa/mesa_17.3.%.bbappend b/meta-v1000/recipes-graphics/mesa/mesa_17.3.%.bbappend new file mode 100644 index 00000000..e819463b --- /dev/null +++ b/meta-v1000/recipes-graphics/mesa/mesa_17.3.%.bbappend @@ -0,0 +1,11 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + +MESA_LLVM_RELEASE_v1000 = "6.0" + +SRC_URI_append_v1000 = " file://0001-st-omx-enc-Correct-the-timestamping.patch \ + file://0002-st-omx-enc-Modularize-the-Encoding-task.patch \ + file://0003-st-omx-enc-Support-framerate-conversion.patch \ + file://0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch \ + file://0005-Added-the-workaround-fix-for-the-opengl-CTS-failure..patch \ + file://0006-st-omx-handle-invalid-timestamps-better-for-frc.patch \ + file://0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch"
\ No newline at end of file diff --git a/meta-v1000/recipes-graphics/mesa/mesa_git.bbappend b/meta-v1000/recipes-graphics/mesa/mesa_git.bbappend deleted file mode 100644 index f6ad3fee..00000000 --- a/meta-v1000/recipes-graphics/mesa/mesa_git.bbappend +++ /dev/null @@ -1,23 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" - -SRCREV_v1000 = "b8dd69e1b49a5c4c5c82e34f804a97f7448ff6c3" -LIC_FILES_CHKSUM_v1000 = "file://docs/license.html;md5=725f991a1cc322aa7a0cd3a2016621c4" -PV_v1000 = "17.3.0+git${SRCPV}" - -MESA_LLVM_RELEASE_v1000 = "6.0" - -PACKAGECONFIG_append_v1000 = " dri3" - -SRC_URI_v1000 = "\ - git://anongit.freedesktop.org/mesa/mesa;branch=master \ - file://0001-st-omx-enc-Correct-the-timestamping.patch \ - file://0002-st-omx-enc-Modularize-the-Encoding-task.patch \ - file://0003-st-omx-enc-Support-framerate-conversion.patch \ - file://0004-st-mesa-Reverting-patches-that-solved-perf-issues-wi.patch \ - file://0005-Added-the-workaround-fix-for-the-opengl-CTS-failure..patch \ - file://0006-st-omx-handle-invalid-timestamps-better-for-frc.patch \ - file://0007-Revert-st-mesa-Reverting-patches-that-solved-perf-is.patch \ -" - -MESA_CRYPTO_v1000 = "" - diff --git a/meta-v1000/recipes-multimedia/ffmpeg/ffmpeg_3.2.2.bb b/meta-v1000/recipes-multimedia/ffmpeg/ffmpeg_3.2.2.bb deleted file mode 100644 index 6afdee27..00000000 --- a/meta-v1000/recipes-multimedia/ffmpeg/ffmpeg_3.2.2.bb +++ /dev/null @@ -1,142 +0,0 @@ -SUMMARY = "A complete, cross-platform solution to record, convert and stream audio and video." -DESCRIPTION = "FFmpeg is the leading multimedia framework, able to decode, encode, transcode, \ - mux, demux, stream, filter and play pretty much anything that humans and machines \ - have created. It supports the most obscure ancient formats up to the cutting edge." -HOMEPAGE = "https://www.ffmpeg.org/" -SECTION = "libs" - -LICENSE = "GPLv2+" -LICENSE_FLAGS = "commercial" - -LIC_FILES_CHKSUM = "file://COPYING.GPLv2;md5=b234ee4d69f5fce4486a80fdaf4a4263 \ - file://COPYING.GPLv3;md5=d32239bcb673463ab874e80d47fae504 \ - file://COPYING.LGPLv2.1;md5=bd7a443320af8c812e4c18d1b79df004 \ - file://COPYING.LGPLv3;md5=e6a600fd5e1d9cbde2d983680233ad02" - -SRC_URI = "https://www.ffmpeg.org/releases/${BP}.tar.xz \ - " -SRC_URI[md5sum] = "e34d1b92c5d844f2a3611c741a6dba18" -SRC_URI[sha256sum] = "3f01bd1fe1a17a277f8c84869e5d9192b4b978cb660872aa2b54c3cc8a2fedfc" - -# Build fails when thumb is enabled: https://bugzilla.yoctoproject.org/show_bug.cgi?id=7717 -ARM_INSTRUCTION_SET = "arm" - -# Should be API compatible with libav (which was a fork of ffmpeg) -# libpostproc was previously packaged from a separate recipe -PROVIDES = "libav libpostproc" - -DEPENDS = "alsa-lib zlib libogg yasm-native" - -inherit autotools pkgconfig - -PACKAGECONFIG ??= "avdevice avfilter avcodec avformat swresample swscale postproc \ - bzlib gpl lzma theora x264 \ - ${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'x11 xv', '', d)}" - -# libraries to build in addition to avutil -PACKAGECONFIG[avdevice] = "--enable-avdevice,--disable-avdevice" -PACKAGECONFIG[avfilter] = "--enable-avfilter,--disable-avfilter" -PACKAGECONFIG[avcodec] = "--enable-avcodec,--disable-avcodec" -PACKAGECONFIG[avformat] = "--enable-avformat,--disable-avformat" -PACKAGECONFIG[swresample] = "--enable-swresample,--disable-swresample" -PACKAGECONFIG[swscale] = "--enable-swscale,--disable-swscale" -PACKAGECONFIG[postproc] = "--enable-postproc,--disable-postproc" -PACKAGECONFIG[avresample] = "--enable-avresample,--disable-avresample" - -# features to support -PACKAGECONFIG[bzlib] = "--enable-bzlib,--disable-bzlib,bzip2" -PACKAGECONFIG[gpl] = "--enable-gpl,--disable-gpl" -PACKAGECONFIG[gsm] = "--enable-libgsm,--disable-libgsm,libgsm" -PACKAGECONFIG[jack] = "--enable-indev=jack,--disable-indev=jack,jack" -PACKAGECONFIG[libvorbis] = "--enable-libvorbis,--disable-libvorbis,libvorbis" -PACKAGECONFIG[lzma] = "--enable-lzma,--disable-lzma,xz" -PACKAGECONFIG[mp3lame] = "--enable-libmp3lame,--disable-libmp3lame,lame" -PACKAGECONFIG[openssl] = "--enable-openssl,--disable-openssl,openssl" -PACKAGECONFIG[schroedinger] = "--enable-libschroedinger,--disable-libschroedinger,schroedinger" -PACKAGECONFIG[speex] = "--enable-libspeex,--disable-libspeex,speex" -PACKAGECONFIG[theora] = "--enable-libtheora,--disable-libtheora,libtheora" -PACKAGECONFIG[vaapi] = "--enable-vaapi,--disable-vaapi,libva" -PACKAGECONFIG[vdpau] = "--enable-vdpau,--disable-vdpau,libvdpau" -PACKAGECONFIG[vpx] = "--enable-libvpx,--disable-libvpx,libvpx" -PACKAGECONFIG[x11] = "--enable-x11grab,--disable-x11grab,virtual/libx11 libxfixes libxext xproto virtual/libsdl" -PACKAGECONFIG[x264] = "--enable-libx264,--disable-libx264,x264" -PACKAGECONFIG[xv] = "--enable-outdev=xv,--disable-outdev=xv,libxv" - -# Check codecs that require --enable-nonfree -USE_NONFREE = "${@bb.utils.contains_any('PACKAGECONFIG', [ 'openssl' ], 'yes', '', d)}" - -EXTRA_OECONF = " \ - --disable-stripping \ - --enable-pic \ - --enable-shared \ - --enable-pthreads \ - ${@bb.utils.contains('USE_NONFREE', 'yes', '--enable-nonfree', '', d)} \ - \ - --cross-prefix=${TARGET_PREFIX} \ - \ - --ld="${CCLD}" \ - --cc="${CC}" \ - --cxx="${CXX}" \ - --arch=${TARGET_ARCH} \ - --target-os="linux" \ - --enable-cross-compile \ - --extra-cflags="${TARGET_CFLAGS} ${HOST_CC_ARCH}${TOOLCHAIN_OPTIONS}" \ - --extra-ldflags="${TARGET_LDFLAGS}" \ - --sysroot="${STAGING_DIR_TARGET}" \ - --enable-hardcoded-tables \ - ${EXTRA_FFCONF} \ - --libdir=${libdir} \ - --shlibdir=${libdir} \ - --datadir=${datadir}/ffmpeg \ - ${@bb.utils.contains('AVAILTUNES', 'mips32r2', '', '--disable-mipsdsp --disable-mipsdspr2', d)} \ -" - -do_configure() { - ${S}/configure ${EXTRA_OECONF} -} - -PACKAGES_DYNAMIC += "^lib(av(codec|device|filter|format|util|resample)|swscale|swresample|postproc).*" - -# ffmpeg disables PIC on some platforms (e.g. x86-32) -INSANE_SKIP_${MLPREFIX}libavcodec = "textrel" -INSANE_SKIP_${MLPREFIX}libavdevice = "textrel" -INSANE_SKIP_${MLPREFIX}libavfilter = "textrel" -INSANE_SKIP_${MLPREFIX}libavformat = "textrel" -INSANE_SKIP_${MLPREFIX}libavutil = "textrel" -INSANE_SKIP_${MLPREFIX}libavresample = "textrel" -INSANE_SKIP_${MLPREFIX}libswscale = "textrel" -INSANE_SKIP_${MLPREFIX}libswresample = "textrel" -INSANE_SKIP_${MLPREFIX}libpostproc = "textrel" - -python populate_packages_prepend() { - av_libdir = d.expand('${libdir}') - av_pkgconfig = d.expand('${libdir}/pkgconfig') - - # Runtime package - do_split_packages(d, av_libdir, '^lib(.*)\.so\..*', - output_pattern='lib%s', - description='libav %s library', - extra_depends='', - prepend=True, - allow_links=True) - - # Development packages (-dev, -staticdev) - do_split_packages(d, av_libdir, '^lib(.*)\.so$', - output_pattern='lib%s-dev', - description='libav %s development package', - extra_depends='${PN}-dev', - prepend=True, - allow_links=True) - do_split_packages(d, av_pkgconfig, '^lib(.*)\.pc$', - output_pattern='lib%s-dev', - description='libav %s development package', - extra_depends='${PN}-dev', - prepend=True) - do_split_packages(d, av_libdir, '^lib(.*)\.a$', - output_pattern='lib%s-staticdev', - description='libav %s development package - static library', - extra_depends='${PN}-dev', - prepend=True, - allow_links=True) - -} diff --git a/meta-v1000/recipes-multimedia/mpv/mpv_0.24.0.bb b/meta-v1000/recipes-multimedia/mpv/mpv_0.24.0.bb deleted file mode 100644 index bb10eec7..00000000 --- a/meta-v1000/recipes-multimedia/mpv/mpv_0.24.0.bb +++ /dev/null @@ -1,60 +0,0 @@ -SUMMARY = "Open Source multimedia player" -DESCRIPTION = "mpv is a fork of mplayer2 and MPlayer. It shares some features with the former projects while introducing many more." -SECTION = "multimedia" -HOMEPAGE = "http://www.mpv.io/" -DEPENDS = "zlib ffmpeg jpeg virtual/libx11 xsp libxv \ - libxscrnsaver libv4l libxinerama libvdpau \ -" - -REQUIRED_DISTRO_FEATURES = "x11" - -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://LICENSE;md5=91f1cb870c1cc2d31351a4d2595441cb" - -SRC_URI = " \ - https://github.com/mpv-player/mpv/archive/v${PV}.tar.gz;name=mpv \ - http://www.freehackers.org/~tnagy/release/waf-1.8.12;name=waf;subdir=${BPN}-${PV} \ -" -SRC_URI[mpv.md5sum] = "5c85d1163911e49315a5bf1ca1fae13d" -SRC_URI[mpv.sha256sum] = "a41854fa0ac35b9c309ad692aaee67c8d4495c3546f11cb4cdd0a124195d3f15" -SRC_URI[waf.md5sum] = "cef4ee82206b1843db082d0b0506bf71" -SRC_URI[waf.sha256sum] = "01bf2beab2106d1558800c8709bc2c8e496d3da4a2ca343fe091f22fca60c98b" - -inherit waf pkgconfig pythonnative distro_features_check - -# Note: both lua and libass are required to get on-screen-display (controls) -PACKAGECONFIG ??= "lua libass" -PACKAGECONFIG[lua] = "--enable-lua,--disable-lua,lua luajit" -PACKAGECONFIG[libass] = "--enable-libass,--disable-libass,libass" -PACKAGECONFIG[libarchive] = "--enable-libarchive,--disable-libarchive,libarchive" -PACKAGECONFIG[jack] = "--enable-jack, --disable-jack, jack" - -SIMPLE_TARGET_SYS = "${@'${TARGET_SYS}'.replace('${TARGET_VENDOR}', '')}" -EXTRA_OECONF = " \ - --prefix=${prefix} \ - --target=${SIMPLE_TARGET_SYS} \ - --confdir=${sysconfdir} \ - --datadir=${datadir} \ - --disable-manpage-build \ - --disable-gl \ - --disable-libsmbclient \ - --disable-encoding \ - --disable-libbluray \ - --disable-dvdread \ - --disable-dvdnav \ - --disable-cdda \ - --disable-uchardet \ - --disable-rubberband \ - --disable-lcms2 \ - --disable-vapoursynth \ - --disable-vapoursynth-lazy \ - ${PACKAGECONFIG_CONFARGS} \ -" - -do_configure_prepend () { - ln -sf waf-1.8.12 ${S}/waf - chmod +x ${S}/waf -} - -FILES_${PN} += "${datadir}/icons" - |