summaryrefslogtreecommitdiffstats
path: root/arch/score/mm/tlb-miss.S
blob: f27651914e8dba916c107853f15853552d907249 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
/*
 * arch/score/mm/tlbex.S
 *
 * Score Processor version.
 *
 * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
 *  Lennox Wu <lennox.wu@sunplusct.com>
 *  Chen Liqin <liqin.chen@sunplusct.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <asm/asmmacro.h>
#include <asm/pgtable-bits.h>
#include <asm/scoreregs.h>

/*
* After this macro runs, the pte faulted on is
* in register PTE, a ptr into the table in which
* the pte belongs is in PTR.
*/
	.macro	load_pte, pte, ptr
	la	\ptr, pgd_current
	lw	\ptr, [\ptr, 0]
	mfcr	\pte, cr6
	srli	\pte, \pte, 22
	slli	\pte, \pte, 2
	add	\ptr, \ptr, \pte
	lw	\ptr, [\ptr, 0]
	mfcr	\pte, cr6
	srli	\pte, \pte, 10
	andi	\pte, 0xffc
	add	\ptr, \ptr, \pte
	lw	\pte, [\ptr, 0]
	.endm

	.macro	pte_reload, ptr
	lw	\ptr, [\ptr, 0]
	mtcr	\ptr, cr12
	nop
	nop
	nop
	nop
	nop
	.endm

	.macro do_fault, write
	SAVE_ALL
	mfcr	r6, cr6
	mv	r4, r0
	ldi	r5, \write
	la	r8, do_page_fault
	brl	r8
	j	ret_from_exception
	.endm

	.macro	pte_writable, pte, ptr, label
	andi	\pte, 0x280
	cmpi.c	\pte, 0x280
	bne	\label
	lw	\pte, [\ptr, 0]		/*reload PTE*/
	.endm

/*
 * Make PTE writable, update software status bits as well,
 * then store at PTR.
 */
	.macro	pte_makewrite, pte, ptr
	ori	\pte, 0x426
	sw	\pte, [\ptr, 0]
	.endm

	.text
ENTRY(score7_FTLB_refill_Handler)
	la	r31, pgd_current	/* get pgd pointer */
	lw	r31, [r31, 0]		/* get the address of PGD */
	mfcr	r30, cr6
	srli	r30, r30, 22		/* PGDIR_SHIFT = 22*/
	slli	r30, r30, 2
	add	r31, r31, r30
	lw	r31, [r31, 0]		/* get the address of the start address of PTE table */

	mfcr	r30, cr9
	andi	r30, 0xfff 		/* equivalent to get PET index and right shift 2 bits */
	add	r31, r31, r30
	lw	r30, [r31, 0]		/* load pte entry */
	mtcr	r30, cr12
	nop
	nop
	nop
	nop
	nop
	mtrtlb
	nop
	nop
	nop
	nop
	nop
	rte				/* 6 cycles to make sure tlb entry works */

ENTRY(score7_KSEG_refill_Handler)
	la	r31, pgd_current	/* get pgd pointer */
	lw	r31, [r31, 0]		/* get the address of PGD */
	mfcr	r30, cr6
	srli	r30, r30, 22		/* PGDIR_SHIFT = 22 */
	slli	r30, r30, 2
	add	r31, r31, r30
	lw	r31, [r31, 0]		/* get the address of the start address of PTE table */

	mfcr	r30, cr6		/* get Bad VPN */
	srli	r30, r30, 10
	andi	r30, 0xffc		/* PTE VPN mask (bit 11~2) */

	add	r31, r31, r30
	lw	r30, [r31, 0]		/* load pte entry */
	mtcr	r30, cr12
	nop
	nop
	nop
	nop
	nop
	mtrtlb
	nop
	nop
	nop
	nop
	nop
	rte				/* 6 cycles to make sure tlb entry works */

nopage_tlbl:
	do_fault	0		/* Read */

ENTRY(handle_tlb_refill)
	load_pte	r30, r31
	pte_writable	r30, r31, handle_tlb_refill_nopage
	pte_makewrite	r30, r31	/* Access|Modify|Dirty|Valid */
	pte_reload	r31
	mtrtlb
	nop
	nop
	nop
	nop
	nop
	rte
handle_tlb_refill_nopage:
	do_fault	0		/* Read */

ENTRY(handle_tlb_invaild)
	load_pte	r30, r31
	stlb				/* find faulting entry */
	pte_writable	r30, r31, handle_tlb_invaild_nopage
	pte_makewrite	r30, r31	/* Access|Modify|Dirty|Valid */
	pte_reload	r31
	mtptlb
	nop
	nop
	nop
	nop
	nop
	rte
handle_tlb_invaild_nopage:
	do_fault	0		/* Read */

ENTRY(handle_mod)
	load_pte	r30, r31
	stlb				/* find faulting entry */
	andi	r30, _PAGE_WRITE	/* Writable? */
	cmpz.c	r30
	beq	nowrite_mod
	lw	r30, [r31, 0]		/* reload into r30 */

	/* Present and writable bits set, set accessed and dirty bits. */
	pte_makewrite	r30, r31

	/* Now reload the entry into the tlb. */
	pte_reload	r31
	mtptlb
	nop
	nop
	nop
	nop
	nop
	rte

nowrite_mod:
	do_fault	1	/* Write */