aboutsummaryrefslogtreecommitdiffstats
path: root/arch/csky/include/asm/atomic.h
blob: e369d73b13e3254570201bf70ae773aa5d6535ce (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __ASM_CSKY_ATOMIC_H
#define __ASM_CSKY_ATOMIC_H

#include <linux/version.h>
#include <asm/cmpxchg.h>
#include <asm/barrier.h>

#ifdef CONFIG_CPU_HAS_LDSTEX

#define __atomic_add_unless __atomic_add_unless
static inline int __atomic_add_unless(atomic_t *v, int a, int u)
{
	unsigned long tmp, ret;

	smp_mb();

	asm volatile (
	"1:	ldex.w		%0, (%3) \n"
	"	mov		%1, %0   \n"
	"	cmpne		%0, %4   \n"
	"	bf		2f	 \n"
	"	add		%0, %2   \n"
	"	stex.w		%0, (%3) \n"
	"	bez		%0, 1b   \n"
	"2:				 \n"
		: "=&r" (tmp), "=&r" (ret)
		: "r" (a), "r"(&v->counter), "r"(u)
		: "memory");

	if (ret != u)
		smp_mb();

	return ret;
}

#define ATOMIC_OP(op, c_op)						\
static inline void atomic_##op(int i, atomic_t *v)			\
{									\
	unsigned long tmp;						\
									\
	asm volatile (							\
	"1:	ldex.w		%0, (%2) \n"				\
	"	" #op "		%0, %1   \n"				\
	"	stex.w		%0, (%2) \n"				\
	"	bez		%0, 1b   \n"				\
		: "=&r" (tmp)						\
		: "r" (i), "r"(&v->counter)				\
		: "memory");						\
}

#define ATOMIC_OP_RETURN(op, c_op)					\
static inline int atomic_##op##_return(int i, atomic_t *v)		\
{									\
	unsigned long tmp, ret;						\
									\
	smp_mb();							\
	asm volatile (							\
	"1:	ldex.w		%0, (%3) \n"				\
	"	" #op "		%0, %2   \n"				\
	"	mov		%1, %0   \n"				\
	"	stex.w		%0, (%3) \n"				\
	"	bez		%0, 1b   \n"				\
		: "=&r" (tmp), "=&r" (ret)				\
		: "r" (i), "r"(&v->counter)				\
		: "memory");						\
	smp_mb();							\
									\
	return ret;							\
}

#define ATOMIC_FETCH_OP(op, c_op)					\
static inline int atomic_fetch_##op(int i, atomic_t *v)			\
{									\
	unsigned long tmp, ret;						\
									\
	smp_mb();							\
	asm volatile (							\
	"1:	ldex.w		%0, (%3) \n"				\
	"	mov		%1, %0   \n"				\
	"	" #op "		%0, %2   \n"				\
	"	stex.w		%0, (%3) \n"				\
	"	bez		%0, 1b   \n"				\
		: "=&r" (tmp), "=&r" (ret)				\
		: "r" (i), "r"(&v->counter)				\
		: "memory");						\
	smp_mb();							\
									\
	return ret;							\
}

#else /* CONFIG_CPU_HAS_LDSTEX */

#include <linux/irqflags.h>

#define __atomic_add_unless __atomic_add_unless
static inline int __atomic_add_unless(atomic_t *v, int a, int u)
{
	unsigned long tmp, ret, flags;

	raw_local_irq_save(flags);

	asm volatile (
	"	ldw		%0, (%3) \n"
	"	mov		%1, %0   \n"
	"	cmpne		%0, %4   \n"
	"	bf		2f	 \n"
	"	add		%0, %2   \n"
	"	stw		%0, (%3) \n"
	"2:				 \n"
		: "=&r" (tmp), "=&r" (ret)
		: "r" (a), "r"(&v->counter), "r"(u)
		: "memory");

	raw_local_irq_restore(flags);

	return ret;
}

#define ATOMIC_OP(op, c_op)						\
static inline void atomic_##op(int i, atomic_t *v)			\
{									\
	unsigned long tmp, flags;					\
									\
	raw_local_irq_save(flags);					\
									\
	asm volatile (							\
	"	ldw		%0, (%2) \n"				\
	"	" #op "		%0, %1   \n"				\
	"	stw		%0, (%2) \n"				\
		: "=&r" (tmp)						\
		: "r" (i), "r"(&v->counter)				\
		: "memory");						\
									\
	raw_local_irq_restore(flags);					\
}

#define ATOMIC_OP_RETURN(op, c_op)					\
static inline int atomic_##op##_return(int i, atomic_t *v)		\
{									\
	unsigned long tmp, ret, flags;					\
									\
	raw_local_irq_save(flags);					\
									\
	asm volatile (							\
	"	ldw		%0, (%3) \n"				\
	"	" #op "		%0, %2   \n"				\
	"	stw		%0, (%3) \n"				\
	"	mov		%1, %0   \n"				\
		: "=&r" (tmp), "=&r" (ret)				\
		: "r" (i), "r"(&v->counter)				\
		: "memory");						\
									\
	raw_local_irq_restore(flags);					\
									\
	return ret;							\
}

#define ATOMIC_FETCH_OP(op, c_op)					\
static inline int atomic_fetch_##op(int i, atomic_t *v)			\
{									\
	unsigned long tmp, ret, flags;					\
									\
	raw_local_irq_save(flags);					\
									\
	asm volatile (							\
	"	ldw		%0, (%3) \n"				\
	"	mov		%1, %0   \n"				\
	"	" #op "		%0, %2   \n"				\
	"	stw		%0, (%3) \n"				\
		: "=&r" (tmp), "=&r" (ret)				\
		: "r" (i), "r"(&v->counter)				\
		: "memory");						\
									\
	raw_local_irq_restore(flags);					\
									\
	return ret;							\
}

#endif /* CONFIG_CPU_HAS_LDSTEX */

#define atomic_add_return atomic_add_return
ATOMIC_OP_RETURN(add, +)
#define atomic_sub_return atomic_sub_return
ATOMIC_OP_RETURN(sub, -)

#define atomic_fetch_add atomic_fetch_add
ATOMIC_FETCH_OP(add, +)
#define atomic_fetch_sub atomic_fetch_sub
ATOMIC_FETCH_OP(sub, -)
#define atomic_fetch_and atomic_fetch_and
ATOMIC_FETCH_OP(and, &)
#define atomic_fetch_or atomic_fetch_or
ATOMIC_FETCH_OP(or, |)
#define atomic_fetch_xor atomic_fetch_xor
ATOMIC_FETCH_OP(xor, ^)

#define atomic_and atomic_and
ATOMIC_OP(and, &)
#define atomic_or atomic_or
ATOMIC_OP(or, |)
#define atomic_xor atomic_xor
ATOMIC_OP(xor, ^)

#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP

#include <asm-generic/atomic.h>

#endif /* __ASM_CSKY_ATOMIC_H */