aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/fpga/altr,freeze-bridge-controller.yaml
blob: fccffeebb2560f5ef1d63110ef6b36676a8e3aff (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera Freeze Bridge Controller

description:
  The Altera Freeze Bridge Controller manages one or more freeze bridges.
  The controller can freeze/disable the bridges which prevents signal
  changes from passing through the bridge. The controller can also
  unfreeze/enable the bridges which allows traffic to pass through the bridge
  normally.

maintainers:
  - Xu Yilun <yilun.xu@intel.com>

allOf:
  - $ref: fpga-bridge.yaml#

properties:
  compatible:
    const: altr,freeze-bridge-controller

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    fpga-bridge@100000450 {
        compatible = "altr,freeze-bridge-controller";
        reg = <0x1000 0x10>;
        bridge-enable = <0>;
    };