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path: root/drivers/clk/tegra/clk-tegra20.c
AgeCommit message (Expand)Author
2023-05-30clk: tegra20: fix gcc-7 constant overflow warningArnd Bergmann
2022-10-26clk: tegra20: Fix refcount leak in tegra20_clock_initMiaoqian Lin
2019-12-01clk: tegra20: Turn EMC clock gate into dividerDmitry Osipenko
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko
2018-05-18clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko
2018-05-18clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko
2018-03-12clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko
2017-11-01clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko
2017-11-01clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding
2016-04-28treewide: Fix typos in printkMasanari Iida
2016-03-02clk: tegra: Remove CLK_IS_ROOTStephen Boyd
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding
2015-11-18clk: tegra: Format tables consistentlyThierry Reding
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding
2015-07-20clk: tegra: Properly include clk.hStephen Boyd
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding
2014-02-17clk: tegra: Add missing Tegra20 fuse clksPeter De Schrijver
2013-12-11clk: tegra: remove bogus PCIE_XCLKStephen Warren
2013-12-11clk: tegra: implement a reset driverStephen Warren
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot
2013-11-26clk: tegra: move tegra20 to common infraPeter De Schrijver
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver
2013-08-19clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan
2013-08-08clk: tegra20: Fix incorrect placement of __initdataSachin Kamat
2013-05-31clk: tegra: Use common of_clk_init functionPrashant Gaikwad
2013-05-20clk: tegra: add ac97 controller clockLucas Stach
2013-05-20clk: tegra: remove USB from clk init tableLucas Stach
2013-05-04Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds
2013-05-02Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds
2013-04-09Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel...Arnd Bergmann
2013-04-04clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver
2013-04-04clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver
2013-04-04clk: tegra: Add PLL post divider tablePeter De Schrijver
2013-04-04clk: tegra: Refactor PLL programming codePeter De Schrijver
2013-04-04clk: tegra: defer application of init tableStephen Warren
2013-04-04clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad
2013-04-04clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding
2013-04-04Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren
2013-04-01clk: tegra: Allow PLLE training to succeedThierry Reding
2013-03-11clk: tegra: No 7.1 super clk dividers on Tegra20Peter De Schrijver
2013-03-04clk: Tegra: Remove duplicate smp_twd clockPrashant Gaikwad