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-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi618
1 files changed, 544 insertions, 74 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 7a9be0acf3f5..7ed0d925a4e9 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -80,6 +80,7 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
qcom,saw = <&saw_l2>;
};
@@ -307,6 +308,8 @@
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
#clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
};
};
};
@@ -416,22 +419,22 @@
regulator;
};
- acc0: clock-controller@f9088000 {
+ acc0: power-manager@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
};
- acc1: clock-controller@f9098000 {
+ acc1: power-manager@f9098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
};
- acc2: clock-controller@f90a8000 {
+ acc2: power-manager@f90a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
};
- acc3: clock-controller@f90b8000 {
+ acc3: power-manager@f90b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
@@ -653,7 +656,7 @@
#size-cells = <0>;
};
- otg: usb@f9a55000 {
+ usb: usb@f9a55000 {
compatible = "qcom,ci-hdrc";
reg = <0xf9a55000 0x200>,
<0xf9a55200 0x200>;
@@ -679,7 +682,7 @@
#phy-cells = <0>;
clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ref", "sleep";
- resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
+ resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
reset-names = "phy", "por";
status = "disabled";
};
@@ -690,7 +693,7 @@
#phy-cells = <0>;
clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
clock-names = "ref", "sleep";
- resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
+ resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>;
reset-names = "phy", "por";
status = "disabled";
};
@@ -1054,9 +1057,14 @@
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>;
+ clock-names = "xo",
+ "sleep_clk";
};
- rpm_msg_ram: memory@fc428000 {
+ rpm_msg_ram: sram@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
@@ -1116,11 +1124,63 @@
};
tsens: thermal-sensor@fc4a9000 {
- compatible = "qcom,msm8974-tsens";
+ compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
reg = <0xfc4a9000 0x1000>, /* TM */
<0xfc4a8000 0x1000>; /* SROT */
- nvmem-cells = <&tsens_calib>, <&tsens_backup>;
- nvmem-cell-names = "calib", "calib_backup";
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base1>, <&tsens_base2>,
+ <&tsens_use_backup>,
+ <&tsens_mode_backup>,
+ <&tsens_base1_backup>, <&tsens_base2_backup>,
+ <&tsens_s0_p1>, <&tsens_s0_p2>,
+ <&tsens_s1_p1>, <&tsens_s1_p2>,
+ <&tsens_s2_p1>, <&tsens_s2_p2>,
+ <&tsens_s3_p1>, <&tsens_s3_p2>,
+ <&tsens_s4_p1>, <&tsens_s4_p2>,
+ <&tsens_s5_p1>, <&tsens_s5_p2>,
+ <&tsens_s6_p1>, <&tsens_s6_p2>,
+ <&tsens_s7_p1>, <&tsens_s7_p2>,
+ <&tsens_s8_p1>, <&tsens_s8_p2>,
+ <&tsens_s9_p1>, <&tsens_s9_p2>,
+ <&tsens_s10_p1>, <&tsens_s10_p2>,
+ <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
+ <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
+ <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
+ <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
+ <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
+ <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
+ <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
+ <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
+ <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
+ <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
+ <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
+ nvmem-cell-names = "mode",
+ "base1", "base2",
+ "use_backup",
+ "mode_backup",
+ "base1_backup", "base2_backup",
+ "s0_p1", "s0_p2",
+ "s1_p1", "s1_p2",
+ "s2_p1", "s2_p2",
+ "s3_p1", "s3_p2",
+ "s4_p1", "s4_p2",
+ "s5_p1", "s5_p2",
+ "s6_p1", "s6_p2",
+ "s7_p1", "s7_p2",
+ "s8_p1", "s8_p2",
+ "s9_p1", "s9_p2",
+ "s10_p1", "s10_p2",
+ "s0_p1_backup", "s0_p2_backup",
+ "s1_p1_backup", "s1_p2_backup",
+ "s2_p1_backup", "s2_p2_backup",
+ "s3_p1_backup", "s3_p2_backup",
+ "s4_p1_backup", "s4_p2_backup",
+ "s5_p1_backup", "s5_p2_backup",
+ "s6_p1_backup", "s6_p2_backup",
+ "s7_p1_backup", "s7_p2_backup",
+ "s8_p1_backup", "s8_p2_backup",
+ "s9_p1_backup", "s9_p2_backup",
+ "s10_p1_backup", "s10_p2_backup";
#qcom,sensors = <11>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
@@ -1137,11 +1197,260 @@
reg = <0xfc4bc000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- tsens_calib: calib@d0 {
- reg = <0xd0 0x18>;
+
+ tsens_base1: base1@d0 {
+ reg = <0xd0 0x1>;
+ bits = <0 8>;
+ };
+
+ tsens_s0_p1: s0-p1@d1 {
+ reg = <0xd1 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s1_p1: s1-p1@d2 {
+ reg = <0xd1 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s2_p1: s2-p1@d2 {
+ reg = <0xd2 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s3_p1: s3-p1@d3 {
+ reg = <0xd3 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s4_p1: s4-p1@d4 {
+ reg = <0xd4 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s5_p1: s5-p1@d4 {
+ reg = <0xd4 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s6_p1: s6-p1@d5 {
+ reg = <0xd5 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s7_p1: s7-p1@d6 {
+ reg = <0xd6 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s8_p1: s8-p1@d7 {
+ reg = <0xd7 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_mode: mode@d7 {
+ reg = <0xd7 0x1>;
+ bits = <6 2>;
+ };
+
+ tsens_s9_p1: s9-p1@d8 {
+ reg = <0xd8 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s10_p1: s10_p1@d8 {
+ reg = <0xd8 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_base2: base2@d9 {
+ reg = <0xd9 0x2>;
+ bits = <4 8>;
+ };
+
+ tsens_s0_p2: s0-p2@da {
+ reg = <0xda 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s1_p2: s1-p2@db {
+ reg = <0xdb 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s2_p2: s2-p2@dc {
+ reg = <0xdc 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s3_p2: s3-p2@dc {
+ reg = <0xdc 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s4_p2: s4-p2@dd {
+ reg = <0xdd 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s5_p2: s5-p2@de {
+ reg = <0xde 0x2>;
+ bits = <2 6>;
+ };
+
+ tsens_s6_p2: s6-p2@df {
+ reg = <0xdf 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s7_p2: s7-p2@e0 {
+ reg = <0xe0 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s8_p2: s8-p2@e0 {
+ reg = <0xe0 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s9_p2: s9-p2@e1 {
+ reg = <0xe1 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s10_p2: s10_p2@e2 {
+ reg = <0xe2 0x2>;
+ bits = <2 6>;
+ };
+
+ tsens_s5_p2_backup: s5-p2_backup@e3 {
+ reg = <0xe3 0x2>;
+ bits = <0 6>;
+ };
+
+ tsens_mode_backup: mode_backup@e3 {
+ reg = <0xe3 0x1>;
+ bits = <6 2>;
+ };
+
+ tsens_s6_p2_backup: s6-p2_backup@e4 {
+ reg = <0xe4 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s7_p2_backup: s7-p2_backup@e4 {
+ reg = <0xe4 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s8_p2_backup: s8-p2_backup@e5 {
+ reg = <0xe5 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s9_p2_backup: s9-p2_backup@e6 {
+ reg = <0xe6 0x2>;
+ bits = <2 6>;
+ };
+
+ tsens_s10_p2_backup: s10_p2_backup@e7 {
+ reg = <0xe7 0x1>;
+ bits = <0 6>;
};
- tsens_backup: backup@440 {
- reg = <0x440 0x10>;
+
+ tsens_base1_backup: base1_backup@440 {
+ reg = <0x440 0x1>;
+ bits = <0 8>;
+ };
+
+ tsens_s0_p1_backup: s0-p1_backup@441 {
+ reg = <0x441 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s1_p1_backup: s1-p1_backup@442 {
+ reg = <0x441 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s2_p1_backup: s2-p1_backup@442 {
+ reg = <0x442 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s3_p1_backup: s3-p1_backup@443 {
+ reg = <0x443 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s4_p1_backup: s4-p1_backup@444 {
+ reg = <0x444 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s5_p1_backup: s5-p1_backup@444 {
+ reg = <0x444 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s6_p1_backup: s6-p1_backup@445 {
+ reg = <0x445 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s7_p1_backup: s7-p1_backup@446 {
+ reg = <0x446 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_use_backup: use_backup@447 {
+ reg = <0x447 0x1>;
+ bits = <5 3>;
+ };
+
+ tsens_s8_p1_backup: s8-p1_backup@448 {
+ reg = <0x448 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s9_p1_backup: s9-p1_backup@448 {
+ reg = <0x448 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s10_p1_backup: s10_p1_backup@449 {
+ reg = <0x449 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_base2_backup: base2_backup@44a {
+ reg = <0x44a 0x2>;
+ bits = <2 8>;
+ };
+
+ tsens_s0_p2_backup: s0-p2_backup@44b {
+ reg = <0x44b 0x3>;
+ bits = <2 6>;
+ };
+
+ tsens_s1_p2_backup: s1-p2_backup@44c {
+ reg = <0x44c 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s2_p2_backup: s2-p2_backup@44c {
+ reg = <0x44c 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s3_p2_backup: s3-p2_backup@44d {
+ reg = <0x44d 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s4_p2_backup: s4-p2_backup@44e {
+ reg = <0x44e 0x1>;
+ bits = <2 6>;
};
};
@@ -1194,7 +1503,7 @@
resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart";
- qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
+ qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -1233,13 +1542,14 @@
};
};
- tcsr_mutex_block: syscon@fd484000 {
- compatible = "syscon";
+ tcsr_mutex: hwlock@fd484000 {
+ compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
reg = <0xfd484000 0x2000>;
+ #hwlock-cells = <1>;
};
tcsr: syscon@fd4a0000 {
- compatible = "syscon";
+ compatible = "qcom,tcsr-msm8974", "syscon";
reg = <0xfd4a0000 0x10000>;
};
@@ -1253,61 +1563,62 @@
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- sdc1_off: sdc1-off {
- clk {
+ sdc1_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
};
- sdc2_off: sdc2-off {
- clk {
+ sdc2_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
- cd {
+ cd-pins {
pins = "gpio54";
+ function = "gpio";
bias-disable;
drive-strength = <2>;
};
};
- blsp1_uart2_default: blsp1-uart2-default {
- rx {
+ blsp1_uart2_default: blsp1-uart2-default-state {
+ rx-pins {
pins = "gpio5";
function = "blsp_uart2";
drive-strength = <2>;
bias-pull-up;
};
- tx {
+ tx-pins {
pins = "gpio4";
function = "blsp_uart2";
drive-strength = <4>;
@@ -1315,15 +1626,15 @@
};
};
- blsp2_uart1_default: blsp2-uart1-default {
- tx-rts {
+ blsp2_uart1_default: blsp2-uart1-default-state {
+ tx-rts-pins {
pins = "gpio41", "gpio44";
function = "blsp_uart7";
drive-strength = <2>;
bias-disable;
};
- rx-cts {
+ rx-cts-pins {
pins = "gpio42", "gpio43";
function = "blsp_uart7";
drive-strength = <2>;
@@ -1331,22 +1642,22 @@
};
};
- blsp2_uart1_sleep: blsp2-uart1-sleep {
+ blsp2_uart1_sleep: blsp2-uart1-sleep-state {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- blsp2_uart4_default: blsp2-uart4-default {
- tx-rts {
+ blsp2_uart4_default: blsp2-uart4-default-state {
+ tx-rts-pins {
pins = "gpio53", "gpio56";
function = "blsp_uart10";
drive-strength = <2>;
bias-disable;
};
- rx-cts {
+ rx-cts-pins {
pins = "gpio54", "gpio55";
function = "blsp_uart10";
drive-strength = <2>;
@@ -1354,42 +1665,42 @@
};
};
- blsp1_i2c1_default: blsp1-i2c1-default {
+ blsp1_i2c1_default: blsp1-i2c1-default-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c1_sleep: blsp1-i2c1-sleep {
+ blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-pull-up;
};
- blsp1_i2c2_default: blsp1-i2c2-default {
+ blsp1_i2c2_default: blsp1-i2c2-default-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c2_sleep: blsp1-i2c2-sleep {
+ blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-pull-up;
};
- blsp1_i2c3_default: blsp1-i2c3-default {
+ blsp1_i2c3_default: blsp1-i2c3-default-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c3_sleep: blsp1-i2c3-sleep {
+ blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
@@ -1400,14 +1711,14 @@
/* BLSP1_I2C5 info is missing */
- blsp1_i2c6_default: blsp1-i2c6-default {
+ blsp1_i2c6_default: blsp1-i2c6-default-state {
pins = "gpio29", "gpio30";
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c6_sleep: blsp1-i2c6-sleep {
+ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
pins = "gpio29", "gpio30";
function = "blsp_i2c6";
drive-strength = <2>;
@@ -1417,14 +1728,14 @@
/* BLSP2_I2C1 info is missing */
- blsp2_i2c2_default: blsp2-i2c2-default {
+ blsp2_i2c2_default: blsp2-i2c2-default-state {
pins = "gpio47", "gpio48";
function = "blsp_i2c8";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c2_sleep: blsp2-i2c2-sleep {
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
pins = "gpio47", "gpio48";
function = "blsp_i2c8";
drive-strength = <2>;
@@ -1435,48 +1746,80 @@
/* BLSP2_I2C4 info is missing */
- blsp2_i2c5_default: blsp2-i2c5-default {
+ blsp2_i2c5_default: blsp2-i2c5-default-state {
pins = "gpio83", "gpio84";
function = "blsp_i2c11";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c5_sleep: blsp2-i2c5-sleep {
+ blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
pins = "gpio83", "gpio84";
function = "blsp_i2c11";
drive-strength = <2>;
bias-pull-up;
};
- blsp2_i2c6_default: blsp2-i2c6-default {
+ blsp2_i2c6_default: blsp2-i2c6-default-state {
pins = "gpio87", "gpio88";
function = "blsp_i2c12";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c6_sleep: blsp2-i2c6-sleep {
+ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
pins = "gpio87", "gpio88";
function = "blsp_i2c12";
drive-strength = <2>;
bias-pull-up;
};
- spi8_default: spi8_default {
- mosi {
+ cci_default: cci-default-state {
+ cci_i2c0_default: cci-i2c0-default-pins {
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c0";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci_i2c1_default: cci-i2c1-default-pins {
+ pins = "gpio21", "gpio22";
+ function = "cci_i2c1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ cci_sleep: cci-sleep-state {
+ cci_i2c0_sleep: cci-i2c0-sleep-pins {
+ pins = "gpio19", "gpio20";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci_i2c1_sleep: cci-i2c1-sleep-pins {
+ pins = "gpio21", "gpio22";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ spi8_default: spi8_default-state {
+ mosi-pins {
pins = "gpio45";
function = "blsp_spi8";
};
- miso {
+ miso-pins {
pins = "gpio46";
function = "blsp_spi8";
};
- cs {
+ cs-pins {
pins = "gpio47";
function = "blsp_spi8";
};
- clk {
+ clk-pins {
pins = "gpio48";
function = "blsp_spi8";
};
@@ -1489,9 +1832,33 @@
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfd8c0000 0x6000>;
- };
-
- mdss: mdss@fd900000 {
+ clocks = <&xo_board>,
+ <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
+ <&gcc GPLL0_VOTE>,
+ <&gcc GPLL1_VOTE>,
+ <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
+ <&dsi0_phy 1>,
+ <&dsi0_phy 0>,
+ <&dsi1_phy 1>,
+ <&dsi1_phy 0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "xo",
+ "mmss_gpll0_vote",
+ "gpll0_vote",
+ "gpll1_vote",
+ "gfx3d_clk_src",
+ "dsi0pll",
+ "dsi0pllbyte",
+ "dsi1pll",
+ "dsi1pllbyte",
+ "hdmipll",
+ "edp_link_clk",
+ "edp_vco_div";
+ };
+
+ mdss: display-subsystem@fd900000 {
compatible = "qcom,mdss";
reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
reg-names = "mdss_phys", "vbif_phys";
@@ -1514,8 +1881,8 @@
#size-cells = <1>;
ranges;
- mdp: mdp@fd900000 {
- compatible = "qcom,mdp5";
+ mdp: display-controller@fd900000 {
+ compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
reg = <0xfd900100 0x22000>;
reg-names = "mdp_phys";
@@ -1541,11 +1908,19 @@
remote-endpoint = <&dsi0_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ mdp5_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
};
};
dsi0: dsi@fd922800 {
- compatible = "qcom,mdss-dsi-ctrl";
+ compatible = "qcom,msm8974-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
reg = <0xfd922800 0x1f8>;
reg-names = "dsi_ctrl";
@@ -1571,7 +1946,6 @@
"core_mmss";
phys = <&dsi0_phy>;
- phy-names = "dsi-phy";
status = "disabled";
@@ -1597,7 +1971,7 @@
};
};
- dsi0_phy: dsi-phy@fd922a00 {
+ dsi0_phy: phy@fd922a00 {
compatible = "qcom,dsi-phy-28nm-hpm";
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x280>,
@@ -1614,6 +1988,111 @@
status = "disabled";
};
+
+ dsi1: dsi@fd922e00 {
+ compatible = "qcom,msm8974-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0xfd922e00 0x1f8>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_BYTE1_CLK>,
+ <&mmcc MDSS_PCLK1_CLK>,
+ <&mmcc MDSS_ESC1_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core",
+ "core_mmss";
+
+ phys = <&dsi1_phy>;
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&mdp5_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi1_phy: phy@fd923000 {
+ compatible = "qcom,dsi-phy-28nm-hpm";
+ reg = <0xfd923000 0xd4>,
+ <0xfd923100 0x280>,
+ <0xfd923380 0x30>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
+ cci: cci@fda0c000 {
+ compatible = "qcom,msm8974-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfda0c000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CCI_CLK>;
+ clock-names = "camss_top_ahb",
+ "cci_ahb",
+ "cci";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cci_default>;
+ pinctrl-1 = <&cci_sleep>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
gpu: adreno@fdb00000 {
@@ -1703,8 +2182,6 @@
qcom,ipc = <&apcs 8 8>;
qcom,smd-edge = <1>;
label = "lpass";
- #address-cells = <1>;
- #size-cells = <0>;
};
};
@@ -1719,13 +2196,6 @@
};
};
- tcsr_mutex: tcsr-mutex {
- compatible = "qcom,tcsr-mutex";
- syscon = <&tcsr_mutex_block 0 0x80>;
-
- #hwlock-cells = <1>;
- };
-
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-02 23:59:54 +0000