diff options
Diffstat (limited to 'Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 104 |
1 files changed, 89 insertions, 15 deletions
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index ee7a8eade3f6..b7a534cef24d 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -2,21 +2,27 @@ # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ %YAML 1.2 --- -$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: TI J721E PCI Host (PCIe Wrapper) maintainers: - Kishon Vijay Abraham I <kishon@ti.com> -allOf: - - $ref: "cdns-pcie-host.yaml#" - properties: compatible: - enum: - - ti,j721e-pcie-host + oneOf: + - const: ti,j721e-pcie-host + - const: ti,j784s4-pcie-host + - description: PCIe controller in AM64 + items: + - const: ti,am64-pcie-host + - const: ti,j721e-pcie-host + - description: PCIe controller in J7200 + items: + - const: ti,j7200-pcie-host + - const: ti,j721e-pcie-host reg: maxItems: 4 @@ -29,29 +35,98 @@ properties: - const: cfg ti,syscon-pcie-ctrl: - description: Phandle to the SYSCON entry required for configuring PCIe mode - and link speed. - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_ctrl register offset within SYSCON + description: Specifier for configuring PCIe mode and link speed. power-domains: maxItems: 1 clocks: - maxItems: 1 - description: clock-specifier to represent input to the PCIe + minItems: 1 + maxItems: 2 + description: |+ + clock-specifier to represent input to the PCIe for 1 item. + 2nd item if present represents reference clock to the connector. clock-names: + minItems: 1 items: - const: fck + - const: pcie_refclk + + dma-coherent: true vendor-id: const: 0x104c device-id: - const: 0xb00d + enum: + - 0xb00d + - 0xb00f + - 0xb010 + - 0xb013 msi-map: true + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: link_state + + interrupt-controller: + type: object + additionalProperties: false + + properties: + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + +allOf: + - $ref: cdns-pcie-host.yaml# + - if: + properties: + compatible: + enum: + - ti,am64-pcie-host + then: + properties: + num-lanes: + const: 1 + + - if: + properties: + compatible: + enum: + - ti,j7200-pcie-host + - ti,j721e-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 2 + + - if: + properties: + compatible: + enum: + - ti,j784s4-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 4 + required: - compatible - reg @@ -65,7 +140,6 @@ required: - vendor-id - device-id - msi-map - - dma-coherent - dma-ranges - ranges - reset-gpios @@ -90,7 +164,7 @@ examples: <0x00 0x0d000000 0x00 0x00800000>, <0x00 0x10000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; |