diff options
Diffstat (limited to 'Documentation/devicetree/bindings/clock/qcom,mmcc.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,mmcc.yaml | 88 |
1 files changed, 82 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml index 03faab5b6a41..acf0c923c24f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Multimedia Clock & Reset Controller Binding +title: Qualcomm Multimedia Clock & Reset Controller maintainers: - Jeffrey Hugo <quic_jhugo@quicinc.com> - Taniya Das <tdas@codeaurora.org> description: | - Qualcomm multimedia clock control module which supports the clocks, resets and + Qualcomm multimedia clock control module provides the clocks, resets and power domains. properties: @@ -32,11 +32,11 @@ properties: clocks: minItems: 8 - maxItems: 10 + maxItems: 13 clock-names: minItems: 8 - maxItems: 10 + maxItems: 13 '#clock-cells': const: 1 @@ -104,6 +104,84 @@ allOf: compatible: contains: enum: + - qcom,mmcc-msm8974 + then: + properties: + clocks: + items: + - description: Board XO source + - description: MMSS GPLL0 voted clock + - description: GPLL0 voted clock + - description: GPLL1 voted clock + - description: GFX3D clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: eDP phy PLL link clock + - description: eDP phy PLL vco clock + + clock-names: + items: + - const: xo + - const: mmss_gpll0_vote + - const: gpll0_vote + - const: gpll1_vote + - const: gfx3d_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + - const: edp_link_clk + - const: edp_vco_div + + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-apq8084 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board sleep source + - description: MMSS GPLL0 voted clock + - description: GPLL0 clock + - description: GPLL0 voted clock + - description: GPLL1 clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: eDP phy PLL link clock + - description: eDP phy PLL vco clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: mmss_gpll0_vote + - const: gpll0 + - const: gpll0_vote + - const: gpll1 + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + - const: edp_link_clk + - const: edp_vco_div + + - if: + properties: + compatible: + contains: + enum: - qcom,mmcc-msm8994 - qcom,mmcc-msm8998 - qcom,mmcc-sdm630 @@ -191,7 +269,6 @@ allOf: - description: HDMI phy PLL clock - description: DisplayPort phy PLL link clock - description: DisplayPort phy PLL vco clock - - description: Test clock clock-names: items: @@ -204,7 +281,6 @@ allOf: - const: hdmipll - const: dplink - const: dpvco - - const: core_bi_pll_test_se - if: properties: |