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path: root/drivers/lguest/interrupts_and_traps.c
AgeCommit message (Expand)Author
2016-04-01lguest, x86/entry/32: Fix handling of guest syscalls using interrupt gatesRusty Russell
2015-05-11x86/asm/entry: Fix remaining use of SYSCALL_VECTORIngo Molnar
2015-04-01lguest: handle traps on the "interrupt suppressed" iret instruction.Rusty Russell
2015-03-24lguest: suppress interrupts for single insn, not range.Rusty Russell
2013-09-06lguest: fix guest kernel stack overflow when TF bit set.Rusty Russell
2011-07-22lguest: update commentsRusty Russell
2011-07-22lguest: don't rewrite vmcall instructionsRusty Russell
2009-10-11headers: remove sched.h from interrupt.hAlexey Dobriyan
2009-07-30lguest: fix comment styleRusty Russell
2009-06-12lguest: allow any process to send interruptsRusty Russell
2009-06-12lguest: improve interrupt handling, speed up stream networkingRusty Russell
2009-06-12lguest: fix race in halt codeRusty Russell
2009-06-12lguest: fix lguest wake on guest clock tick, or fd activityRusty Russell
2009-03-30lguest: use bool instead of intMatias Zabaljauregui
2009-03-30lguest: use KVM hypercallsMatias Zabaljauregui
2008-12-23x86: fix lguest used_vectors breakage, -v2Yinghai Lu
2008-07-29lguest: Guest int3 fixRusty Russell
2008-03-28lguest: comment documentation update.Rusty Russell
2008-01-30lguest: get rid of lg variable assignmentsGlauber de Oliveira Costa
2008-01-30lguest: move changed bitmap to lg_cpuGlauber de Oliveira Costa
2008-01-30lguest: per-vcpu lguest pgdir managementGlauber de Oliveira Costa
2008-01-30lguest: makes special fields be per-vcpuGlauber de Oliveira Costa
2008-01-30lguest: per-vcpu lguest task managementGlauber de Oliveira Costa
2008-01-30lguest: replace lguest_arch with lg_cpu_arch.Glauber de Oliveira Costa
2008-01-30lguest: make registers per-vcpuGlauber de Oliveira Costa
2008-01-30lguest: per-vcpu interrupt processing.Glauber de Oliveira Costa
2008-01-30lguest: per-vcpu lguest timersGlauber de Oliveira Costa
2007-10-25lguest: documentation updateRusty Russell
2007-10-23generalize lgread_u32/lgwrite_u32.Rusty Russell
2007-10-23Boot with virtual == physical to get closer to native Linux.Rusty Russell
2007-10-23Allow guest to specify syscall vector to use.Rusty Russell
2007-10-23Move i386 part of core.c to x86/core.c.Jes Sorensen
2007-10-23Make shadow IDT a complete IDT with 256 entries.Rusty Russell
2007-08-30Fix lguest page-pinning logic ("lguest: bad stack page 0xc057a000")Rusty Russell
2007-08-09lguest: Fix Malicious Guest GDT Host CrashRusty Russell
2007-07-28Provide timespec to guests rather than jiffies clock.Rusty Russell
2007-07-26lguest: documentation VII: FIXMEsRusty Russell
2007-07-26lguest: documentation V: HostRusty Russell
2007-07-26lguest: documentation I: PreparationRusty Russell
2007-07-20lguest: fix sense if IF flag on interrupt injectionRusty Russell
2007-07-19lguest: the host codeRusty Russell
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-08 19:25:14 +0000
CPU1 startup vector for BMIPS4350 * * On some systems the bootloader has already started CPU1 and configured * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is * triggered by the SW1 interrupt. If that is the case we try to move * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380. ***********************************************************************/ LEAF(bmips_smp_movevec) la k0, 1f li k1, CKSEG1 or k0, k1 jr k0 1: /* clear IV, pending IPIs */ mtc0 zero, CP0_CAUSE /* re-enable IRQs to wait for SW1 */ li k0, ST0_IE | ST0_BEV | STATUSF_IP1 mtc0 k0, CP0_STATUS /* set up CPU1 CBR; move BASE to 0xa000_0000 */ li k0, 0xff400000 mtc0 k0, $22, 6 /* set up relocation vector address based on thread ID */ mfc0 k1, $22, 3 srl k1, 16 andi k1, 0x8000 or k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0 or k0, k1 li k1, 0xa0080000 sw k1, 0(k0) /* wait here for SW1 interrupt from bmips_boot_secondary() */ wait la k0, bmips_reset_nmi_vec li k1, CKSEG1 or k0, k1 jr k0 END(bmips_smp_movevec) /*********************************************************************** * Reset/NMI vector * For BMIPS processors that can relocate their exception vectors, this * entire function gets copied to 0x8000_0000. ***********************************************************************/ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) .set push .set noat .align 4 #ifdef CONFIG_SMP /* if the NMI bit is clear, assume this is a CPU1 reset instead */ li k1, (1 << 19) mfc0 k0, CP0_STATUS and k0, k1 beqz k0, bmips_smp_entry #if defined(CONFIG_CPU_BMIPS5000) mfc0 k0, CP0_PRID li k1, PRID_IMP_BMIPS5000 andi k0, 0xff00 bne k0, k1, 1f /* if we're not on core 0, this must be the SMP boot signal */ li k1, (3 << 25) mfc0 k0, $22 and k0, k1 bnez k0, bmips_smp_entry 1: #endif /* CONFIG_CPU_BMIPS5000 */ #endif /* CONFIG_SMP */ /* nope, it's just a regular NMI */ SAVE_ALL move a0, sp /* clear EXL, ERL, BEV so that TLB refills still work */ mfc0 k0, CP0_STATUS li k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE or k0, k1 xor k0, k1 mtc0 k0, CP0_STATUS BARRIER /* jump to the NMI handler function */ la k0, nmi_handler jr k0 RESTORE_ALL .set arch=r4000 eret /*********************************************************************** * CPU1 reset vector (used for the initial boot only) * This is still part of bmips_reset_nmi_vec(). ***********************************************************************/ #ifdef CONFIG_SMP bmips_smp_entry: /* set up CP0 STATUS; enable FPU */ li k0, 0x30000000 mtc0 k0, CP0_STATUS BARRIER /* set local CP0 CONFIG to make kseg0 cacheable, write-back */ mfc0 k0, CP0_CONFIG ori k0, 0x07 xori k0, 0x04 mtc0 k0, CP0_CONFIG mfc0 k0, CP0_PRID andi k0, 0xff00 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) li k1, PRID_IMP_BMIPS43XX bne k0, k1, 2f /* initialize CPU1's local I-cache */ li k0, 0x80000000 li k1, 0x80010000 mtc0 zero, $28 mtc0 zero, $28, 1 BARRIER 1: cache Index_Store_Tag_I, 0(k0) addiu k0, 16 bne k0, k1, 1b b 3f 2: #endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */ #if defined(CONFIG_CPU_BMIPS5000) /* set exception vector base */ li k1, PRID_IMP_BMIPS5000 bne k0, k1, 3f la k0, ebase lw k0, 0(k0) mtc0 k0, $15, 1 BARRIER #endif /* CONFIG_CPU_BMIPS5000 */ 3: /* jump back to kseg0 in case we need to remap the kseg1 area */ la k0, 1f jr k0 1: la k0, bmips_enable_xks01 jalr k0 /* use temporary stack to set up upper memory TLB */ li sp, BMIPS_WARM_RESTART_VEC la k0, plat_wired_tlb_setup jalr k0 /* switch to permanent stack and continue booting */ .global bmips_secondary_reentry bmips_secondary_reentry: la k0, bmips_smp_boot_sp lw sp, 0(k0) la k0, bmips_smp_boot_gp lw gp, 0(k0) la k0, start_secondary jr k0 #endif /* CONFIG_SMP */ .align 4 .global bmips_reset_nmi_vec_end bmips_reset_nmi_vec_end: END(bmips_reset_nmi_vec) .set pop .previous /*********************************************************************** * CPU1 warm restart vector (used for second and subsequent boots). * Also used for S2 standby recovery (PM). * This entire function gets copied to (BMIPS_WARM_RESTART_VEC) ***********************************************************************/ LEAF(bmips_smp_int_vec) .align 4 mfc0 k0, CP0_STATUS ori k0, 0x01 xori k0, 0x01 mtc0 k0, CP0_STATUS eret .align 4 .global bmips_smp_int_vec_end bmips_smp_int_vec_end: END(bmips_smp_int_vec) /*********************************************************************** * XKS01 support * Certain CPUs support extending kseg0 to 1024MB. ***********************************************************************/ LEAF(bmips_enable_xks01) #if defined(CONFIG_XKS01) mfc0 t0, CP0_PRID andi t2, t0, 0xff00 #if defined(CONFIG_CPU_BMIPS4380) li t1, PRID_IMP_BMIPS43XX bne t2, t1, 1f andi t0, 0xff addiu t1, t0, -PRID_REV_BMIPS4380_HI bgtz t1, 2f addiu t0, -PRID_REV_BMIPS4380_LO bltz t0, 2f mfc0 t0, $22, 3 li t1, 0x1ff0 li t2, (1 << 12) | (1 << 9) or t0, t1 xor t0, t1 or t0, t2 mtc0 t0, $22, 3 BARRIER b 2f 1: #endif /* CONFIG_CPU_BMIPS4380 */ #if defined(CONFIG_CPU_BMIPS5000) li t1, PRID_IMP_BMIPS5000 bne t2, t1, 2f mfc0 t0, $22, 5 li t1, 0x01ff li t2, (1 << 8) | (1 << 5) or t0, t1 xor t0, t1 or t0, t2 mtc0 t0, $22, 5 BARRIER #endif /* CONFIG_CPU_BMIPS5000 */ 2: #endif /* defined(CONFIG_XKS01) */ jr ra END(bmips_enable_xks01) .previous
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-08 19:25:13 +0000