diff options
Diffstat (limited to 'drivers/staging/comedi/drivers')
24 files changed, 1145 insertions, 1584 deletions
diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3501.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3501.c deleted file mode 100644 index 375707497896..000000000000 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3501.c +++ /dev/null @@ -1,141 +0,0 @@ -/* Watchdog Related Defines */ - -#define ADDIDATA_TIMER 0 -#define ADDIDATA_WATCHDOG 2 - -/* - * (*insn_config) for the timer subdevice - * - * Configures The Timer, Counter or Watchdog - * Data Pointer contains configuration parameters as below - * data[0] : 0 Configure As Timer - * 1 Configure As Counter - * 2 Configure As Watchdog - * data[1] : 1 Enable Interrupt - * 0 Disable Interrupt - * data[2] : Time Unit - * data[3] : Reload Value - */ -static int apci3501_config_insn_timer(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - struct apci3501_private *devpriv = dev->private; - unsigned int ctrl; - - if (data[0] != ADDIDATA_WATCHDOG && - data[0] != ADDIDATA_TIMER) - return -EINVAL; - - devpriv->tsk_Current = current; - - devpriv->timer_mode = data[0]; - - /* first, disable the watchdog or stop the timer */ - if (devpriv->timer_mode == ADDIDATA_WATCHDOG) { - ctrl = 0; - } else { - ctrl = inl(devpriv->tcw + ADDI_TCW_CTRL_REG); - ctrl &= ~(ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG | - ADDI_TCW_CTRL_ENA); - } - outl(ctrl, devpriv->tcw + ADDI_TCW_CTRL_REG); - - /* enable/disable the timer interrupt */ - ctrl = (data[1] == 1) ? ADDI_TCW_CTRL_IRQ_ENA : 0; - outl(ctrl, devpriv->tcw + ADDI_TCW_CTRL_REG); - - outl(data[2], devpriv->tcw + ADDI_TCW_TIMEBASE_REG); - outl(data[3], devpriv->tcw + ADDI_TCW_RELOAD_REG); - - ctrl = inl(devpriv->tcw + ADDI_TCW_CTRL_REG); - if (devpriv->timer_mode == ADDIDATA_WATCHDOG) { - /* Set the mode (e2->e0) NOTE: this doesn't look correct */ - ctrl |= ~(ADDI_TCW_CTRL_CNT_UP | ADDI_TCW_CTRL_EXT_CLK_MASK | - ADDI_TCW_CTRL_MODE_MASK | ADDI_TCW_CTRL_GATE | - ADDI_TCW_CTRL_TRIG | ADDI_TCW_CTRL_TIMER_ENA | - ADDI_TCW_CTRL_RESET_ENA | ADDI_TCW_CTRL_WARN_ENA | - ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_ENA); - } else { - /* mode 2 */ - ctrl &= ~(ADDI_TCW_CTRL_CNTR_ENA | ADDI_TCW_CTRL_MODE_MASK | - ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG | - ADDI_TCW_CTRL_TIMER_ENA | ADDI_TCW_CTRL_RESET_ENA | - ADDI_TCW_CTRL_WARN_ENA | ADDI_TCW_CTRL_ENA); - ctrl |= ADDI_TCW_CTRL_MODE(2) | ADDI_TCW_CTRL_TIMER_ENA; - } - outl(ctrl, devpriv->tcw + ADDI_TCW_CTRL_REG); - - return insn->n; -} - -/* - * (*insn_write) for the timer subdevice - * - * Start / Stop The Selected Timer , Counter or Watchdog - * Data Pointer contains configuration parameters as below - * data[0] : 0 Timer - * 1 Counter - * 2 Watchdog - * data[1] : 1 Start - * 0 Stop - * 2 Trigger - */ -static int apci3501_write_insn_timer(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - struct apci3501_private *devpriv = dev->private; - unsigned int ctrl; - - if (devpriv->timer_mode == ADDIDATA_WATCHDOG || - devpriv->timer_mode == ADDIDATA_TIMER) { - ctrl = inl(devpriv->tcw + ADDI_TCW_CTRL_REG); - ctrl &= ~(ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG); - - if (data[1] == 1) { /* enable */ - ctrl |= ADDI_TCW_CTRL_ENA; - } else if (data[1] == 0) { /* stop */ - if (devpriv->timer_mode == ADDIDATA_WATCHDOG) - ctrl = 0; - else - ctrl &= ~ADDI_TCW_CTRL_ENA; - } else if (data[1] == 2) { /* trigger */ - ctrl |= ADDI_TCW_CTRL_TRIG; - } - outl(ctrl, devpriv->tcw + ADDI_TCW_CTRL_REG); - } - - inl(devpriv->tcw + ADDI_TCW_STATUS_REG); - return insn->n; -} - -/* - * (*insn_read) for the timer subdevice - * - * Read The Selected Timer, Counter or Watchdog - * Data Pointer contains configuration parameters as below - * data[0] : 0 Timer - * 1 Counter - * 2 Watchdog - * data[1] : Timer Counter Watchdog Number - */ -static int apci3501_read_insn_timer(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - struct apci3501_private *devpriv = dev->private; - - if (devpriv->timer_mode != ADDIDATA_TIMER && - devpriv->timer_mode != ADDIDATA_WATCHDOG) - return -EINVAL; - - data[0] = inl(devpriv->tcw + ADDI_TCW_STATUS_REG) & - ADDI_TCW_STATUS_OVERFLOW; - data[1] = inl(devpriv->tcw + ADDI_TCW_VAL_REG); - - return insn->n; -} diff --git a/drivers/staging/comedi/drivers/addi_apci_3501.c b/drivers/staging/comedi/drivers/addi_apci_3501.c index 40ff91411139..57f0f46de0be 100644 --- a/drivers/staging/comedi/drivers/addi_apci_3501.c +++ b/drivers/staging/comedi/drivers/addi_apci_3501.c @@ -22,12 +22,36 @@ * more details. */ +/* + * Driver: addi_apci_3501 + * Description: ADDI-DATA APCI-3501 Analog output board + * Devices: [ADDI-DATA] APCI-3501 (addi_apci_3501) + * Author: H Hartley Sweeten <hsweeten@visionengravers.com> + * Updated: Mon, 20 Jun 2016 10:57:01 -0700 + * Status: untested + * + * Configuration Options: not applicable, uses comedi PCI auto config + * + * This board has the following features: + * - 4 or 8 analog output channels + * - 2 optically isolated digital inputs + * - 2 optically isolated digital outputs + * - 1 12-bit watchdog/timer + * + * There are 2 versions of the APCI-3501: + * - APCI-3501-4 4 analog output channels + * - APCI-3501-8 8 analog output channels + * + * These boards use the same PCI Vendor/Device IDs. The number of output + * channels used by this driver is determined by reading the EEPROM on + * the board. + * + * The watchdog/timer subdevice is not currently supported. + */ + #include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/sched.h> #include "../comedi_pci.h" -#include "addi_tcw.h" #include "amcc_s5933.h" /* @@ -67,8 +91,6 @@ struct apci3501_private { unsigned long amcc; - unsigned long tcw; - struct task_struct *tsk_Current; unsigned char timer_mode; }; @@ -139,8 +161,6 @@ static int apci3501_ao_insn_write(struct comedi_device *dev, return insn->n; } -#include "addi-data/hwdrv_apci3501.c" - static int apci3501_di_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, @@ -253,37 +273,6 @@ static int apci3501_eeprom_insn_read(struct comedi_device *dev, return insn->n; } -static irqreturn_t apci3501_interrupt(int irq, void *d) -{ - struct comedi_device *dev = d; - struct apci3501_private *devpriv = dev->private; - unsigned int status; - unsigned int ctrl; - - /* Disable Interrupt */ - ctrl = inl(devpriv->tcw + ADDI_TCW_CTRL_REG); - ctrl &= ~(ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG | - ADDI_TCW_CTRL_IRQ_ENA); - outl(ctrl, devpriv->tcw + ADDI_TCW_CTRL_REG); - - status = inl(devpriv->tcw + ADDI_TCW_IRQ_REG); - if (!(status & ADDI_TCW_IRQ)) { - dev_err(dev->class_dev, "IRQ from unknown source\n"); - return IRQ_NONE; - } - - /* Enable Interrupt Send a signal to from kernel to user space */ - send_sig(SIGIO, devpriv->tsk_Current, 0); - ctrl = inl(devpriv->tcw + ADDI_TCW_CTRL_REG); - ctrl &= ~(ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG | - ADDI_TCW_CTRL_IRQ_ENA); - ctrl |= ADDI_TCW_CTRL_IRQ_ENA; - outl(ctrl, devpriv->tcw + ADDI_TCW_CTRL_REG); - inl(devpriv->tcw + ADDI_TCW_STATUS_REG); - - return IRQ_HANDLED; -} - static int apci3501_reset(struct comedi_device *dev) { unsigned int val; @@ -333,17 +322,9 @@ static int apci3501_auto_attach(struct comedi_device *dev, devpriv->amcc = pci_resource_start(pcidev, 0); dev->iobase = pci_resource_start(pcidev, 1); - devpriv->tcw = dev->iobase + APCI3501_TIMER_BASE; ao_n_chan = apci3501_eeprom_get_ao_n_chan(dev); - if (pcidev->irq > 0) { - ret = request_irq(pcidev->irq, apci3501_interrupt, IRQF_SHARED, - dev->board_name, dev); - if (ret == 0) - dev->irq = pcidev->irq; - } - ret = comedi_alloc_subdevices(dev, 5); if (ret) return ret; @@ -383,17 +364,9 @@ static int apci3501_auto_attach(struct comedi_device *dev, s->range_table = &range_digital; s->insn_bits = apci3501_do_insn_bits; - /* Initialize the timer/watchdog subdevice */ + /* Timer/Watchdog subdevice */ s = &dev->subdevices[3]; - s->type = COMEDI_SUBD_TIMER; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = 1; - s->maxdata = 0; - s->len_chanlist = 1; - s->range_table = &range_digital; - s->insn_write = apci3501_write_insn_timer; - s->insn_read = apci3501_read_insn_timer; - s->insn_config = apci3501_config_insn_timer; + s->type = COMEDI_SUBD_UNUSED; /* Initialize the eeprom subdevice */ s = &dev->subdevices[4]; diff --git a/drivers/staging/comedi/drivers/adl_pci9118.c b/drivers/staging/comedi/drivers/adl_pci9118.c index be70bd333807..86450c08f291 100644 --- a/drivers/staging/comedi/drivers/adl_pci9118.c +++ b/drivers/staging/comedi/drivers/adl_pci9118.c @@ -1693,8 +1693,7 @@ static void pci9118_detach(struct comedi_device *dev) pci9118_reset(dev); comedi_pci_detach(dev); pci9118_free_dma(dev); - if (pcidev) - pci_dev_put(pcidev); + pci_dev_put(pcidev); } static struct comedi_driver adl_pci9118_driver = { diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c index 1f9c08a845b6..cb9c2699277e 100644 --- a/drivers/staging/comedi/drivers/cb_pcidas64.c +++ b/drivers/staging/comedi/drivers/cb_pcidas64.c @@ -1,34 +1,34 @@ /* - comedi/drivers/cb_pcidas64.c - This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS - 64xx, 60xx, and 4020 cards. - - Author: Frank Mori Hess <fmhess@users.sourceforge.net> - Copyright (C) 2001, 2002 Frank Mori Hess - - Thanks also go to the following people: - - Steve Rosenbluth, for providing the source code for - his pci-das6402 driver, and source code for working QNX pci-6402 - drivers by Greg Laird and Mariusz Bogacz. None of the code was - used directly here, but it was useful as an additional source of - documentation on how to program the boards. - - John Sims, for much testing and feedback on pcidas-4020 support. - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * comedi/drivers/cb_pcidas64.c + * This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS + * 64xx, 60xx, and 4020 cards. + * + * Author: Frank Mori Hess <fmhess@users.sourceforge.net> + * Copyright (C) 2001, 2002 Frank Mori Hess + * + * Thanks also go to the following people: + * + * Steve Rosenbluth, for providing the source code for + * his pci-das6402 driver, and source code for working QNX pci-6402 + * drivers by Greg Laird and Mariusz Bogacz. None of the code was + * used directly here, but it was useful as an additional source of + * documentation on how to program the boards. + * + * John Sims, for much testing and feedback on pcidas-4020 support. + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* * Driver: cb_pcidas64 @@ -66,19 +66,18 @@ */ /* - -TODO: - make it return error if user attempts an ai command that uses the - external queue, and an ao command simultaneously user counter subdevice - there are a number of boards this driver will support when they are - fully released, but does not yet since the pci device id numbers - are not yet available. - - support prescaled 100khz clock for slow pacing (not available on 6000 - series?) - - make ao fifo size adjustable like ai fifo -*/ + * TODO: + * make it return error if user attempts an ai command that uses the + * external queue, and an ao command simultaneously user counter subdevice + * there are a number of boards this driver will support when they are + * fully released, but does not yet since the pci device id numbers + * are not yet available. + * + * support prescaled 100khz clock for slow pacing (not available on 6000 + * series?) + * + * make ao fifo size adjustable like ai fifo + */ #include <linux/module.h> #include <linux/delay.h> @@ -90,53 +89,56 @@ TODO: #include "plx9080.h" #define TIMER_BASE 25 /* 40MHz master clock */ -/* 100kHz 'prescaled' clock for slow acquisition, - * maybe I'll support this someday */ +/* + * 100kHz 'prescaled' clock for slow acquisition, + * maybe I'll support this someday + */ #define PRESCALED_TIMER_BASE 10000 -#define DMA_BUFFER_SIZE 0x1000 +#define DMA_BUFFER_SIZE 0x1000 +#define DAC_FIFO_SIZE 0x2000 -/* maximum value that can be loaded into board's 24-bit counters*/ +/* maximum value that can be loaded into board's 24-bit counters */ static const int max_counter_value = 0xffffff; /* PCI-DAS64xxx base addresses */ /* devpriv->main_iobase registers */ enum write_only_registers { - INTR_ENABLE_REG = 0x0, /* interrupt enable register */ - HW_CONFIG_REG = 0x2, /* hardware config register */ + INTR_ENABLE_REG = 0x0, /* interrupt enable register */ + HW_CONFIG_REG = 0x2, /* hardware config register */ DAQ_SYNC_REG = 0xc, DAQ_ATRIG_LOW_4020_REG = 0xc, - ADC_CONTROL0_REG = 0x10, /* adc control register 0 */ - ADC_CONTROL1_REG = 0x12, /* adc control register 1 */ + ADC_CONTROL0_REG = 0x10, /* adc control register 0 */ + ADC_CONTROL1_REG = 0x12, /* adc control register 1 */ CALIBRATION_REG = 0x14, - /* lower 16 bits of adc sample interval counter */ + /* lower 16 bits of adc sample interval counter */ ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16, - /* upper 8 bits of adc sample interval counter */ + /* upper 8 bits of adc sample interval counter */ ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18, - /* lower 16 bits of delay interval counter */ + /* lower 16 bits of delay interval counter */ ADC_DELAY_INTERVAL_LOWER_REG = 0x1a, - /* upper 8 bits of delay interval counter */ + /* upper 8 bits of delay interval counter */ ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, - /* lower 16 bits of hardware conversion/scan counter */ + /* lower 16 bits of hardware conversion/scan counter */ ADC_COUNT_LOWER_REG = 0x1e, - /* upper 8 bits of hardware conversion/scan counter */ + /* upper 8 bits of hardware conversion/scan counter */ ADC_COUNT_UPPER_REG = 0x20, - ADC_START_REG = 0x22, /* software trigger to start acquisition */ - ADC_CONVERT_REG = 0x24, /* initiates single conversion */ - ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */ - ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */ + ADC_START_REG = 0x22, /* software trigger to start acquisition */ + ADC_CONVERT_REG = 0x24, /* initiates single conversion */ + ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */ + ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */ ADC_BUFFER_CLEAR_REG = 0x2a, - /* high channel for internal queue, use adc_chan_bits() inline above */ + /* high channel for internal queue, use adc_chan_bits() inline above */ ADC_QUEUE_HIGH_REG = 0x2c, - DAC_CONTROL0_REG = 0x50, /* dac control register 0 */ - DAC_CONTROL1_REG = 0x52, /* dac control register 0 */ - /* lower 16 bits of dac sample interval counter */ + DAC_CONTROL0_REG = 0x50, /* dac control register 0 */ + DAC_CONTROL1_REG = 0x52, /* dac control register 0 */ + /* lower 16 bits of dac sample interval counter */ DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54, - /* upper 8 bits of dac sample interval counter */ + /* upper 8 bits of dac sample interval counter */ DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56, DAC_SELECT_REG = 0x60, DAC_START_REG = 0x64, - DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */ + DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */ }; static inline unsigned int dac_convert_reg(unsigned int channel) @@ -168,8 +170,8 @@ enum read_only_registers { }; enum read_write_registers { - I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */ - /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */ + I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */ + /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */ ADC_QUEUE_FIFO_REG = 0x100, ADC_FIFO_REG = 0x200, /* adc data fifo */ /* dac data fifo, has weird interactions with external channel queue */ @@ -188,50 +190,51 @@ enum dio_counter_registers { /* bit definitions for write-only registers */ enum intr_enable_contents { - ADC_INTR_SRC_MASK = 0x3, /* adc interrupt source mask */ - ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quarter full */ - ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */ - ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */ - ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence mask */ - EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */ - EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done intr */ + ADC_INTR_SRC_MASK = 0x3, /* adc interrupt source mask */ + ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quarter full */ + ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */ + ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */ + ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence mask */ + EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */ + EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done intr */ DAC_INTR_SRC_MASK = 0x30, DAC_INTR_QEMPTY_BITS = 0x0, DAC_INTR_HIGH_CHAN_BITS = 0x10, - EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */ + EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */ EN_DAC_DONE_INTR_BIT = 0x80, - EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */ - EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */ - EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */ - EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */ - EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */ + EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */ + EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */ + EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */ + EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */ + EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */ }; enum hw_config_contents { - MASTER_CLOCK_4020_MASK = 0x3, /* master clock source mask for 4020 */ - INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock */ - BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */ - EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */ - EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue */ - /* use 225 nanosec strobe when loading dac instead of 50 nanosec */ + MASTER_CLOCK_4020_MASK = 0x3, /* master clock source mask for 4020 */ + INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock */ + BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */ + EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */ + EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue */ + /* use 225 nanosec strobe when loading dac instead of 50 nanosec */ SLOW_DAC_BIT = 0x400, - /* bit with unknown function yet given as default value in pci-das64 - * manual */ + /* + * bit with unknown function yet given as default value in pci-das64 + * manual + */ HW_CONFIG_DUMMY_BITS = 0x2000, - /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */ + /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */ DMA_CH_SELECT_BIT = 0x8000, - FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */ - DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */ - DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */ + FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */ + DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */ + DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */ }; -#define DAC_FIFO_SIZE 0x2000 enum daq_atrig_low_4020_contents { - /* use trig/ext clk bnc input for analog gate signal */ + /* use trig/ext clk bnc input for analog gate signal */ EXT_AGATE_BNC_BIT = 0x8000, - /* use trig/ext clk bnc input for external stop trigger signal */ + /* use trig/ext clk bnc input for external stop trigger signal */ EXT_STOP_TRIG_BNC_BIT = 0x4000, - /* use trig/ext clk bnc input for external start trigger signal */ + /* use trig/ext clk bnc input for external start trigger signal */ EXT_START_TRIG_BNC_BIT = 0x2000, }; @@ -241,38 +244,38 @@ static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold) } enum adc_control0_contents { - ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */ - ADC_SOFT_GATE_BITS = 0x1, /* software gate */ - ADC_EXT_GATE_BITS = 0x2, /* external digital gate */ - ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */ - /* level-sensitive gate (for digital) */ + ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */ + ADC_SOFT_GATE_BITS = 0x1, /* software gate */ + ADC_EXT_GATE_BITS = 0x2, /* external digital gate */ + ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */ + /* level-sensitive gate (for digital) */ ADC_GATE_LEVEL_BIT = 0x4, - ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */ + ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */ ADC_START_TRIG_SOFT_BITS = 0x10, ADC_START_TRIG_EXT_BITS = 0x20, ADC_START_TRIG_ANALOG_BITS = 0x30, ADC_START_TRIG_MASK = 0x30, - ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */ - /* external pacing uses falling edge */ + ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */ + /* external pacing uses falling edge */ ADC_EXT_CONV_FALLING_BIT = 0x800, - /* enable hardware scan counter */ + /* enable hardware scan counter */ ADC_SAMPLE_COUNTER_EN_BIT = 0x1000, - ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */ - ADC_ENABLE_BIT = 0x8000, /* master adc enable */ + ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */ + ADC_ENABLE_BIT = 0x8000, /* master adc enable */ }; enum adc_control1_contents { - /* should be set for boards with > 16 channels */ + /* should be set for boards with > 16 channels */ ADC_QUEUE_CONFIG_BIT = 0x1, CONVERT_POLARITY_BIT = 0x10, EOC_POLARITY_BIT = 0x20, - ADC_SW_GATE_BIT = 0x40, /* software gate of adc */ - ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */ + ADC_SW_GATE_BIT = 0x40, /* software gate of adc */ + ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */ RETRIGGER_BIT = 0x800, ADC_LO_CHANNEL_4020_MASK = 0x300, ADC_HI_CHANNEL_4020_MASK = 0xc00, - TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */ - FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */ + TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */ + FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */ CHANNEL_MODE_4020_MASK = 0x3000, ADC_MODE_MASK = 0xf000, }; @@ -296,10 +299,10 @@ enum calibration_contents { SELECT_8800_BIT = 0x1, SELECT_8402_64XX_BIT = 0x2, SELECT_1590_60XX_BIT = 0x2, - CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */ + CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */ SERIAL_DATA_IN_BIT = 0x80, SERIAL_CLOCK_BIT = 0x100, - CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */ + CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */ CAL_GAIN_BIT = 0x800, }; @@ -326,12 +329,12 @@ static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel) }; enum adc_queue_load_contents { - UNIP_BIT = 0x800, /* unipolar/bipolar bit */ - ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */ - /* non-referenced single-ended (common-mode input) */ + UNIP_BIT = 0x800, /* unipolar/bipolar bit */ + ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */ + /* non-referenced single-ended (common-mode input) */ ADC_COMMON_BIT = 0x2000, - QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */ - QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */ + QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */ + QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */ }; static inline uint16_t adc_chan_bits(unsigned int channel) @@ -340,7 +343,7 @@ static inline uint16_t adc_chan_bits(unsigned int channel) }; enum dac_control0_contents { - DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */ + DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */ DAC_CYCLIC_STOP_BIT = 0x4000, DAC_WAVEFORM_MODE_BIT = 0x100, DAC_EXT_UPDATE_FALLING_BIT = 0x80, @@ -360,7 +363,7 @@ enum dac_control1_contents { DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */ DAC1_EXT_REF_BIT = 0x200, DAC0_EXT_REF_BIT = 0x100, - DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */ + DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */ DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */ DAC_SW_GATE_BIT = 0x20, DAC1_UNIPOLAR_BIT = 0x8, @@ -409,9 +412,9 @@ enum i2c_addresses { }; enum range_cal_i2c_contents { - /* bits that set what source the adc converter measures */ + /* bits that set what source the adc converter measures */ ADC_SRC_4020_MASK = 0x70, - /* make bnc trig/ext clock threshold 0V instead of 2.5V */ + /* make bnc trig/ext clock threshold 0V instead of 2.5V */ BNC_TRIG_THRESHOLD_0V_BIT = 0x80, }; @@ -422,7 +425,7 @@ static inline uint8_t adc_src_4020_bits(unsigned int source) static inline uint8_t attenuate_bit(unsigned int channel) { - /* attenuate channel (+-5V input range) */ + /* attenuate channel (+-5V input range) */ return 1 << (channel & 0x3); }; @@ -627,18 +630,18 @@ enum pcidas64_boardid { struct pcidas64_board { const char *name; - int ai_se_chans; /* number of ai inputs in single-ended mode */ - int ai_bits; /* analog input resolution */ - int ai_speed; /* fastest conversion period in ns */ + int ai_se_chans; /* number of ai inputs in single-ended mode */ + int ai_bits; /* analog input resolution */ + int ai_speed; /* fastest conversion period in ns */ const struct comedi_lrange *ai_range_table; const uint8_t *ai_range_code; - int ao_nchan; /* number of analog out channels */ - int ao_bits; /* analog output resolution */ - int ao_scan_speed; /* analog output scan speed */ + int ao_nchan; /* number of analog out channels */ + int ao_bits; /* analog output resolution */ + int ao_scan_speed; /* analog output scan speed */ const struct comedi_lrange *ao_range_table; const int *ao_range_code; const struct hw_fifo_info *const ai_fifo; - /* different board families have slightly different registers */ + /* different board families have slightly different registers */ enum register_layout layout; unsigned has_8255:1; }; @@ -699,7 +702,7 @@ static const struct pcidas64_board pcidas64_boards[] = { .has_8255 = 1, }, [BOARD_PCIDAS6402_12] = { - .name = "pci-das6402/12", /* XXX check */ + .name = "pci-das6402/12", /* XXX check */ .ai_se_chans = 64, .ai_bits = 12, .ai_speed = 5000, @@ -996,7 +999,7 @@ static const struct pcidas64_board pcidas64_boards[] = { .ai_speed = 50, .ao_bits = 12, .ao_nchan = 2, - .ao_scan_speed = 0, /* no hardware pacing on ao */ + .ao_scan_speed = 0, /* no hardware pacing on ao */ .layout = LAYOUT_4020, .ai_range_table = &ai_ranges_4020, .ao_range_table = &ao_ranges_4020, @@ -1005,9 +1008,7 @@ static const struct pcidas64_board pcidas64_boards[] = { .has_8255 = 1, }, #if 0 - /* - * The device id for these boards is unknown - */ + /* The device id for these boards is unknown */ [BOARD_PCIDAS6402_16_JR] = { .name = "pci-das6402/16/jr", @@ -1116,62 +1117,66 @@ static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev, } struct ext_clock_info { - /* master clock divisor to use for scans with external master clock */ + /* master clock divisor to use for scans with external master clock */ unsigned int divisor; - /* chanspec for master clock input when used as scan begin src */ + /* chanspec for master clock input when used as scan begin src */ unsigned int chanspec; }; /* this structure is for data unique to this hardware driver. */ struct pcidas64_private { - /* base addresses (physical) */ + /* base addresses (physical) */ resource_size_t main_phys_iobase; resource_size_t dio_counter_phys_iobase; - /* base addresses (ioremapped) */ + /* base addresses (ioremapped) */ void __iomem *plx9080_iobase; void __iomem *main_iobase; - /* local address (used by dma controller) */ + /* local address (used by dma controller) */ uint32_t local0_iobase; uint32_t local1_iobase; - /* dma buffers for analog input */ + /* dma buffers for analog input */ uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT]; - /* physical addresses of ai dma buffers */ + /* physical addresses of ai dma buffers */ dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT]; - /* array of ai dma descriptors read by plx9080, - * allocated to get proper alignment */ + /* + * array of ai dma descriptors read by plx9080, + * allocated to get proper alignment + */ struct plx_dma_desc *ai_dma_desc; - /* physical address of ai dma descriptor array */ + /* physical address of ai dma descriptor array */ dma_addr_t ai_dma_desc_bus_addr; - /* index of the ai dma descriptor/buffer - * that is currently being used */ + /* + * index of the ai dma descriptor/buffer + * that is currently being used + */ unsigned int ai_dma_index; - /* dma buffers for analog output */ + /* dma buffers for analog output */ uint16_t *ao_buffer[AO_DMA_RING_COUNT]; - /* physical addresses of ao dma buffers */ + /* physical addresses of ao dma buffers */ dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT]; struct plx_dma_desc *ao_dma_desc; dma_addr_t ao_dma_desc_bus_addr; - /* keeps track of buffer where the next ao sample should go */ + /* keeps track of buffer where the next ao sample should go */ unsigned int ao_dma_index; - unsigned int hw_revision; /* stc chip hardware revision number */ - /* last bits sent to INTR_ENABLE_REG register */ + unsigned int hw_revision; /* stc chip hardware revision number */ + /* last bits sent to INTR_ENABLE_REG register */ unsigned int intr_enable_bits; - /* last bits sent to ADC_CONTROL1_REG register */ + /* last bits sent to ADC_CONTROL1_REG register */ uint16_t adc_control1_bits; - /* last bits sent to FIFO_SIZE_REG register */ + /* last bits sent to FIFO_SIZE_REG register */ uint16_t fifo_size_bits; - /* last bits sent to HW_CONFIG_REG register */ + /* last bits sent to HW_CONFIG_REG register */ uint16_t hw_config_bits; uint16_t dac_control1_bits; - /* last bits written to plx9080 control register */ + /* last bits written to plx9080 control register */ uint32_t plx_control_bits; - /* last bits written to plx interrupt control and status register */ + /* last bits written to plx interrupt control and status register */ uint32_t plx_intcsr_bits; - /* index of calibration source readable through ai ch0 */ + /* index of calibration source readable through ai ch0 */ int calibration_source; - /* bits written to i2c calibration/range register */ + /* bits written to i2c calibration/range register */ uint8_t i2c_cal_range_bits; - /* configure digital triggers to trigger on falling edge */ + /* configure digital triggers to trigger on falling edge */ unsigned int ext_trig_falling; short ai_cmd_running; unsigned int ai_fifo_segment_length; @@ -1224,7 +1229,7 @@ static void abort_dma(struct comedi_device *dev, unsigned int channel) struct pcidas64_private *devpriv = dev->private; unsigned long flags; - /* spinlock for plx dma control/status reg */ + /* spinlock for plx dma control/status reg */ spin_lock_irqsave(&dev->spinlock, flags); plx9080_abort_dma(devpriv->plx9080_iobase, channel); @@ -1271,7 +1276,7 @@ static void enable_ai_interrupts(struct comedi_device *dev, * if CMDF_WAKE_EOS flag is set. */ if (cmd->flags & CMDF_WAKE_EOS) { - /* 4020 doesn't support pio transfers except for fifo dregs */ + /* 4020 doesn't support pio transfers except for fifo dregs */ if (board->layout != LAYOUT_4020) bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT; } @@ -1305,36 +1310,40 @@ static void init_plx9080(struct comedi_device *dev) abort_dma(dev, 0); abort_dma(dev, 1); - /* configure dma0 mode */ + /* configure dma0 mode */ bits = 0; - /* enable ready input, not sure if this is necessary */ + /* enable ready input, not sure if this is necessary */ bits |= PLX_DMAMODE_READYIEN; - /* enable bterm, not sure if this is necessary */ + /* enable bterm, not sure if this is necessary */ bits |= PLX_DMAMODE_BTERMIEN; - /* enable dma chaining */ + /* enable dma chaining */ bits |= PLX_DMAMODE_CHAINEN; - /* enable interrupt on dma done - * (probably don't need this, since chain never finishes) */ + /* + * enable interrupt on dma done + * (probably don't need this, since chain never finishes) + */ bits |= PLX_DMAMODE_DONEIEN; - /* don't increment local address during transfers - * (we are transferring from a fixed fifo register) */ + /* + * don't increment local address during transfers + * (we are transferring from a fixed fifo register) + */ bits |= PLX_DMAMODE_LACONST; - /* route dma interrupt to pci bus */ + /* route dma interrupt to pci bus */ bits |= PLX_DMAMODE_INTRPCI; - /* enable demand mode */ + /* enable demand mode */ bits |= PLX_DMAMODE_DEMAND; - /* enable local burst mode */ + /* enable local burst mode */ bits |= PLX_DMAMODE_BURSTEN; - /* 4020 uses 32 bit dma */ + /* 4020 uses 32 bit dma */ if (board->layout == LAYOUT_4020) - bits |= PLX_DMAMODE_WIDTH32; - else /* localspace0 bus is 16 bits wide */ - bits |= PLX_DMAMODE_WIDTH16; + bits |= PLX_DMAMODE_WIDTH_32; + else /* localspace0 bus is 16 bits wide */ + bits |= PLX_DMAMODE_WIDTH_16; writel(bits, plx_iobase + PLX_REG_DMAMODE1); if (ao_cmd_is_supported(board)) writel(bits, plx_iobase + PLX_REG_DMAMODE0); - /* enable interrupts on plx 9080 */ + /* enable interrupts on plx 9080 */ devpriv->plx_intcsr_bits |= PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN | PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN | @@ -1376,7 +1385,7 @@ static int set_ai_fifo_segment_length(struct comedi_device *dev, if (num_entries > fifo->max_segment_length) num_entries = fifo->max_segment_length; - /* 1 == 256 entries, 2 == 512 entries, etc */ + /* 1 == 256 entries, 2 == 512 entries, etc */ num_increments = DIV_ROUND_CLOSEST(num_entries, increment_size); bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask; @@ -1442,7 +1451,7 @@ static void init_stc_registers(struct comedi_device *dev) writew(devpriv->adc_control1_bits, devpriv->main_iobase + ADC_CONTROL1_REG); - /* 6402/16 manual says this register must be initialized to 0xff? */ + /* 6402/16 manual says this register must be initialized to 0xff? */ writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT; @@ -1457,7 +1466,7 @@ static void init_stc_registers(struct comedi_device *dev) spin_unlock_irqrestore(&dev->spinlock, flags); - /* set fifos to maximum size */ + /* set fifos to maximum size */ devpriv->fifo_size_bits |= DAC_FIFO_BITS; set_ai_fifo_segment_length(dev, board->ai_fifo->max_segment_length); @@ -1478,7 +1487,7 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) struct pcidas64_private *devpriv = dev->private; int i; - /* allocate pci dma buffers */ + /* allocate pci dma buffers */ for (i = 0; i < ai_dma_ring_count(board); i++) { devpriv->ai_buffer[i] = dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE, @@ -1499,7 +1508,7 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) return -ENOMEM; } } - /* allocate dma descriptors */ + /* allocate dma descriptors */ devpriv->ai_dma_desc = dma_alloc_coherent(&pcidev->dev, sizeof(struct plx_dma_desc) * ai_dma_ring_count(board), @@ -1517,7 +1526,7 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) if (!devpriv->ao_dma_desc) return -ENOMEM; } - /* initialize dma descriptors */ + /* initialize dma descriptors */ for (i = 0; i < ai_dma_ring_count(board); i++) { devpriv->ai_dma_desc[i].pci_start_addr = cpu_to_le32(devpriv->ai_buffer_bus_addr[i]); @@ -1618,13 +1627,11 @@ static void i2c_set_sda(struct comedi_device *dev, int state) void __iomem *plx_control_addr = devpriv->plx9080_iobase + PLX_REG_CNTRL; - if (state) { - /* set data line high */ + if (state) { /* set data line high */ devpriv->plx_control_bits &= ~data_bit; writel(devpriv->plx_control_bits, plx_control_addr); udelay(i2c_high_udelay); - } else { /* set data line low */ - + } else { /* set data line low */ devpriv->plx_control_bits |= data_bit; writel(devpriv->plx_control_bits, plx_control_addr); udelay(i2c_low_udelay); @@ -1639,13 +1646,11 @@ static void i2c_set_scl(struct comedi_device *dev, int state) void __iomem *plx_control_addr = devpriv->plx9080_iobase + PLX_REG_CNTRL; - if (state) { - /* set clock line high */ + if (state) { /* set clock line high */ devpriv->plx_control_bits &= ~clock_bit; writel(devpriv->plx_control_bits, plx_control_addr); udelay(i2c_high_udelay); - } else { /* set clock line low */ - + } else { /* set clock line low */ devpriv->plx_control_bits |= clock_bit; writel(devpriv->plx_control_bits, plx_control_addr); udelay(i2c_low_udelay); @@ -1674,7 +1679,7 @@ static int i2c_read_ack(struct comedi_device *dev) i2c_set_sda(dev, 1); i2c_set_scl(dev, 1); - return 0; /* return fake acknowledge bit */ + return 0; /* return fake acknowledge bit */ } /* send start bit */ @@ -1707,23 +1712,23 @@ static void i2c_write(struct comedi_device *dev, unsigned int address, * eeprom and i2c bus */ - /* make sure we dont send anything to eeprom */ + /* make sure we dont send anything to eeprom */ devpriv->plx_control_bits &= ~PLX_CNTRL_EECS; i2c_stop(dev); i2c_start(dev); - /* send address and write bit */ + /* send address and write bit */ bitstream = (address << 1) & ~read_bit; i2c_write_byte(dev, bitstream); - /* get acknowledge */ + /* get acknowledge */ if (i2c_read_ack(dev) != 0) { dev_err(dev->class_dev, "failed: no acknowledge\n"); i2c_stop(dev); return; } - /* write data bytes */ + /* write data bytes */ for (i = 0; i < length; i++) { i2c_write_byte(dev, data[i]); if (i2c_read_ack(dev) != 0) { @@ -1770,8 +1775,8 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, range = CR_RANGE(insn->chanspec); aref = CR_AREF(insn->chanspec); - /* disable card's analog input interrupt sources and pacing */ - /* 4020 generates dac done interrupts even though they are disabled */ + /* disable card's analog input interrupt sources and pacing */ + /* 4020 generates dac done interrupts even though they are disabled */ disable_ai_pacing(dev); spin_lock_irqsave(&dev->spinlock, flags); @@ -1784,12 +1789,12 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, spin_unlock_irqrestore(&dev->spinlock, flags); if (board->layout != LAYOUT_4020) { - /* use internal queue */ + /* use internal queue */ devpriv->hw_config_bits &= ~EXT_QUEUE_BIT; writew(devpriv->hw_config_bits, devpriv->main_iobase + HW_CONFIG_REG); - /* ALT_SOURCE is internal calibration reference */ + /* ALT_SOURCE is internal calibration reference */ if (insn->chanspec & CR_ALT_SOURCE) { unsigned int cal_en_bit; @@ -1811,19 +1816,19 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, */ writew(0, devpriv->main_iobase + CALIBRATION_REG); } - /* load internal queue */ + /* load internal queue */ bits = 0; - /* set gain */ + /* set gain */ bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec)); - /* set single-ended / differential */ + /* set single-ended / differential */ bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF); if (aref == AREF_COMMON) bits |= ADC_COMMON_BIT; bits |= adc_chan_bits(channel); - /* set stop channel */ + /* set stop channel */ writew(adc_chan_bits(channel), devpriv->main_iobase + ADC_QUEUE_HIGH_REG); - /* set start channel, and rest of settings */ + /* set start channel, and rest of settings */ writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG); } else { uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits; @@ -1835,7 +1840,7 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, } else { /* select BNC inputs */ devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4); } - /* select range */ + /* select range */ if (range == 0) devpriv->i2c_cal_range_bits |= attenuate_bit(channel); else @@ -1862,14 +1867,14 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, } for (n = 0; n < insn->n; n++) { - /* clear adc buffer (inside loop for 4020 sake) */ + /* clear adc buffer (inside loop for 4020 sake) */ writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG); /* trigger conversion, bits sent only matter for 4020 */ writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)), devpriv->main_iobase + ADC_CONVERT_REG); - /* wait for data */ + /* wait for data */ ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0); if (ret) return ret; @@ -2249,7 +2254,7 @@ static void setup_sample_counters(struct comedi_device *dev, { struct pcidas64_private *devpriv = dev->private; - /* load hardware conversion counter */ + /* load hardware conversion counter */ if (use_hw_sample_counter(cmd)) { writew(cmd->stop_arg & 0xffff, devpriv->main_iobase + ADC_COUNT_LOWER_REG); @@ -2277,7 +2282,7 @@ static inline unsigned int dma_transfer_size(struct comedi_device *dev) static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev, const struct comedi_cmd *cmd) { - /* supposed to load counter with desired divisor minus 3 */ + /* supposed to load counter with desired divisor minus 3 */ return cmd->convert_arg / TIMER_BASE - 3; } @@ -2286,7 +2291,7 @@ static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev, { uint32_t count; - /* figure out how long we need to delay at end of scan */ + /* figure out how long we need to delay at end of scan */ switch (cmd->scan_begin_src) { case TRIG_TIMER: count = (cmd->scan_begin_arg - @@ -2315,13 +2320,13 @@ static uint32_t ai_convert_counter_4020(struct comedi_device *dev, case TRIG_OTHER: divisor = devpriv->ext_clock.divisor; break; - default: /* should never happen */ + default: /* should never happen */ dev_err(dev->class_dev, "bug! failed to set ai pacing!\n"); divisor = 1000; break; } - /* supposed to load counter with desired divisor minus 2 for 4020 */ + /* supposed to load counter with desired divisor minus 2 for 4020 */ return divisor - 2; } @@ -2330,7 +2335,7 @@ static void select_master_clock_4020(struct comedi_device *dev, { struct pcidas64_private *devpriv = dev->private; - /* select internal/external master clock */ + /* select internal/external master clock */ devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK; if (cmd->scan_begin_src == TRIG_OTHER) { int chanspec = devpriv->ext_clock.chanspec; @@ -2366,7 +2371,7 @@ static inline void dma_start_sync(struct comedi_device *dev, struct pcidas64_private *devpriv = dev->private; unsigned long flags; - /* spinlock for plx dma control/status reg */ + /* spinlock for plx dma control/status reg */ spin_lock_irqsave(&dev->spinlock, flags); writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR, devpriv->plx9080_iobase + PLX_REG_DMACSR(channel)); @@ -2390,16 +2395,16 @@ static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd) scan_counter = ai_scan_counter_6xxx(dev, cmd); } - /* load lower 16 bits of convert interval */ + /* load lower 16 bits of convert interval */ writew(convert_counter & 0xffff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG); - /* load upper 8 bits of convert interval */ + /* load upper 8 bits of convert interval */ writew((convert_counter >> 16) & 0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); - /* load lower 16 bits of scan delay */ + /* load lower 16 bits of scan delay */ writew(scan_counter & 0xffff, devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG); - /* load upper 8 bits of scan delay */ + /* load upper 8 bits of scan delay */ writew((scan_counter >> 16) & 0xff, devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG); } @@ -2435,26 +2440,26 @@ static int setup_channel_queue(struct comedi_device *dev, writew(devpriv->hw_config_bits, devpriv->main_iobase + HW_CONFIG_REG); bits = 0; - /* set channel */ + /* set channel */ bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0])); - /* set gain */ + /* set gain */ bits |= ai_range_bits_6xxx(dev, CR_RANGE(cmd->chanlist[0])); - /* set single-ended / differential */ + /* set single-ended / differential */ bits |= se_diff_bit_6xxx(dev, CR_AREF(cmd->chanlist[0]) == AREF_DIFF); if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON) bits |= ADC_COMMON_BIT; - /* set stop channel */ + /* set stop channel */ writew(adc_chan_bits (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])), devpriv->main_iobase + ADC_QUEUE_HIGH_REG); - /* set start channel, and rest of settings */ + /* set start channel, and rest of settings */ writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG); } else { - /* use external queue */ + /* use external queue */ if (dev->write_subdev && dev->write_subdev->busy) { warn_external_queue(dev); return -EBUSY; @@ -2462,30 +2467,30 @@ static int setup_channel_queue(struct comedi_device *dev, devpriv->hw_config_bits |= EXT_QUEUE_BIT; writew(devpriv->hw_config_bits, devpriv->main_iobase + HW_CONFIG_REG); - /* clear DAC buffer to prevent weird interactions */ + /* clear DAC buffer to prevent weird interactions */ writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG); - /* clear queue pointer */ + /* clear queue pointer */ writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG); - /* load external queue */ + /* load external queue */ for (i = 0; i < cmd->chanlist_len; i++) { bits = 0; - /* set channel */ + /* set channel */ bits |= adc_chan_bits(CR_CHAN(cmd-> chanlist[i])); - /* set gain */ + /* set gain */ bits |= ai_range_bits_6xxx(dev, CR_RANGE(cmd-> chanlist [i])); - /* set single-ended / differential */ + /* set single-ended / differential */ bits |= se_diff_bit_6xxx(dev, CR_AREF(cmd-> chanlist[i]) == AREF_DIFF); if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON) bits |= ADC_COMMON_BIT; - /* mark end of queue */ + /* mark end of queue */ if (i == cmd->chanlist_len - 1) bits |= QUEUE_EOSCAN_BIT | QUEUE_EOSEQ_BIT; @@ -2498,7 +2503,7 @@ static int setup_channel_queue(struct comedi_device *dev, * but required for reliable operation */ writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG); - /* prime queue holding register */ + /* prime queue holding register */ writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG); } } else { @@ -2507,7 +2512,7 @@ static int setup_channel_queue(struct comedi_device *dev, devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK; /* select BNC inputs */ devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4); - /* select ranges */ + /* select ranges */ for (i = 0; i < cmd->chanlist_len; i++) { unsigned int channel = CR_CHAN(cmd->chanlist[i]); unsigned int range = CR_RANGE(cmd->chanlist[i]); @@ -2579,7 +2584,7 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) if (retval < 0) return retval; - /* make sure internal calibration source is turned off */ + /* make sure internal calibration source is turned off */ writew(0, devpriv->main_iobase + CALIBRATION_REG); set_ai_pacing(dev, cmd); @@ -2595,10 +2600,10 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) if (board->layout != LAYOUT_4020) { devpriv->adc_control1_bits &= ~ADC_MODE_MASK; if (cmd->convert_src == TRIG_EXT) - /* good old mode 13 */ + /* good old mode 13 */ devpriv->adc_control1_bits |= adc_mode_bits(13); else - /* mode 8. What else could you need? */ + /* mode 8. What else could you need? */ devpriv->adc_control1_bits |= adc_mode_bits(8); } else { devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK; @@ -2618,20 +2623,20 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->main_iobase + ADC_CONTROL1_REG); spin_unlock_irqrestore(&dev->spinlock, flags); - /* clear adc buffer */ + /* clear adc buffer */ writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG); if ((cmd->flags & CMDF_WAKE_EOS) == 0 || board->layout == LAYOUT_4020) { devpriv->ai_dma_index = 0; - /* set dma transfer size */ + /* set dma transfer size */ for (i = 0; i < ai_dma_ring_count(board); i++) devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(dma_transfer_size(dev) * sizeof(uint16_t)); - /* give location of first dma descriptor */ + /* give location of first dma descriptor */ load_first_dma_descriptor(dev, 1, devpriv->ai_dma_desc_bus_addr | PLX_DMADPR_DESCPCI | @@ -2657,7 +2662,7 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT; if (cmd->flags & CMDF_WAKE_EOS) bits |= ADC_DMA_DISABLE_BIT; - /* set start trigger */ + /* set start trigger */ if (cmd->start_src == TRIG_EXT) { bits |= ADC_START_TRIG_EXT_BITS; if (cmd->start_arg & CR_INVERT) @@ -2673,7 +2678,7 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) spin_unlock_irqrestore(&dev->spinlock, flags); - /* start acquisition */ + /* start acquisition */ if (cmd->start_src == TRIG_NOW) writew(0, devpriv->main_iobase + ADC_START_REG); @@ -2691,7 +2696,7 @@ static void pio_drain_ai_fifo_16(struct comedi_device *dev) int num_samples; do { - /* get least significant 15 bits */ + /* get least significant 15 bits */ read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff; write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & @@ -2796,14 +2801,14 @@ static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR(channel); - /* loop until we have read all the full buffers */ + /* loop until we have read all the full buffers */ for (j = 0, next_transfer_addr = readl(pci_addr_reg); (next_transfer_addr < devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] || next_transfer_addr >= devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] + DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board); j++) { - /* transfer data from dma buffer to comedi buffer */ + /* transfer data from dma buffer to comedi buffer */ num_samples = comedi_nsamples_left(s, dma_transfer_size(dev)); comedi_buf_write_samples(s, devpriv->ai_buffer[devpriv->ai_dma_index], @@ -2829,15 +2834,15 @@ static void handle_ai_interrupt(struct comedi_device *dev, uint8_t dma1_status; unsigned long flags; - /* check for fifo overrun */ + /* check for fifo overrun */ if (status & ADC_OVERRUN_BIT) { dev_err(dev->class_dev, "fifo overrun\n"); async->events |= COMEDI_CB_ERROR; } - /* spin lock makes sure no one else changes plx dma control reg */ + /* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave(&dev->spinlock, flags); dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1); - if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */ + if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */ writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR, devpriv->plx9080_iobase + PLX_REG_DMACSR1); @@ -2846,7 +2851,7 @@ static void handle_ai_interrupt(struct comedi_device *dev, } spin_unlock_irqrestore(&dev->spinlock, flags); - /* drain fifo with pio */ + /* drain fifo with pio */ if ((status & ADC_DONE_BIT) || ((cmd->flags & CMDF_WAKE_EOS) && (status & ADC_INTR_PENDING_BIT) && @@ -2859,7 +2864,7 @@ static void handle_ai_interrupt(struct comedi_device *dev, spin_unlock_irqrestore(&dev->spinlock, flags); } } - /* if we are have all the data, then quit */ + /* if we are have all the data, then quit */ if ((cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg) || (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) @@ -3012,7 +3017,7 @@ static void handle_ao_interrupt(struct comedi_device *dev, async = s->async; cmd = &async->cmd; - /* spin lock makes sure no one else changes plx dma control reg */ + /* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave(&dev->spinlock, flags); dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0); if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */ @@ -3106,15 +3111,15 @@ static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, int chan = CR_CHAN(insn->chanspec); int range = CR_RANGE(insn->chanspec); - /* do some initializing */ + /* do some initializing */ writew(0, devpriv->main_iobase + DAC_CONTROL0_REG); - /* set range */ + /* set range */ set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range); writew(devpriv->dac_control1_bits, devpriv->main_iobase + DAC_CONTROL1_REG); - /* write to channel */ + /* write to channel */ if (board->layout == LAYOUT_4020) { writew(data[0] & 0xff, devpriv->main_iobase + dac_lsb_4020_reg(chan)); @@ -3124,7 +3129,7 @@ static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, writew(data[0], devpriv->main_iobase + dac_convert_reg(chan)); } - /* remember output value */ + /* remember output value */ s->readback[chan] = data[0]; return 1; @@ -3556,7 +3561,7 @@ static int caldac_i2c_write(struct comedi_device *dev, uint8_t serial_bytes[3]; uint8_t i2c_addr; enum pointer_bits { - /* manual has gain and offset bits switched */ + /* manual has gain and offset bits switched */ OFFSET_0_2 = 0x1, GAIN_0_2 = 0x2, OFFSET_1_3 = 0x4, @@ -3567,35 +3572,35 @@ static int caldac_i2c_write(struct comedi_device *dev, }; switch (caldac_channel) { - case 0: /* chan 0 offset */ + case 0: /* chan 0 offset */ i2c_addr = CALDAC0_I2C_ADDR; serial_bytes[0] = OFFSET_0_2; break; - case 1: /* chan 1 offset */ + case 1: /* chan 1 offset */ i2c_addr = CALDAC0_I2C_ADDR; serial_bytes[0] = OFFSET_1_3; break; - case 2: /* chan 2 offset */ + case 2: /* chan 2 offset */ i2c_addr = CALDAC1_I2C_ADDR; serial_bytes[0] = OFFSET_0_2; break; - case 3: /* chan 3 offset */ + case 3: /* chan 3 offset */ i2c_addr = CALDAC1_I2C_ADDR; serial_bytes[0] = OFFSET_1_3; break; - case 4: /* chan 0 gain */ + case 4: /* chan 0 gain */ i2c_addr = CALDAC0_I2C_ADDR; serial_bytes[0] = GAIN_0_2; break; - case 5: /* chan 1 gain */ + case 5: /* chan 1 gain */ i2c_addr = CALDAC0_I2C_ADDR; serial_bytes[0] = GAIN_1_3; break; - case 6: /* chan 2 gain */ + case 6: /* chan 2 gain */ i2c_addr = CALDAC1_I2C_ADDR; serial_bytes[0] = GAIN_0_2; break; - case 7: /* chan 3 gain */ + case 7: /* chan 3 gain */ i2c_addr = CALDAC1_I2C_ADDR; serial_bytes[0] = GAIN_1_3; break; @@ -3718,24 +3723,24 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) udelay(eeprom_udelay); devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS; - /* make sure we don't send anything to the i2c bus on 4020 */ + /* make sure we don't send anything to the i2c bus on 4020 */ devpriv->plx_control_bits |= PLX_CNTRL_USERO; writel(devpriv->plx_control_bits, plx_control_addr); - /* activate serial eeprom */ + /* activate serial eeprom */ udelay(eeprom_udelay); devpriv->plx_control_bits |= PLX_CNTRL_EECS; writel(devpriv->plx_control_bits, plx_control_addr); - /* write read command and desired memory address */ + /* write read command and desired memory address */ for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { - /* set bit to be written */ + /* set bit to be written */ udelay(eeprom_udelay); if (bitstream & bit) devpriv->plx_control_bits |= PLX_CNTRL_EEWB; else devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB; writel(devpriv->plx_control_bits, plx_control_addr); - /* clock in bit */ + /* clock in bit */ udelay(eeprom_udelay); devpriv->plx_control_bits |= PLX_CNTRL_EESK; writel(devpriv->plx_control_bits, plx_control_addr); @@ -3743,10 +3748,10 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) devpriv->plx_control_bits &= ~PLX_CNTRL_EESK; writel(devpriv->plx_control_bits, plx_control_addr); } - /* read back value from eeprom memory location */ + /* read back value from eeprom memory location */ value = 0; for (bit = 1 << (value_length - 1); bit; bit >>= 1) { - /* clock out bit */ + /* clock out bit */ udelay(eeprom_udelay); devpriv->plx_control_bits |= PLX_CNTRL_EESK; writel(devpriv->plx_control_bits, plx_control_addr); @@ -3758,7 +3763,7 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) value |= bit; } - /* deactivate eeprom serial input */ + /* deactivate eeprom serial input */ udelay(eeprom_udelay); devpriv->plx_control_bits &= ~PLX_CNTRL_EECS; writel(devpriv->plx_control_bits, plx_control_addr); @@ -3775,9 +3780,7 @@ static int eeprom_read_insn(struct comedi_device *dev, return 1; } -/* - * Allocate and initialize the subdevice structures. - */ +/* Allocate and initialize the subdevice structures. */ static int setup_subdevices(struct comedi_device *dev) { const struct pcidas64_board *board = dev->board_ptr; @@ -3816,7 +3819,7 @@ static int setup_subdevices(struct comedi_device *dev) * (not internal calibration sources) */ devpriv->i2c_cal_range_bits = adc_src_4020_bits(4); - /* set channels to +-5 volt input ranges */ + /* set channels to +-5 volt input ranges */ for (i = 0; i < s->n_chan; i++) devpriv->i2c_cal_range_bits |= attenuate_bit(i); data = devpriv->i2c_cal_range_bits; @@ -3849,7 +3852,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type = COMEDI_SUBD_UNUSED; } - /* digital input */ + /* digital input */ s = &dev->subdevices[2]; if (board->layout == LAYOUT_64XX) { s->type = COMEDI_SUBD_DI; @@ -3862,7 +3865,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type = COMEDI_SUBD_UNUSED; } - /* digital output */ + /* digital output */ if (board->layout == LAYOUT_64XX) { s = &dev->subdevices[3]; s->type = COMEDI_SUBD_DO; @@ -3891,7 +3894,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type = COMEDI_SUBD_UNUSED; } - /* 8 channel dio for 60xx */ + /* 8 channel dio for 60xx */ s = &dev->subdevices[5]; if (board->layout == LAYOUT_60XX) { s->type = COMEDI_SUBD_DIO; @@ -3905,7 +3908,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type = COMEDI_SUBD_UNUSED; } - /* caldac */ + /* caldac */ s = &dev->subdevices[6]; s->type = COMEDI_SUBD_CALIB; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; @@ -3925,7 +3928,7 @@ static int setup_subdevices(struct comedi_device *dev) s->readback[i] = s->maxdata / 2; } - /* 2 channel ad8402 potentiometer */ + /* 2 channel ad8402 potentiometer */ s = &dev->subdevices[7]; if (board->layout == LAYOUT_64XX) { s->type = COMEDI_SUBD_CALIB; @@ -3959,7 +3962,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type = COMEDI_SUBD_UNUSED; } - /* user counter subd XXX */ + /* user counter subd XXX */ s = &dev->subdevices[9]; s->type = COMEDI_SUBD_UNUSED; @@ -4005,7 +4008,7 @@ static int auto_attach(struct comedi_device *dev, return -ENOMEM; } - /* figure out what local addresses are */ + /* figure out what local addresses are */ local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) & PLX_LASRR_MEM_MASK; local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) & diff --git a/drivers/staging/comedi/drivers/das08_cs.c b/drivers/staging/comedi/drivers/das08_cs.c index 9c02b17a2834..317a9b5e4a3b 100644 --- a/drivers/staging/comedi/drivers/das08_cs.c +++ b/drivers/staging/comedi/drivers/das08_cs.c @@ -1,43 +1,42 @@ /* - comedi/drivers/das08_cs.c - DAS08 driver + * Comedi driver for DAS008 PCMCIA boards + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * Copyright (C) 2001,2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * PCMCIA support code for this driver is adapted from the dummy_cs.c + * driver of the Linux PCMCIA Card Services package. + * + * The initial developer of the original code is David A. Hinds + * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds + * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. + */ - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2000 David A. Schleef <ds@schleef.org> - Copyright (C) 2001,2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - PCMCIA support code for this driver is adapted from the dummy_cs.c - driver of the Linux PCMCIA Card Services package. - - The initial developer of the original code is David A. Hinds - <dahinds@users.sourceforge.net>. Portions created by David A. Hinds - are Copyright (C) 1999 David A. Hinds. All Rights Reserved. -*/ /* -Driver: das08_cs -Description: DAS-08 PCMCIA boards -Author: Warren Jasper, ds, Frank Hess -Devices: [ComputerBoards] PCM-DAS08 (pcm-das08) -Status: works - -This is the PCMCIA-specific support split off from the -das08 driver. - -Options (for pcm-das08): - NONE - -Command support does not exist, but could be added for this board. -*/ + * Driver: das08_cs + * Description: DAS-08 PCMCIA boards + * Author: Warren Jasper, ds, Frank Hess + * Devices: [ComputerBoards] PCM-DAS08 (pcm-das08) + * Status: works + * + * This is the PCMCIA-specific support split off from the + * das08 driver. + * + * Configuration Options: none, uses PCMCIA auto config + * + * Command support does not exist, but could be added for this board. + */ #include <linux/module.h> diff --git a/drivers/staging/comedi/drivers/dt2811.c b/drivers/staging/comedi/drivers/dt2811.c index 8bbd93814340..fcd85475e429 100644 --- a/drivers/staging/comedi/drivers/dt2811.c +++ b/drivers/staging/comedi/drivers/dt2811.c @@ -96,11 +96,11 @@ * 6 6 100 kHz 6 1000000 * 7 12 50 kHz 7 10000000 */ -const unsigned int dt2811_clk_dividers[] = { +static const unsigned int dt2811_clk_dividers[] = { 1, 10, 2, 3, 4, 5, 6, 12 }; -const unsigned int dt2811_clk_multipliers[] = { +static const unsigned int dt2811_clk_multipliers[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 }; diff --git a/drivers/staging/comedi/drivers/dt9812.c b/drivers/staging/comedi/drivers/dt9812.c index 3295bb4ac8c4..7ebca862ecaa 100644 --- a/drivers/staging/comedi/drivers/dt9812.c +++ b/drivers/staging/comedi/drivers/dt9812.c @@ -660,12 +660,12 @@ static int dt9812_find_endpoints(struct comedi_device *dev) case 1: dir = USB_DIR_OUT; devpriv->cmd_wr.addr = ep->bEndpointAddress; - devpriv->cmd_wr.size = le16_to_cpu(ep->wMaxPacketSize); + devpriv->cmd_wr.size = usb_endpoint_maxp(ep); break; case 2: dir = USB_DIR_IN; devpriv->cmd_rd.addr = ep->bEndpointAddress; - devpriv->cmd_rd.size = le16_to_cpu(ep->wMaxPacketSize); + devpriv->cmd_rd.size = usb_endpoint_maxp(ep); break; case 3: /* unused write stream */ diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c index af4b4175af4d..e5b948405fd9 100644 --- a/drivers/staging/comedi/drivers/gsc_hpdi.c +++ b/drivers/staging/comedi/drivers/gsc_hpdi.c @@ -582,7 +582,7 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev) bits |= PLX_DMAMODE_DEMAND; /* enable local burst mode */ bits |= PLX_DMAMODE_BURSTEN; - bits |= PLX_DMAMODE_WIDTH32; + bits |= PLX_DMAMODE_WIDTH_32; writel(bits, plx_iobase + PLX_REG_DMAMODE0); } diff --git a/drivers/staging/comedi/drivers/jr3_pci.c b/drivers/staging/comedi/drivers/jr3_pci.c index 6c4ff023717f..70390de66e0e 100644 --- a/drivers/staging/comedi/drivers/jr3_pci.c +++ b/drivers/staging/comedi/drivers/jr3_pci.c @@ -141,7 +141,7 @@ static void set_transforms(struct jr3_channel __iomem *channel, { int i; - num &= 0x000f; /* Make sure that 0 <= num <= 15 */ + num &= 0x000f; /* Make sure that 0 <= num <= 15 */ for (i = 0; i < 8; i++) { set_u16(&channel->transforms[num].link[i].link_type, transf.link[i].link_type); @@ -323,10 +323,10 @@ static int read_idm_word(const u8 *data, size_t size, int *pos, int value; if (pos && val) { - /* Skip over non hex */ + /* Skip over non hex */ for (; *pos < size && !isxdigit(data[*pos]); (*pos)++) ; - /* Collect value */ + /* Collect value */ *val = 0; for (; *pos < size; (*pos)++) { value = hex_to_bin(data[*pos]); @@ -448,7 +448,8 @@ static int jr3_download_firmware(struct comedi_device *dev, return 0; } -static struct jr3_pci_poll_delay jr3_pci_poll_subdevice(struct comedi_subdevice *s) +static struct jr3_pci_poll_delay +jr3_pci_poll_subdevice(struct comedi_subdevice *s) { struct jr3_pci_subdev_private *spriv = s->private; struct jr3_pci_poll_delay result = poll_delay_min_max(1000, 2000); @@ -733,13 +734,13 @@ static int jr3_pci_auto_attach(struct comedi_device *dev, } } - /* Reset DSP card */ + /* Reset DSP card */ writel(0, &devpriv->iobase->channel[0].reset); ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev, "comedi/jr3pci.idm", jr3_download_firmware, 0); - dev_dbg(dev->class_dev, "Firmare load %d\n", ret); + dev_dbg(dev->class_dev, "Firmware load %d\n", ret); if (ret < 0) return ret; /* @@ -763,7 +764,7 @@ static int jr3_pci_auto_attach(struct comedi_device *dev, data.copyright[i]) >> 8); } - /* Start card timer */ + /* Start card timer */ for (i = 0; i < dev->n_subdevices; i++) { s = &dev->subdevices[i]; spriv = s->private; diff --git a/drivers/staging/comedi/drivers/jr3_pci.h b/drivers/staging/comedi/drivers/jr3_pci.h index 356811defaf4..f10a84fb6c14 100644 --- a/drivers/staging/comedi/drivers/jr3_pci.h +++ b/drivers/staging/comedi/drivers/jr3_pci.h @@ -1,4 +1,5 @@ -/* Helper types to take care of the fact that the DSP card memory +/* + * Helper types to take care of the fact that the DSP card memory * is 16 bits, but aligned on a 32 bit PCI boundary */ @@ -22,7 +23,8 @@ static inline void set_s16(s32 __iomem *p, s16 val) writel(val, p); } -/* The raw data is stored in a format which facilitates rapid +/* + * The raw data is stored in a format which facilitates rapid * processing by the JR3 DSP chip. The raw_channel structure shows the * format for a single channel of data. Each channel takes four, * two-byte words. @@ -47,7 +49,8 @@ struct raw_channel { s32 reserved[2]; }; -/* The force_array structure shows the layout for the decoupled and +/* + * The force_array structure shows the layout for the decoupled and * filtered force data. */ struct force_array { @@ -61,7 +64,8 @@ struct force_array { s32 v2; }; -/* The six_axis_array structure shows the layout for the offsets and +/* + * The six_axis_array structure shows the layout for the offsets and * the full scales. */ struct six_axis_array { @@ -74,7 +78,8 @@ struct six_axis_array { }; /* VECT_BITS */ -/* The vect_bits structure shows the layout for indicating +/* + * The vect_bits structure shows the layout for indicating * which axes to use in computing the vectors. Each bit signifies * selection of a single axis. The V1x axis bit corresponds to a hex * value of 0x0001 and the V2z bit corresponds to a hex value of @@ -100,12 +105,14 @@ enum { }; /* WARNING_BITS */ -/* The warning_bits structure shows the bit pattern for the warning +/* + * The warning_bits structure shows the bit pattern for the warning * word. The bit fields are shown from bit 0 (lsb) to bit 15 (msb). */ -/* XX_NEAR_SET */ -/* The xx_near_sat bits signify that the indicated axis has reached or +/* XX_NEAR_SET */ +/* + * The xx_near_sat bits signify that the indicated axis has reached or * exceeded the near saturation value. */ @@ -118,12 +125,13 @@ enum { mz_near_sat = 0x0020 }; -/* ERROR_BITS */ -/* XX_SAT */ -/* MEMORY_ERROR */ -/* SENSOR_CHANGE */ +/* ERROR_BITS */ +/* XX_SAT */ +/* MEMORY_ERROR */ +/* SENSOR_CHANGE */ -/* The error_bits structure shows the bit pattern for the error word. +/* + * The error_bits structure shows the bit pattern for the error word. * The bit fields are shown from bit 0 (lsb) to bit 15 (msb). The * xx_sat bits signify that the indicated axis has reached or exceeded * the saturation value. The memory_error bit indicates that a problem @@ -134,9 +142,10 @@ enum { * */ -/* SYSTEM_BUSY */ +/* SYSTEM_BUSY */ -/* The system_busy bit indicates that the JR3 DSP is currently busy +/* + * The system_busy bit indicates that the JR3 DSP is currently busy * and is not calculating force data. This occurs when a new * coordinate transformation, or new sensor full scale is set by the * user. A very fast system using the force data for feedback might @@ -146,9 +155,10 @@ enum { * calibration CRC. */ -/* CAL_CRC_BAD */ +/* CAL_CRC_BAD */ -/* The cal_crc_bad bit indicates that the calibration CRC has not +/* + * The cal_crc_bad bit indicates that the calibration CRC has not * calculated to zero. CRC is short for cyclic redundancy code. It is * a method for determining the integrity of messages in data * communication. The calibration data stored inside the sensor is @@ -168,7 +178,8 @@ enum { /* WATCH_DOG */ /* WATCH_DOG2 */ -/* The watch_dog and watch_dog2 bits are sensor, not processor, watch +/* + * The watch_dog and watch_dog2 bits are sensor, not processor, watch * dog bits. Watch_dog indicates that the sensor data line seems to be * acting correctly, while watch_dog2 indicates that sensor data and * clock are being received. It is possible for watch_dog2 to go off @@ -192,9 +203,10 @@ enum error_bits_t { watch_dog = 0x8000 }; -/* THRESH_STRUCT */ +/* THRESH_STRUCT */ -/* This structure shows the layout for a single threshold packet inside of a +/* + * This structure shows the layout for a single threshold packet inside of a * load envelope. Each load envelope can contain several threshold structures. * 1. data_address contains the address of the data for that threshold. This * includes filtered, unfiltered, raw, rate, counters, error and warning data @@ -210,9 +222,10 @@ struct thresh_struct { s32 bit_pattern; }; -/* LE_STRUCT */ +/* LE_STRUCT */ -/* Layout of a load enveloped packet. Four thresholds are showed ... for more +/* + * Layout of a load enveloped packet. Four thresholds are showed ... for more * see manual (pag.25) * 1. latch_bits is a bit pattern that show which bits the user wants to latch. * The latched bits will not be reset once the threshold which set them is @@ -228,8 +241,9 @@ struct le_struct { s32 reserved; }; -/* LINK_TYPES */ -/* Link types is an enumerated value showing the different possible transform +/* LINK_TYPES */ +/* + * Link types is an enumerated value showing the different possible transform * link types. * 0 - end transform packet * 1 - translate along X axis (TX) @@ -252,8 +266,8 @@ enum link_types { neg }; -/* TRANSFORM */ -/* Structure used to describe a transform. */ +/* TRANSFORM */ +/* Structure used to describe a transform. */ struct intern_transform { struct { u32 link_type; @@ -261,23 +275,29 @@ struct intern_transform { } link[8]; }; -/* JR3 force/torque sensor data definition. For more information see sensor - * and hardware manuals. +/* + * JR3 force/torque sensor data definition. For more information see sensor + * and hardware manuals. */ struct jr3_channel { - /* Raw_channels is the area used to store the raw data coming from */ - /* the sensor. */ + /* + * Raw_channels is the area used to store the raw data coming from + * the sensor. + */ struct raw_channel raw_channels[16]; /* offset 0x0000 */ - /* Copyright is a null terminated ASCII string containing the JR3 */ - /* copyright notice. */ + /* + * Copyright is a null terminated ASCII string containing the JR3 + * copyright notice. + */ u32 copyright[0x0018]; /* offset 0x0040 */ s32 reserved1[0x0008]; /* offset 0x0058 */ - /* Shunts contains the sensor shunt readings. Some JR3 sensors have + /* + * Shunts contains the sensor shunt readings. Some JR3 sensors have * the ability to have their gains adjusted. This allows the * hardware full scales to be adjusted to potentially allow * better resolution or dynamic range. For sensors that have @@ -298,25 +318,29 @@ struct jr3_channel { * command (10) set new full scales (pg. 38). */ - struct six_axis_array shunts; /* offset 0x0060 */ - s32 reserved2[2]; /* offset 0x0066 */ + struct six_axis_array shunts; /* offset 0x0060 */ + s32 reserved2[2]; /* offset 0x0066 */ - /* Default_FS contains the full scale that is used if the user does */ - /* not set a full scale. */ + /* + * Default_FS contains the full scale that is used if the user does + * not set a full scale. + */ struct six_axis_array default_FS; /* offset 0x0068 */ - s32 reserved3; /* offset 0x006e */ + s32 reserved3; /* offset 0x006e */ - /* Load_envelope_num is the load envelope number that is currently + /* + * Load_envelope_num is the load envelope number that is currently * in use. This value is set by the user after one of the load * envelopes has been initialized. */ - s32 load_envelope_num; /* offset 0x006f */ + s32 load_envelope_num; /* offset 0x006f */ /* Min_full_scale is the recommend minimum full scale. */ - /* These values in conjunction with max_full_scale (pg. 9) helps + /* + * These values in conjunction with max_full_scale (pg. 9) helps * determine the appropriate value for setting the full scales. The * software allows the user to set the sensor full scale to an * arbitrary value. But setting the full scales has some hazards. If @@ -342,30 +366,35 @@ struct jr3_channel { */ struct six_axis_array min_full_scale; /* offset 0x0070 */ - s32 reserved4; /* offset 0x0076 */ + s32 reserved4; /* offset 0x0076 */ - /* Transform_num is the transform number that is currently in use. + /* + * Transform_num is the transform number that is currently in use. * This value is set by the JR3 DSP after the user has used command * (5) use transform # (pg. 33). */ - s32 transform_num; /* offset 0x0077 */ + s32 transform_num; /* offset 0x0077 */ - /* Max_full_scale is the recommended maximum full scale. See */ - /* min_full_scale (pg. 9) for more details. */ + /* + * Max_full_scale is the recommended maximum full scale. + * See min_full_scale (pg. 9) for more details. + */ struct six_axis_array max_full_scale; /* offset 0x0078 */ - s32 reserved5; /* offset 0x007e */ + s32 reserved5; /* offset 0x007e */ - /* Peak_address is the address of the data which will be monitored + /* + * Peak_address is the address of the data which will be monitored * by the peak routine. This value is set by the user. The peak * routine will monitor any 8 contiguous addresses for peak values. * (ex. to watch filter3 data for peaks, set this value to 0x00a8). */ - s32 peak_address; /* offset 0x007f */ + s32 peak_address; /* offset 0x007f */ - /* Full_scale is the sensor full scales which are currently in use. + /* + * Full_scale is the sensor full scales which are currently in use. * Decoupled and filtered data is scaled so that +/- 16384 is equal * to the full scales. The engineering units used are indicated by * the units value discussed on page 16. The full scales for Fx, Fy, @@ -377,9 +406,10 @@ struct jr3_channel { * axes used for each vector respectively. */ - struct force_array full_scale; /* offset 0x0080 */ + struct force_array full_scale; /* offset 0x0080 */ - /* Offsets contains the sensor offsets. These values are subtracted from + /* + * Offsets contains the sensor offsets. These values are subtracted from * the sensor data to obtain the decoupled data. The offsets are set a * few seconds (< 10) after the calibration data has been received. * They are set so that the output data will be zero. These values @@ -392,23 +422,26 @@ struct jr3_channel { * about Z by 90 degrees, FY would be 5 and all others would be zero. */ - struct six_axis_array offsets; /* offset 0x0088 */ + struct six_axis_array offsets; /* offset 0x0088 */ - /* Offset_num is the number of the offset currently in use. This + /* + * Offset_num is the number of the offset currently in use. This * value is set by the JR3 DSP after the user has executed the use * offset # command (pg. 34). It can vary between 0 and 15. */ - s32 offset_num; /* offset 0x008e */ + s32 offset_num; /* offset 0x008e */ - /* Vect_axes is a bit map showing which of the axes are being used + /* + * Vect_axes is a bit map showing which of the axes are being used * in the vector calculations. This value is set by the JR3 DSP * after the user has executed the set vector axes command (pg. 37). */ - u32 vect_axes; /* offset 0x008f */ + u32 vect_axes; /* offset 0x008f */ - /* Filter0 is the decoupled, unfiltered data from the JR3 sensor. + /* + * Filter0 is the decoupled, unfiltered data from the JR3 sensor. * This data has had the offsets removed. * * These force_arrays hold the filtered data. The decoupled data is @@ -420,23 +453,27 @@ struct jr3_channel { * cutoff at 125 Hz, 31.25 Hz, 7.813 Hz, 1.953 Hz and 0.4883 Hz. */ - struct force_array filter[7]; /* offset 0x0090, - offset 0x0098, - offset 0x00a0, - offset 0x00a8, - offset 0x00b0, - offset 0x00b8 , - offset 0x00c0 */ - - /* Rate_data is the calculated rate data. It is a first derivative + struct force_array filter[7]; /* + * offset 0x0090, + * offset 0x0098, + * offset 0x00a0, + * offset 0x00a8, + * offset 0x00b0, + * offset 0x00b8, + * offset 0x00c0 + */ + + /* + * Rate_data is the calculated rate data. It is a first derivative * calculation. It is calculated at a frequency specified by the * variable rate_divisor (pg. 12). The data on which the rate is * calculated is specified by the variable rate_address (pg. 12). */ - struct force_array rate_data; /* offset 0x00c8 */ + struct force_array rate_data; /* offset 0x00c8 */ - /* Minimum_data & maximum_data are the minimum and maximum (peak) + /* + * Minimum_data & maximum_data are the minimum and maximum (peak) * data values. The JR3 DSP can monitor any 8 contiguous data items * for minimums and maximums at full sensor bandwidth. This area is * only updated at user request. This is done so that the user does @@ -451,7 +488,8 @@ struct jr3_channel { struct force_array minimum_data; /* offset 0x00d0 */ struct force_array maximum_data; /* offset 0x00d8 */ - /* Near_sat_value & sat_value contain the value used to determine if + /* + * Near_sat_value & sat_value contain the value used to determine if * the raw sensor is saturated. Because of decoupling and offset * removal, it is difficult to tell from the processed data if the * sensor is saturated. These values, in conjunction with the error @@ -465,10 +503,11 @@ struct jr3_channel { * sat_value = 32768 - 2^(16 - ADC bits) */ - s32 near_sat_value; /* offset 0x00e0 */ - s32 sat_value; /* offset 0x00e1 */ + s32 near_sat_value; /* offset 0x00e0 */ + s32 sat_value; /* offset 0x00e1 */ - /* Rate_address, rate_divisor & rate_count contain the data used to + /* + * Rate_address, rate_divisor & rate_count contain the data used to * control the calculations of the rates. Rate_address is the * address of the data used for the rate calculation. The JR3 DSP * will calculate rates for any 8 contiguous values (ex. to @@ -485,11 +524,12 @@ struct jr3_channel { * will minimize the time necessary to start the rate calculations. */ - s32 rate_address; /* offset 0x00e2 */ - u32 rate_divisor; /* offset 0x00e3 */ - u32 rate_count; /* offset 0x00e4 */ + s32 rate_address; /* offset 0x00e2 */ + u32 rate_divisor; /* offset 0x00e3 */ + u32 rate_count; /* offset 0x00e4 */ - /* Command_word2 through command_word0 are the locations used to + /* + * Command_word2 through command_word0 are the locations used to * send commands to the JR3 DSP. Their usage varies with the command * and is detailed later in the Command Definitions section (pg. * 29). In general the user places values into various memory @@ -502,11 +542,12 @@ struct jr3_channel { * command_word1). */ - s32 command_word2; /* offset 0x00e5 */ - s32 command_word1; /* offset 0x00e6 */ - s32 command_word0; /* offset 0x00e7 */ + s32 command_word2; /* offset 0x00e5 */ + s32 command_word1; /* offset 0x00e6 */ + s32 command_word0; /* offset 0x00e7 */ - /* Count1 through count6 are unsigned counters which are incremented + /* + * Count1 through count6 are unsigned counters which are incremented * every time the matching filters are calculated. Filter1 is * calculated at the sensor data bandwidth. So this counter would * increment at 8 kHz for a typical sensor. The rest of the counters @@ -518,14 +559,15 @@ struct jr3_channel { * once. */ - u32 count1; /* offset 0x00e8 */ - u32 count2; /* offset 0x00e9 */ - u32 count3; /* offset 0x00ea */ - u32 count4; /* offset 0x00eb */ - u32 count5; /* offset 0x00ec */ - u32 count6; /* offset 0x00ed */ + u32 count1; /* offset 0x00e8 */ + u32 count2; /* offset 0x00e9 */ + u32 count3; /* offset 0x00ea */ + u32 count4; /* offset 0x00eb */ + u32 count5; /* offset 0x00ec */ + u32 count6; /* offset 0x00ed */ - /* Error_count is a running count of data reception errors. If this + /* + * Error_count is a running count of data reception errors. If this * counter is changing rapidly, it probably indicates a bad sensor * cable connection or other hardware problem. In most installations * error_count should not change at all. But it is possible in an @@ -535,75 +577,84 @@ struct jr3_channel { * where this counter counts a bad sample, that sample is ignored. */ - u32 error_count; /* offset 0x00ee */ + u32 error_count; /* offset 0x00ee */ - /* Count_x is a counter which is incremented every time the JR3 DSP + /* + * Count_x is a counter which is incremented every time the JR3 DSP * searches its job queues and finds nothing to do. It indicates the * amount of idle time the JR3 DSP has available. It can also be * used to determine if the JR3 DSP is alive. See the Performance * Issues section on pg. 49 for more details. */ - u32 count_x; /* offset 0x00ef */ + u32 count_x; /* offset 0x00ef */ - /* Warnings & errors contain the warning and error bits + /* + * Warnings & errors contain the warning and error bits * respectively. The format of these two words is discussed on page * 21 under the headings warnings_bits and error_bits. */ - u32 warnings; /* offset 0x00f0 */ - u32 errors; /* offset 0x00f1 */ + u32 warnings; /* offset 0x00f0 */ + u32 errors; /* offset 0x00f1 */ - /* Threshold_bits is a word containing the bits that are set by the + /* + * Threshold_bits is a word containing the bits that are set by the * load envelopes. See load_envelopes (pg. 17) and thresh_struct * (pg. 23) for more details. */ - s32 threshold_bits; /* offset 0x00f2 */ + s32 threshold_bits; /* offset 0x00f2 */ - /* Last_crc is the value that shows the actual calculated CRC. CRC + /* + * Last_crc is the value that shows the actual calculated CRC. CRC * is short for cyclic redundancy code. It should be zero. See the * description for cal_crc_bad (pg. 21) for more information. */ - s32 last_CRC; /* offset 0x00f3 */ + s32 last_CRC; /* offset 0x00f3 */ - /* EEProm_ver_no contains the version number of the sensor EEProm. + /* + * EEProm_ver_no contains the version number of the sensor EEProm. * EEProm version numbers can vary between 0 and 255. * Software_ver_no contains the software version number. Version * 3.02 would be stored as 302. */ - s32 eeprom_ver_no; /* offset 0x00f4 */ - s32 software_ver_no; /* offset 0x00f5 */ + s32 eeprom_ver_no; /* offset 0x00f4 */ + s32 software_ver_no; /* offset 0x00f5 */ - /* Software_day & software_year are the release date of the software + /* + * Software_day & software_year are the release date of the software * the JR3 DSP is currently running. Day is the day of the year, * with January 1 being 1, and December 31, being 365 for non leap * years. */ - s32 software_day; /* offset 0x00f6 */ - s32 software_year; /* offset 0x00f7 */ + s32 software_day; /* offset 0x00f6 */ + s32 software_year; /* offset 0x00f7 */ - /* Serial_no & model_no are the two values which uniquely identify a + /* + * Serial_no & model_no are the two values which uniquely identify a * sensor. This model number does not directly correspond to the JR3 * model number, but it will provide a unique identifier for * different sensor configurations. */ - u32 serial_no; /* offset 0x00f8 */ - u32 model_no; /* offset 0x00f9 */ + u32 serial_no; /* offset 0x00f8 */ + u32 model_no; /* offset 0x00f9 */ - /* Cal_day & cal_year are the sensor calibration date. Day is the + /* + * Cal_day & cal_year are the sensor calibration date. Day is the * day of the year, with January 1 being 1, and December 31, being * 366 for leap years. */ - s32 cal_day; /* offset 0x00fa */ - s32 cal_year; /* offset 0x00fb */ + s32 cal_day; /* offset 0x00fa */ + s32 cal_year; /* offset 0x00fb */ - /* Units is an enumerated read only value defining the engineering + /* + * Units is an enumerated read only value defining the engineering * units used in the sensor full scale. The meanings of particular * values are discussed in the section detailing the force_units * structure on page 22. The engineering units are setto customer @@ -626,20 +677,22 @@ struct jr3_channel { * received. */ - u32 units; /* offset 0x00fc */ - s32 bits; /* offset 0x00fd */ - s32 channels; /* offset 0x00fe */ + u32 units; /* offset 0x00fc */ + s32 bits; /* offset 0x00fd */ + s32 channels; /* offset 0x00fe */ - /* Thickness specifies the overall thickness of the sensor from + /* + * Thickness specifies the overall thickness of the sensor from * flange to flange. The engineering units for this value are * contained in units (pg. 16). The sensor calibration is relative * to the center of the sensor. This value allows easy coordinate * transformation from the center of the sensor to either flange. */ - s32 thickness; /* offset 0x00ff */ + s32 thickness; /* offset 0x00ff */ - /* Load_envelopes is a table containing the load envelope + /* + * Load_envelopes is a table containing the load envelope * descriptions. There are 16 possible load envelope slots in the * table. The slots are on 16 word boundaries and are numbered 0-15. * Each load envelope needs to start at the beginning of a slot but @@ -655,7 +708,8 @@ struct jr3_channel { struct le_struct load_envelopes[0x10]; /* offset 0x0100 */ - /* Transforms is a table containing the transform descriptions. + /* + * Transforms is a table containing the transform descriptions. * There are 16 possible transform slots in the table. The slots are * on 16 word boundaries and are numbered 0-15. Each transform needs * to start at the beginning of a slot but need not be fully diff --git a/drivers/staging/comedi/drivers/ni_670x.c b/drivers/staging/comedi/drivers/ni_670x.c index 3e72718801a9..74911dbb2561 100644 --- a/drivers/staging/comedi/drivers/ni_670x.c +++ b/drivers/staging/comedi/drivers/ni_670x.c @@ -1,40 +1,34 @@ /* - comedi/drivers/ni_670x.c - Hardware driver for NI 670x devices - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ -/* -Driver: ni_670x -Description: National Instruments 670x -Author: Bart Joris <bjoris@advalvas.be> -Updated: Wed, 11 Dec 2002 18:25:35 -0800 -Devices: [National Instruments] PCI-6703 (ni_670x), PCI-6704 -Status: unknown - -Commands are not supported. -*/ + * Comedi driver for NI 670x devices + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* - Bart Joris <bjoris@advalvas.be> Last updated on 20/08/2001 - - Manuals: - - 322110a.pdf PCI/PXI-6704 User Manual - 322110b.pdf PCI/PXI-6703/6704 User Manual - -*/ + * Driver: ni_670x + * Description: National Instruments 670x + * Author: Bart Joris <bjoris@advalvas.be> + * Updated: Wed, 11 Dec 2002 18:25:35 -0800 + * Devices: [National Instruments] PCI-6703 (ni_670x), PCI-6704 + * Status: unknown + * + * Commands are not supported. + * + * Manuals: + * 322110a.pdf PCI/PXI-6704 User Manual + * 322110b.pdf PCI/PXI-6703/6704 User Manual + */ #include <linux/module.h> #include <linux/interrupt.h> diff --git a/drivers/staging/comedi/drivers/ni_at_a2150.c b/drivers/staging/comedi/drivers/ni_at_a2150.c index 9b444f8c4e33..5a4dcc6e61d8 100644 --- a/drivers/staging/comedi/drivers/ni_at_a2150.c +++ b/drivers/staging/comedi/drivers/ni_at_a2150.c @@ -1,62 +1,47 @@ /* - comedi/drivers/ni_at_a2150.c - Driver for National Instruments AT-A2150 boards - Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ -/* -Driver: ni_at_a2150 -Description: National Instruments AT-A2150 -Author: Frank Mori Hess -Status: works -Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s) - -If you want to ac couple the board's inputs, use AREF_OTHER. - -Configuration options: - [0] - I/O port base address - [1] - IRQ (optional, required for timed conversions) - [2] - DMA (optional, required for timed conversions) + * Comedi driver for National Instruments AT-A2150 boards + * Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ -*/ /* -Yet another driver for obsolete hardware brought to you by Frank Hess. -Testing and debugging help provided by Dave Andruczyk. - -This driver supports the boards: - -AT-A2150C -AT-A2150S - -The only difference is their master clock frequencies. - -Options: - [0] - base io address - [1] - irq - [2] - dma channel - -References (from ftp://ftp.natinst.com/support/manuals): - - 320360.pdf AT-A2150 User Manual - -TODO: - -analog level triggering -TRIG_WAKE_EOS - -*/ + * Driver: ni_at_a2150 + * Description: National Instruments AT-A2150 + * Author: Frank Mori Hess + * Status: works + * Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s) + * + * Configuration options: + * [0] - I/O port base address + * [1] - IRQ (optional, required for timed conversions) + * [2] - DMA (optional, required for timed conversions) + * + * Yet another driver for obsolete hardware brought to you by Frank Hess. + * Testing and debugging help provided by Dave Andruczyk. + * + * If you want to ac couple the board's inputs, use AREF_OTHER. + * + * The only difference in the boards is their master clock frequencies. + * + * References (from ftp://ftp.natinst.com/support/manuals): + * 320360.pdf AT-A2150 User Manual + * + * TODO: + * - analog level triggering + * - TRIG_WAKE_EOS + */ #include <linux/module.h> #include <linux/delay.h> @@ -73,48 +58,52 @@ TRIG_WAKE_EOS /* Registers and bits */ #define CONFIG_REG 0x0 -#define CHANNEL_BITS(x) ((x) & 0x7) +#define CHANNEL_BITS(x) ((x) & 0x7) #define CHANNEL_MASK 0x7 -#define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3) -#define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5) +#define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3) +#define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5) #define CLOCK_MASK (0xf << 3) -#define ENABLE0_BIT 0x80 /* enable (don't internally ground) channels 0 and 1 */ -#define ENABLE1_BIT 0x100 /* enable (don't internally ground) channels 2 and 3 */ -#define AC0_BIT 0x200 /* ac couple channels 0,1 */ -#define AC1_BIT 0x400 /* ac couple channels 2,3 */ -#define APD_BIT 0x800 /* analog power down */ -#define DPD_BIT 0x1000 /* digital power down */ -#define TRIGGER_REG 0x2 /* trigger config register */ -#define POST_TRIGGER_BITS 0x2 -#define DELAY_TRIGGER_BITS 0x3 -#define HW_TRIG_EN 0x10 /* enable hardware trigger */ -#define FIFO_START_REG 0x6 /* software start aquistion trigger */ -#define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */ -#define FIFO_DATA_REG 0xa /* read data */ -#define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */ -#define STATUS_REG 0x12 /* read only */ -#define FNE_BIT 0x1 /* fifo not empty */ -#define OVFL_BIT 0x8 /* fifo overflow */ -#define EDAQ_BIT 0x10 /* end of acquisition interrupt */ -#define DCAL_BIT 0x20 /* offset calibration in progress */ -#define INTR_BIT 0x40 /* interrupt has occurred */ -#define DMA_TC_BIT 0x80 /* dma terminal count interrupt has occurred */ -#define ID_BITS(x) (((x) >> 8) & 0x3) -#define IRQ_DMA_CNTRL_REG 0x12 /* write only */ -#define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */ -#define DMA_EN_BIT 0x8 /* enables dma */ -#define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */ -#define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */ -#define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */ -#define DMA_INTR_EN_BIT 0x800 /* enable interrupt on dma terminal count */ -#define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */ +/* enable (don't internally ground) channels 0 and 1 */ +#define ENABLE0_BIT 0x80 +/* enable (don't internally ground) channels 2 and 3 */ +#define ENABLE1_BIT 0x100 +#define AC0_BIT 0x200 /* ac couple channels 0,1 */ +#define AC1_BIT 0x400 /* ac couple channels 2,3 */ +#define APD_BIT 0x800 /* analog power down */ +#define DPD_BIT 0x1000 /* digital power down */ +#define TRIGGER_REG 0x2 /* trigger config register */ +#define POST_TRIGGER_BITS 0x2 +#define DELAY_TRIGGER_BITS 0x3 +#define HW_TRIG_EN 0x10 /* enable hardware trigger */ +#define FIFO_START_REG 0x6 /* software start aquistion trigger */ +#define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */ +#define FIFO_DATA_REG 0xa /* read data */ +#define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */ +#define STATUS_REG 0x12 /* read only */ +#define FNE_BIT 0x1 /* fifo not empty */ +#define OVFL_BIT 0x8 /* fifo overflow */ +#define EDAQ_BIT 0x10 /* end of acquisition interrupt */ +#define DCAL_BIT 0x20 /* offset calibration in progress */ +#define INTR_BIT 0x40 /* interrupt has occurred */ +/* dma terminal count interrupt has occurred */ +#define DMA_TC_BIT 0x80 +#define ID_BITS(x) (((x) >> 8) & 0x3) +#define IRQ_DMA_CNTRL_REG 0x12 /* write only */ +#define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */ +#define DMA_EN_BIT 0x8 /* enables dma */ +#define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */ +#define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */ +#define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */ +/* enable interrupt on dma terminal count */ +#define DMA_INTR_EN_BIT 0x800 +#define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */ #define I8253_BASE_REG 0x14 struct a2150_board { const char *name; - int clock[4]; /* master clock periods, in nanoseconds */ - int num_clocks; /* number of available master clock speeds */ - int ai_speed; /* maximum conversion rate in nanoseconds */ + int clock[4]; /* master clock periods, in nanoseconds */ + int num_clocks; /* number of available master clock speeds */ + int ai_speed; /* maximum conversion rate in nanoseconds */ }; /* analog input range */ @@ -144,8 +133,8 @@ static const struct a2150_board a2150_boards[] = { struct a2150_private { struct comedi_isadma *dma; unsigned int count; /* number of data points left to be taken */ - int irq_dma_bits; /* irq/dma register bits */ - int config_bits; /* config register bits */ + int irq_dma_bits; /* irq/dma register bits */ + int config_bits; /* config register bits */ }; /* interrupt service routine */ @@ -189,13 +178,13 @@ static irqreturn_t a2150_interrupt(int irq, void *d) */ residue = comedi_isadma_disable(desc->chan); - /* figure out how many points to read */ + /* figure out how many points to read */ max_points = comedi_bytes_to_samples(s, desc->size); num_points = max_points - comedi_bytes_to_samples(s, residue); if (devpriv->count < num_points && cmd->stop_src == TRIG_COUNT) num_points = devpriv->count; - /* figure out how many points will be stored next time */ + /* figure out how many points will be stored next time */ leftover = 0; if (cmd->stop_src == TRIG_NONE) { leftover = comedi_bytes_to_samples(s, desc->size); @@ -204,7 +193,8 @@ static irqreturn_t a2150_interrupt(int irq, void *d) if (leftover > max_points) leftover = max_points; } - /* there should only be a residue if collection was stopped by having + /* + * There should only be a residue if collection was stopped by having * the stop_src set to an external trigger, in which case there * will be no more data */ @@ -214,7 +204,7 @@ static irqreturn_t a2150_interrupt(int irq, void *d) for (i = 0; i < num_points; i++) { /* write data point to comedi buffer */ dpnt = buf[i]; - /* convert from 2's complement to unsigned coding */ + /* convert from 2's complement to unsigned coding */ dpnt ^= 0x8000; comedi_buf_write_samples(s, &dpnt, 1); if (cmd->stop_src == TRIG_COUNT) { @@ -244,14 +234,14 @@ static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s) struct comedi_isadma *dma = devpriv->dma; struct comedi_isadma_desc *desc = &dma->desc[0]; - /* disable dma on card */ + /* disable dma on card */ devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT; outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); - /* disable computer's dma */ + /* disable computer's dma */ comedi_isadma_disable(desc->chan); - /* clear fifo and reset triggering circuitry */ + /* clear fifo and reset triggering circuitry */ outw(0, dev->iobase + FIFO_RESET_REG); return 0; @@ -270,7 +260,7 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index; int i, j; - /* initialize greatest lower and least upper bounds */ + /* initialize greatest lower and least upper bounds */ lub_divisor_shift = 3; lub_index = 0; lub = board->clock[lub_index] * (1 << lub_divisor_shift); @@ -278,19 +268,19 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, glb_index = board->num_clocks - 1; glb = board->clock[glb_index] * (1 << glb_divisor_shift); - /* make sure period is in available range */ + /* make sure period is in available range */ if (*period < glb) *period = glb; if (*period > lub) *period = lub; - /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */ + /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */ for (i = 0; i < 4; i++) { - /* there are a maximum of 4 master clocks */ + /* there are a maximum of 4 master clocks */ for (j = 0; j < board->num_clocks; j++) { - /* temp is the period in nanosec we are evaluating */ + /* temp is the period in nanosec we are evaluating */ temp = board->clock[j] * (1 << i); - /* if it is the best match yet */ + /* if it is the best match yet */ if (temp < lub && temp >= *period) { lub_divisor_shift = i; lub_index = j; @@ -306,7 +296,7 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, switch (flags & CMDF_ROUND_MASK) { case CMDF_ROUND_NEAREST: default: - /* if least upper bound is better approximation */ + /* if least upper bound is better approximation */ if (lub - *period < *period - glb) *period = lub; else @@ -320,7 +310,7 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, break; } - /* set clock bits for config register appropriately */ + /* set clock bits for config register appropriately */ devpriv->config_bits &= ~CLOCK_MASK; if (*period == lub) { devpriv->config_bits |= @@ -495,7 +485,7 @@ static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) "dma incompatible with hard real-time interrupt (CMDF_PRIORITY), aborting\n"); return -1; } - /* clear fifo and reset triggering circuitry */ + /* clear fifo and reset triggering circuitry */ outw(0, dev->iobase + FIFO_RESET_REG); /* setup chanlist */ @@ -503,7 +493,7 @@ static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) cmd->chanlist_len) < 0) return -1; - /* setup ac/dc coupling */ + /* setup ac/dc coupling */ if (CR_AREF(cmd->chanlist[0]) == AREF_OTHER) devpriv->config_bits |= AC0_BIT; else @@ -513,18 +503,18 @@ static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) else devpriv->config_bits &= ~AC1_BIT; - /* setup timing */ + /* setup timing */ a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags); - /* send timing, channel, config bits */ + /* send timing, channel, config bits */ outw(devpriv->config_bits, dev->iobase + CONFIG_REG); - /* initialize number of samples remaining */ + /* initialize number of samples remaining */ devpriv->count = cmd->stop_arg * cmd->chanlist_len; comedi_isadma_disable(desc->chan); - /* set size of transfer to fill in 1/3 second */ + /* set size of transfer to fill in 1/3 second */ #define ONE_THIRD_SECOND 333333333 desc->size = comedi_bytes_per_sample(s) * cmd->chanlist_len * ONE_THIRD_SECOND / cmd->scan_begin_arg; @@ -536,40 +526,45 @@ static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) comedi_isadma_program(desc); - /* clear dma interrupt before enabling it, to try and get rid of that - * one spurious interrupt that has been happening */ + /* + * Clear dma interrupt before enabling it, to try and get rid of + * that one spurious interrupt that has been happening. + */ outw(0x00, dev->iobase + DMA_TC_CLEAR_REG); - /* enable dma on card */ + /* enable dma on card */ devpriv->irq_dma_bits |= DMA_INTR_EN_BIT | DMA_EN_BIT; outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); - /* may need to wait 72 sampling periods if timing was changed */ + /* may need to wait 72 sampling periods if timing was changed */ comedi_8254_load(dev->pacer, 2, 72, I8254_MODE0 | I8254_BINARY); - /* setup start triggering */ + /* setup start triggering */ trigger_bits = 0; - /* decide if we need to wait 72 periods for valid data */ + /* decide if we need to wait 72 periods for valid data */ if (cmd->start_src == TRIG_NOW && (old_config_bits & CLOCK_MASK) != (devpriv->config_bits & CLOCK_MASK)) { - /* set trigger source to delay trigger */ + /* set trigger source to delay trigger */ trigger_bits |= DELAY_TRIGGER_BITS; } else { - /* otherwise no delay */ + /* otherwise no delay */ trigger_bits |= POST_TRIGGER_BITS; } - /* enable external hardware trigger */ + /* enable external hardware trigger */ if (cmd->start_src == TRIG_EXT) { trigger_bits |= HW_TRIG_EN; } else if (cmd->start_src == TRIG_OTHER) { - /* XXX add support for level/slope start trigger using TRIG_OTHER */ + /* + * XXX add support for level/slope start trigger + * using TRIG_OTHER + */ dev_err(dev->class_dev, "you shouldn't see this?\n"); } - /* send trigger config bits */ + /* send trigger config bits */ outw(trigger_bits, dev->iobase + TRIGGER_REG); - /* start acquisition for soft trigger */ + /* start acquisition for soft trigger */ if (cmd->start_src == TRIG_NOW) outw(0, dev->iobase + FIFO_START_REG); @@ -596,28 +591,28 @@ static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int n; int ret; - /* clear fifo and reset triggering circuitry */ + /* clear fifo and reset triggering circuitry */ outw(0, dev->iobase + FIFO_RESET_REG); /* setup chanlist */ if (a2150_set_chanlist(dev, CR_CHAN(insn->chanspec), 1) < 0) return -1; - /* set dc coupling */ + /* set dc coupling */ devpriv->config_bits &= ~AC0_BIT; devpriv->config_bits &= ~AC1_BIT; - /* send timing, channel, config bits */ + /* send timing, channel, config bits */ outw(devpriv->config_bits, dev->iobase + CONFIG_REG); - /* disable dma on card */ + /* disable dma on card */ devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT; outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); - /* setup start triggering */ + /* setup start triggering */ outw(0, dev->iobase + TRIGGER_REG); - /* start acquisition for soft trigger */ + /* start acquisition for soft trigger */ outw(0, dev->iobase + FIFO_START_REG); /* @@ -632,7 +627,7 @@ static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, inw(dev->iobase + FIFO_DATA_REG); } - /* read data */ + /* read data */ for (n = 0; n < insn->n; n++) { ret = comedi_timeout(dev, s, insn, a2150_ai_eoc, 0); if (ret) @@ -642,7 +637,7 @@ static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, data[n] ^= 0x8000; } - /* clear fifo and reset triggering circuitry */ + /* clear fifo and reset triggering circuitry */ outw(0, dev->iobase + FIFO_RESET_REG); return n; @@ -749,16 +744,16 @@ static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->cancel = a2150_cancel; } - /* set card's irq and dma levels */ + /* set card's irq and dma levels */ outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); - /* reset and sync adc clock circuitry */ + /* reset and sync adc clock circuitry */ outw_p(DPD_BIT | APD_BIT, dev->iobase + CONFIG_REG); outw_p(DPD_BIT, dev->iobase + CONFIG_REG); - /* initialize configuration register */ + /* initialize configuration register */ devpriv->config_bits = 0; outw(devpriv->config_bits, dev->iobase + CONFIG_REG); - /* wait until offset calibration is done, then enable analog inputs */ + /* wait until offset calibration is done, then enable analog inputs */ for (i = 0; i < timeout; i++) { if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0) break; diff --git a/drivers/staging/comedi/drivers/ni_atmio.c b/drivers/staging/comedi/drivers/ni_atmio.c index 95435b81aa55..ffcf7afce684 100644 --- a/drivers/staging/comedi/drivers/ni_atmio.c +++ b/drivers/staging/comedi/drivers/ni_atmio.c @@ -1,93 +1,84 @@ /* - comedi/drivers/ni_atmio.c - Hardware driver for NI AT-MIO E series cards - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ -/* -Driver: ni_atmio -Description: National Instruments AT-MIO-E series -Author: ds -Devices: [National Instruments] AT-MIO-16E-1 (ni_atmio), - AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16DE-10, AT-MIO-64E-3, - AT-MIO-16XE-50, AT-MIO-16XE-10, AT-AI-16XE-10 -Status: works -Updated: Thu May 1 20:03:02 CDT 2003 - -The driver has 2.6 kernel isapnp support, and -will automatically probe for a supported board if the -I/O base is left unspecified with comedi_config. -However, many of -the isapnp id numbers are unknown. If your board is not -recognized, please send the output of 'cat /proc/isapnp' -(you may need to modprobe the isa-pnp module for -/proc/isapnp to exist) so the -id numbers for your board can be added to the driver. - -Otherwise, you can use the isapnptools package to configure -your board. Use isapnp to -configure the I/O base and IRQ for the board, and then pass -the same values as -parameters in comedi_config. A sample isapnp.conf file is included -in the etc/ directory of Comedilib. - -Comedilib includes a utility to autocalibrate these boards. The -boards seem to boot into a state where the all calibration DACs -are at one extreme of their range, thus the default calibration -is terrible. Calibration at boot is strongly encouraged. - -To use the extended digital I/O on some of the boards, enable the -8255 driver when configuring the Comedi source tree. - -External triggering is supported for some events. The channel index -(scan_begin_arg, etc.) maps to PFI0 - PFI9. - -Some of the more esoteric triggering possibilities of these boards -are not supported. -*/ -/* - The real guts of the driver is in ni_mio_common.c, which is included - both here and in ni_pcimio.c - - Interrupt support added by Truxton Fulton <trux@truxton.com> - - References for specifications: - - 340747b.pdf Register Level Programmer Manual (obsolete) - 340747c.pdf Register Level Programmer Manual (new) - DAQ-STC reference manual - - Other possibly relevant info: - - 320517c.pdf User manual (obsolete) - 320517f.pdf User manual (new) - 320889a.pdf delete - 320906c.pdf maximum signal ratings - 321066a.pdf about 16x - 321791a.pdf discontinuation of at-mio-16e-10 rev. c - 321808a.pdf about at-mio-16e-10 rev P - 321837a.pdf discontinuation of at-mio-16de-10 rev d - 321838a.pdf about at-mio-16de-10 rev N - - ISSUES: - - need to deal with external reference for DAC, and other DAC - properties in board properties + * Comedi driver for NI AT-MIO E series cards + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - deal with at-mio-16de-10 revision D to N changes, etc. +/* + * Driver: ni_atmio + * Description: National Instruments AT-MIO-E series + * Author: ds + * Devices: [National Instruments] AT-MIO-16E-1 (ni_atmio), + * AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16DE-10, AT-MIO-64E-3, + * AT-MIO-16XE-50, AT-MIO-16XE-10, AT-AI-16XE-10 + * Status: works + * Updated: Thu May 1 20:03:02 CDT 2003 + * + * The driver has 2.6 kernel isapnp support, and will automatically probe for + * a supported board if the I/O base is left unspecified with comedi_config. + * However, many of the isapnp id numbers are unknown. If your board is not + * recognized, please send the output of 'cat /proc/isapnp' (you may need to + * modprobe the isa-pnp module for /proc/isapnp to exist) so the id numbers + * for your board can be added to the driver. + * + * Otherwise, you can use the isapnptools package to configure your board. + * Use isapnp to configure the I/O base and IRQ for the board, and then pass + * the same values as parameters in comedi_config. A sample isapnp.conf file + * is included in the etc/ directory of Comedilib. + * + * Comedilib includes a utility to autocalibrate these boards. The boards + * seem to boot into a state where the all calibration DACs are at one + * extreme of their range, thus the default calibration is terrible. + * Calibration at boot is strongly encouraged. + * + * To use the extended digital I/O on some of the boards, enable the + * 8255 driver when configuring the Comedi source tree. + * + * External triggering is supported for some events. The channel index + * (scan_begin_arg, etc.) maps to PFI0 - PFI9. + * + * Some of the more esoteric triggering possibilities of these boards are + * not supported. + */ -*/ +/* + * The real guts of the driver is in ni_mio_common.c, which is included + * both here and in ni_pcimio.c + * + * Interrupt support added by Truxton Fulton <trux@truxton.com> + * + * References for specifications: + * 340747b.pdf Register Level Programmer Manual (obsolete) + * 340747c.pdf Register Level Programmer Manual (new) + * DAQ-STC reference manual + * + * Other possibly relevant info: + * 320517c.pdf User manual (obsolete) + * 320517f.pdf User manual (new) + * 320889a.pdf delete + * 320906c.pdf maximum signal ratings + * 321066a.pdf about 16x + * 321791a.pdf discontinuation of at-mio-16e-10 rev. c + * 321808a.pdf about at-mio-16e-10 rev P + * 321837a.pdf discontinuation of at-mio-16de-10 rev d + * 321838a.pdf about at-mio-16de-10 rev N + * + * ISSUES: + * - need to deal with external reference for DAC, and other DAC + * properties in board properties + * - deal with at-mio-16de-10 revision D to N changes, etc. + */ #include <linux/module.h> #include <linux/interrupt.h> @@ -98,10 +89,7 @@ are not supported. #include "ni_stc.h" #include "8255.h" -/* - * AT specific setup - */ - +/* AT specific setup */ static const struct ni_board_struct ni_boards[] = { { .name = "at-mio-16e-1", @@ -215,7 +203,7 @@ static const struct ni_board_struct ni_boards[] = { .n_adchan = 16, .ai_maxdata = 0xffff, .ai_fifo_depth = 512, - .alwaysdither = 1, /* unknown */ + .alwaysdither = 1, /* unknown */ .gainlkup = ai_gain_14, .ai_speed = 10000, .caldac = { dac8800, dac8043, ad8522 }, @@ -287,10 +275,10 @@ static const struct ni_board_struct *ni_atmio_probe(struct comedi_device *dev) } if (device_id == 255) dev_err(dev->class_dev, "can't find board\n"); - else if (device_id == 0) + else if (device_id == 0) dev_err(dev->class_dev, "EEPROM read error (?) or device not found\n"); - else + else dev_err(dev->class_dev, "unknown device ID %d -- contact author\n", device_id); diff --git a/drivers/staging/comedi/drivers/ni_atmio16d.c b/drivers/staging/comedi/drivers/ni_atmio16d.c index c3eb54622bc3..fb59b0ffbba6 100644 --- a/drivers/staging/comedi/drivers/ni_atmio16d.c +++ b/drivers/staging/comedi/drivers/ni_atmio16d.c @@ -1,25 +1,41 @@ /* - comedi/drivers/ni_atmio16d.c - Hardware driver for National Instruments AT-MIO16D board - Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + * Comedi driver for National Instruments AT-MIO16D board + * Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ + /* -Driver: ni_atmio16d -Description: National Instruments AT-MIO-16D -Author: Chris R. Baugher <baugher@enteract.com> -Status: unknown -Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d) -*/ + * Driver: ni_atmio16d + * Description: National Instruments AT-MIO-16D + * Author: Chris R. Baugher <baugher@enteract.com> + * Status: unknown + * Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d) + * + * Configuration options: + * [0] - I/O port + * [1] - MIO irq (0 == no irq; or 3,4,5,6,7,9,10,11,12,14,15) + * [2] - DIO irq (0 == no irq; or 3,4,5,6,7,9) + * [3] - DMA1 channel (0 == no DMA; or 5,6,7) + * [4] - DMA2 channel (0 == no DMA; or 5,6,7) + * [5] - a/d mux (0=differential; 1=single) + * [6] - a/d range (0=bipolar10; 1=bipolar5; 2=unipolar10) + * [7] - dac0 range (0=bipolar; 1=unipolar) + * [8] - dac0 reference (0=internal; 1=external) + * [9] - dac0 coding (0=2's comp; 1=straight binary) + * [10] - dac1 range (same as dac0 options) + * [11] - dac1 reference (same as dac0 options) + * [12] - dac1 coding (same as dac0 options) + */ + /* * I must give credit here to Michal Dobes <dobes@tesnet.cz> who * wrote the driver for Advantec's pcl812 boards. I used the interrupt @@ -295,8 +311,10 @@ static int atmio16d_ai_cmd(struct comedi_device *dev, unsigned int sample_count, tmp, chan, gain; int i; - /* This is slowly becoming a working command interface. * - * It is still uber-experimental */ + /* + * This is slowly becoming a working command interface. + * It is still uber-experimental + */ reset_counters(dev); @@ -322,9 +340,10 @@ static int atmio16d_ai_cmd(struct comedi_device *dev, outw(tmp, dev->iobase + MUX_GAIN_REG); } - /* Now program the sample interval timer */ - /* Figure out which clock to use then get an - * appropriate timer value */ + /* + * Now program the sample interval timer. + * Figure out which clock to use then get an appropriate timer value. + */ if (cmd->convert_arg < 65536000) { base_clock = CLOCK_1_MHZ; timer = cmd->convert_arg / 1000; @@ -386,9 +405,10 @@ static int atmio16d_ai_cmd(struct comedi_device *dev, outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); } - /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */ - /* Figure out which clock to use then get an - * appropriate timer value */ + /* + * Program the scan interval timer ONLY IF SCANNING IS ENABLED. + * Figure out which clock to use then get an appropriate timer value. + */ if (cmd->chanlist_len > 1) { if (cmd->scan_begin_arg < 65536000) { base_clock = CLOCK_1_MHZ; @@ -566,38 +586,6 @@ static int atmio16d_dio_insn_config(struct comedi_device *dev, return insn->n; } -/* - options[0] - I/O port - options[1] - MIO irq - 0 == no irq - N == irq N {3,4,5,6,7,9,10,11,12,14,15} - options[2] - DIO irq - 0 == no irq - N == irq N {3,4,5,6,7,9} - options[3] - DMA1 channel - 0 == no DMA - N == DMA N {5,6,7} - options[4] - DMA2 channel - 0 == no DMA - N == DMA N {5,6,7} - - options[5] - a/d mux - 0=differential, 1=single - options[6] - a/d range - 0=bipolar10, 1=bipolar5, 2=unipolar10 - - options[7] - dac0 range - 0=bipolar, 1=unipolar - options[8] - dac0 reference - 0=internal, 1=external - options[9] - dac0 coding - 0=2's comp, 1=straight binary - - options[10] - dac1 range - options[11] - dac1 reference - options[12] - dac1 coding - */ - static int atmio16d_attach(struct comedi_device *dev, struct comedi_devconfig *it) { diff --git a/drivers/staging/comedi/drivers/ni_daq_dio24.c b/drivers/staging/comedi/drivers/ni_daq_dio24.c index d9de83ab0267..733d3fbafa4d 100644 --- a/drivers/staging/comedi/drivers/ni_daq_dio24.c +++ b/drivers/staging/comedi/drivers/ni_daq_dio24.c @@ -1,35 +1,35 @@ /* - comedi/drivers/ni_daq_dio24.c - Driver for National Instruments PCMCIA DAQ-Card DIO-24 - Copyright (C) 2002 Daniel Vecino Castel <dvecino@able.es> + * Comedi driver for National Instruments PCMCIA DAQ-Card DIO-24 + * Copyright (C) 2002 Daniel Vecino Castel <dvecino@able.es> + * + * PCMCIA crap at end of file is adapted from dummy_cs.c 1.31 + * 2001/08/24 12:13:13 from the pcmcia package. + * The initial developer of the pcmcia dummy_cs.c code is David A. Hinds + * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds + * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - PCMCIA crap at end of file is adapted from dummy_cs.c 1.31 - 2001/08/24 12:13:13 from the pcmcia package. - The initial developer of the pcmcia dummy_cs.c code is David A. Hinds - <dahinds@users.sourceforge.net>. Portions created by David A. Hinds - are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ /* -Driver: ni_daq_dio24 -Description: National Instruments PCMCIA DAQ-Card DIO-24 -Author: Daniel Vecino Castel <dvecino@able.es> -Devices: [National Instruments] PCMCIA DAQ-Card DIO-24 (ni_daq_dio24) -Status: ? -Updated: Thu, 07 Nov 2002 21:53:06 -0800 - -This is just a wrapper around the 8255.o driver to properly handle -the PCMCIA interface. -*/ + * Driver: ni_daq_dio24 + * Description: National Instruments PCMCIA DAQ-Card DIO-24 + * Author: Daniel Vecino Castel <dvecino@able.es> + * Devices: [National Instruments] PCMCIA DAQ-Card DIO-24 (ni_daq_dio24) + * Status: ? + * Updated: Thu, 07 Nov 2002 21:53:06 -0800 + * + * This is just a wrapper around the 8255.o driver to properly handle + * the PCMCIA interface. + */ #include <linux/module.h> #include "../comedi_pcmcia.h" diff --git a/drivers/staging/comedi/drivers/ni_mio_cs.c b/drivers/staging/comedi/drivers/ni_mio_cs.c index e3d821bf2d6a..21f823179356 100644 --- a/drivers/staging/comedi/drivers/ni_mio_cs.c +++ b/drivers/staging/comedi/drivers/ni_mio_cs.c @@ -1,40 +1,39 @@ /* - comedi/drivers/ni_mio_cs.c - Hardware driver for NI PCMCIA MIO E series cards - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1997-2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ -/* -Driver: ni_mio_cs -Description: National Instruments DAQCard E series -Author: ds -Status: works -Devices: [National Instruments] DAQCard-AI-16XE-50 (ni_mio_cs), - DAQCard-AI-16E-4, DAQCard-6062E, DAQCard-6024E, DAQCard-6036E -Updated: Thu Oct 23 19:43:17 CDT 2003 - -See the notes in the ni_atmio.o driver. -*/ -/* - The real guts of the driver is in ni_mio_common.c, which is - included by all the E series drivers. - - References for specifications: + * Comedi driver for NI PCMCIA MIO E series cards + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1997-2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - 341080a.pdf DAQCard E Series Register Level Programmer Manual +/* + * Driver: ni_mio_cs + * Description: National Instruments DAQCard E series + * Author: ds + * Status: works + * Devices: [National Instruments] DAQCard-AI-16XE-50 (ni_mio_cs), + * DAQCard-AI-16E-4, DAQCard-6062E, DAQCard-6024E, DAQCard-6036E + * Updated: Thu Oct 23 19:43:17 CDT 2003 + * + * See the notes in the ni_atmio.o driver. + */ -*/ +/* + * The real guts of the driver is in ni_mio_common.c, which is + * included by all the E series drivers. + * + * References for specifications: + * 341080a.pdf DAQCard E Series Register Level Programmer Manual + */ #include <linux/module.h> #include <linux/delay.h> diff --git a/drivers/staging/comedi/drivers/ni_pcidio.c b/drivers/staging/comedi/drivers/ni_pcidio.c index 35ef1925703f..daeb4ad7a75f 100644 --- a/drivers/staging/comedi/drivers/ni_pcidio.c +++ b/drivers/staging/comedi/drivers/ni_pcidio.c @@ -1,50 +1,49 @@ /* - comedi/drivers/ni_pcidio.c - driver for National Instruments PCI-DIO-32HS - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Comedi driver for National Instruments PCI-DIO-32HS + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + /* -Driver: ni_pcidio -Description: National Instruments PCI-DIO32HS, PCI-6533 -Author: ds -Status: works -Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio) - [National Instruments] PXI-6533, PCI-6533 (pxi-6533) - [National Instruments] PCI-6534 (pci-6534) -Updated: Mon, 09 Jan 2012 14:27:23 +0000 - -The DIO32HS board appears as one subdevice, with 32 channels. -Each channel is individually I/O configurable. The channel order -is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only -supports simple digital I/O; no handshaking is supported. - -DMA mostly works for the PCI-DIO32HS, but only in timed input mode. - -The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting -scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting -scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the -trailing edge. - -This driver could be easily modified to support AT-MIO32HS and -AT-MIO96. - -The PCI-6534 requires a firmware upload after power-up to work, the -firmware data and instructions for loading it with comedi_config -it are contained in the -comedi_nonfree_firmware tarball available from http://www.comedi.org -*/ + * Driver: ni_pcidio + * Description: National Instruments PCI-DIO32HS, PCI-6533 + * Author: ds + * Status: works + * Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio) + * [National Instruments] PXI-6533, PCI-6533 (pxi-6533) + * [National Instruments] PCI-6534 (pci-6534) + * Updated: Mon, 09 Jan 2012 14:27:23 +0000 + * + * The DIO32HS board appears as one subdevice, with 32 channels. Each + * channel is individually I/O configurable. The channel order is 0=A0, + * 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple + * digital I/O; no handshaking is supported. + * + * DMA mostly works for the PCI-DIO32HS, but only in timed input mode. + * + * The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting + * scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting + * scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the + * trailing edge. + * + * This driver could be easily modified to support AT-MIO32HS and AT-MIO96. + * + * The PCI-6534 requires a firmware upload after power-up to work, the + * firmware data and instructions for loading it with comedi_config + * it are contained in the comedi_nonfree_firmware tarball available from + * http://www.comedi.org + */ #define USE_DMA @@ -61,36 +60,36 @@ comedi_nonfree_firmware tarball available from http://www.comedi.org #define Window_Address 4 /* W */ #define Interrupt_And_Window_Status 4 /* R */ -#define IntStatus1 (1<<0) -#define IntStatus2 (1<<1) +#define IntStatus1 BIT(0) +#define IntStatus2 BIT(1) #define WindowAddressStatus_mask 0x7c #define Master_DMA_And_Interrupt_Control 5 /* W */ #define InterruptLine(x) ((x)&3) -#define OpenInt (1<<2) +#define OpenInt BIT(2) #define Group_Status 5 /* R */ -#define DataLeft (1<<0) -#define Req (1<<2) -#define StopTrig (1<<3) +#define DataLeft BIT(0) +#define Req BIT(2) +#define StopTrig BIT(3) #define Group_1_Flags 6 /* R */ #define Group_2_Flags 7 /* R */ -#define TransferReady (1<<0) -#define CountExpired (1<<1) -#define Waited (1<<5) -#define PrimaryTC (1<<6) -#define SecondaryTC (1<<7) +#define TransferReady BIT(0) +#define CountExpired BIT(1) +#define Waited BIT(5) +#define PrimaryTC BIT(6) +#define SecondaryTC BIT(7) /* #define SerialRose */ /* #define ReqRose */ /* #define Paused */ #define Group_1_First_Clear 6 /* W */ #define Group_2_First_Clear 7 /* W */ -#define ClearWaited (1<<3) -#define ClearPrimaryTC (1<<4) -#define ClearSecondaryTC (1<<5) -#define DMAReset (1<<6) -#define FIFOReset (1<<7) +#define ClearWaited BIT(3) +#define ClearPrimaryTC BIT(4) +#define ClearSecondaryTC BIT(5) +#define DMAReset BIT(6) +#define FIFOReset BIT(7) #define ClearAll 0xf8 #define Group_1_FIFO 8 /* W */ @@ -111,27 +110,27 @@ comedi_nonfree_firmware tarball available from http://www.comedi.org #define Group_1_Second_Clear 46 /* W */ #define Group_2_Second_Clear 47 /* W */ -#define ClearExpired (1<<0) +#define ClearExpired BIT(0) #define Port_Pattern(x) (48+(x)) #define Data_Path 64 -#define FIFOEnableA (1<<0) -#define FIFOEnableB (1<<1) -#define FIFOEnableC (1<<2) -#define FIFOEnableD (1<<3) +#define FIFOEnableA BIT(0) +#define FIFOEnableB BIT(1) +#define FIFOEnableC BIT(2) +#define FIFOEnableD BIT(3) #define Funneling(x) (((x)&3)<<4) -#define GroupDirection (1<<7) +#define GroupDirection BIT(7) #define Protocol_Register_1 65 #define OpMode Protocol_Register_1 #define RunMode(x) ((x)&7) -#define Numbered (1<<3) +#define Numbered BIT(3) #define Protocol_Register_2 66 #define ClockReg Protocol_Register_2 #define ClockLine(x) (((x)&3)<<5) -#define InvertStopTrig (1<<7) +#define InvertStopTrig BIT(7) #define DataLatching(x) (((x)&3)<<5) #define Protocol_Register_3 67 @@ -152,17 +151,17 @@ comedi_nonfree_firmware tarball available from http://www.comedi.org #define Protocol_Register_6 73 #define LinePolarities Protocol_Register_6 -#define InvertAck (1<<0) -#define InvertReq (1<<1) -#define InvertClock (1<<2) -#define InvertSerial (1<<3) -#define OpenAck (1<<4) -#define OpenClock (1<<5) +#define InvertAck BIT(0) +#define InvertReq BIT(1) +#define InvertClock BIT(2) +#define InvertSerial BIT(3) +#define OpenAck BIT(4) +#define OpenClock BIT(5) #define Protocol_Register_7 74 #define AckSer Protocol_Register_7 #define AckLine(x) (((x)&3)<<2) -#define ExchangePins (1<<7) +#define ExchangePins BIT(7) #define Interrupt_Control 75 /* bits same as flags */ @@ -183,20 +182,20 @@ static inline unsigned int secondary_DMAChannel_bits(unsigned int channel) #define Transfer_Size_Control 77 #define TransferWidth(x) ((x)&3) #define TransferLength(x) (((x)&3)<<3) -#define RequireRLevel (1<<5) +#define RequireRLevel BIT(5) #define Protocol_Register_15 79 #define DAQOptions Protocol_Register_15 #define StartSource(x) ((x)&0x3) -#define InvertStart (1<<2) +#define InvertStart BIT(2) #define StopSource(x) (((x)&0x3)<<3) -#define ReqStart (1<<6) -#define PreStart (1<<7) +#define ReqStart BIT(6) +#define PreStart BIT(7) #define Pattern_Detection 81 -#define DetectionMethod (1<<0) -#define InvertMatch (1<<1) -#define IE_Pattern_Detection (1<<2) +#define DetectionMethod BIT(0) +#define InvertMatch BIT(1) +#define IE_Pattern_Detection BIT(2) #define Protocol_Register_9 82 #define ReqDelay Protocol_Register_9 @@ -649,8 +648,10 @@ static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) writeb(1, dev->mmio + AckDelay); writeb(0x0b, dev->mmio + AckNotDelay); writeb(0x01, dev->mmio + Data1Delay); - /* manual, page 4-5: ClockSpeed comment is incorrectly listed - * on DAQOptions */ + /* + * manual, page 4-5: + * ClockSpeed comment is incorrectly listed on DAQOptions + */ writew(0, dev->mmio + ClockSpeed); writeb(0, dev->mmio + DAQOptions); } else { diff --git a/drivers/staging/comedi/drivers/ni_pcimio.c b/drivers/staging/comedi/drivers/ni_pcimio.c index d8917392b9f9..f13a2f7360b3 100644 --- a/drivers/staging/comedi/drivers/ni_pcimio.c +++ b/drivers/staging/comedi/drivers/ni_pcimio.c @@ -1,111 +1,106 @@ /* - comedi/drivers/ni_pcimio.c - Hardware driver for NI PCI-MIO E series cards + * Comedi driver for NI PCI-MIO E series cards + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ /* -Driver: ni_pcimio -Description: National Instruments PCI-MIO-E series and M series (all boards) -Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans, - Herman Bruyninckx, Terry Barnaby -Status: works -Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio), - PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E, - PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E, - PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E, - PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, - PCI-6225, PXI-6225, PCI-6229, PCI-6250, - PCI-6251, PXI-6251, PCIe-6251, PXIe-6251, - PCI-6254, PCI-6259, PCIe-6259, - PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289, - PCI-6711, PXI-6711, PCI-6713, PXI-6713, - PXI-6071E, PCI-6070E, PXI-6070E, - PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733, - PCI-6143, PXI-6143 -Updated: Mon, 09 Jan 2012 14:52:48 +0000 - -These boards are almost identical to the AT-MIO E series, except that -they use the PCI bus instead of ISA (i.e., AT). See the notes for -the ni_atmio.o driver for additional information about these boards. - -Autocalibration is supported on many of the devices, using the -comedi_calibrate (or comedi_soft_calibrate for m-series) utility. -M-Series boards do analog input and analog output calibration entirely -in software. The software calibration corrects -the analog input for offset, gain and -nonlinearity. The analog outputs are corrected for offset and gain. -See the comedilib documentation on comedi_get_softcal_converter() for -more information. - -By default, the driver uses DMA to transfer analog input data to -memory. When DMA is enabled, not all triggering features are -supported. - -Digital I/O may not work on 673x. - -Note that the PCI-6143 is a simultaineous sampling device with 8 convertors. -With this board all of the convertors perform one simultaineous sample during -a scan interval. The period for a scan is used for the convert time in a -Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default. - -The RTSI trigger bus is supported on these cards on -subdevice 10. See the comedilib documentation for details. - -Information (number of channels, bits, etc.) for some devices may be -incorrect. Please check this and submit a bug if there are problems -for your device. - -SCXI is probably broken for m-series boards. - -Bugs: - - When DMA is enabled, COMEDI_EV_CONVERT does - not work correctly. + * Driver: ni_pcimio + * Description: National Instruments PCI-MIO-E series and M series (all boards) + * Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans, + * Herman Bruyninckx, Terry Barnaby + * Status: works + * Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio), + * PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, + * PCI-6040E, PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, + * PCI-6071E, PCI-6023E, PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, + * PCI-6035E, PCI-6052E, + * PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, + * PCI-6225, PXI-6225, PCI-6229, PCI-6250, + * PCI-6251, PXI-6251, PCIe-6251, PXIe-6251, + * PCI-6254, PCI-6259, PCIe-6259, + * PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289, + * PCI-6711, PXI-6711, PCI-6713, PXI-6713, + * PXI-6071E, PCI-6070E, PXI-6070E, + * PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733, + * PCI-6143, PXI-6143 + * Updated: Mon, 09 Jan 2012 14:52:48 +0000 + * + * These boards are almost identical to the AT-MIO E series, except that + * they use the PCI bus instead of ISA (i.e., AT). See the notes for the + * ni_atmio.o driver for additional information about these boards. + * + * Autocalibration is supported on many of the devices, using the + * comedi_calibrate (or comedi_soft_calibrate for m-series) utility. + * M-Series boards do analog input and analog output calibration entirely + * in software. The software calibration corrects the analog input for + * offset, gain and nonlinearity. The analog outputs are corrected for + * offset and gain. See the comedilib documentation on + * comedi_get_softcal_converter() for more information. + * + * By default, the driver uses DMA to transfer analog input data to + * memory. When DMA is enabled, not all triggering features are + * supported. + * + * Digital I/O may not work on 673x. + * + * Note that the PCI-6143 is a simultaineous sampling device with 8 + * convertors. With this board all of the convertors perform one + * simultaineous sample during a scan interval. The period for a scan + * is used for the convert time in a Comedi cmd. The convert trigger + * source is normally set to TRIG_NOW by default. + * + * The RTSI trigger bus is supported on these cards on subdevice 10. + * See the comedilib documentation for details. + * + * Information (number of channels, bits, etc.) for some devices may be + * incorrect. Please check this and submit a bug if there are problems + * for your device. + * + * SCXI is probably broken for m-series boards. + * + * Bugs: + * - When DMA is enabled, COMEDI_EV_CONVERT does not work correctly. + */ -*/ /* - The PCI-MIO E series driver was originally written by - Tomasz Motylewski <...>, and ported to comedi by ds. - - References: - - 341079b.pdf PCI E Series Register-Level Programmer Manual - 340934b.pdf DAQ-STC reference manual - - 322080b.pdf 6711/6713/6715 User Manual - - 320945c.pdf PCI E Series User Manual - 322138a.pdf PCI-6052E and DAQPad-6052E User Manual - - ISSUES: - - need to deal with external reference for DAC, and other DAC - properties in board properties - - deal with at-mio-16de-10 revision D to N changes, etc. - - need to add other CALDAC type - - need to slow down DAC loading. I don't trust NI's claim that - two writes to the PCI bus slows IO enough. I would prefer to - use udelay(). Timing specs: (clock) - AD8522 30ns - DAC8043 120ns - DAC8800 60ns - MB88341 ? - -*/ + * The PCI-MIO E series driver was originally written by + * Tomasz Motylewski <...>, and ported to comedi by ds. + * + * References: + * 341079b.pdf PCI E Series Register-Level Programmer Manual + * 340934b.pdf DAQ-STC reference manual + * + * 322080b.pdf 6711/6713/6715 User Manual + * + * 320945c.pdf PCI E Series User Manual + * 322138a.pdf PCI-6052E and DAQPad-6052E User Manual + * + * ISSUES: + * - need to deal with external reference for DAC, and other DAC + * properties in board properties + * - deal with at-mio-16de-10 revision D to N changes, etc. + * - need to add other CALDAC type + * - need to slow down DAC loading. I don't trust NI's claim that + * two writes to the PCI bus slows IO enough. I would prefer to + * use udelay(). + * Timing specs: (clock) + * AD8522 30ns + * DAC8043 120ns + * DAC8800 60ns + * MB88341 ? + */ #include <linux/module.h> #include <linux/delay.h> @@ -119,13 +114,14 @@ Bugs: #define PCIDMA -/* These are not all the possible ao ranges for 628x boards. - They can do OFFSET +- REFERENCE where OFFSET can be - 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can - be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's - 63 different possibilities. An AO channel - can not act as it's own OFFSET or REFERENCE. -*/ +/* + * These are not all the possible ao ranges for 628x boards. + * They can do OFFSET +- REFERENCE where OFFSET can be + * 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can + * be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's + * 63 different possibilities. An AO channel + * can not act as it's own OFFSET or REFERENCE. + */ static const struct comedi_lrange range_ni_M_628x_ao = { 8, { BIP_RANGE(10), diff --git a/drivers/staging/comedi/drivers/ni_usb6501.c b/drivers/staging/comedi/drivers/ni_usb6501.c index 95b537a8ecdb..5036eebb9162 100644 --- a/drivers/staging/comedi/drivers/ni_usb6501.c +++ b/drivers/staging/comedi/drivers/ni_usb6501.c @@ -465,12 +465,12 @@ static int ni6501_alloc_usb_buffers(struct comedi_device *dev) struct ni6501_private *devpriv = dev->private; size_t size; - size = le16_to_cpu(devpriv->ep_rx->wMaxPacketSize); + size = usb_endpoint_maxp(devpriv->ep_rx); devpriv->usb_rx_buf = kzalloc(size, GFP_KERNEL); if (!devpriv->usb_rx_buf) return -ENOMEM; - size = le16_to_cpu(devpriv->ep_tx->wMaxPacketSize); + size = usb_endpoint_maxp(devpriv->ep_tx); devpriv->usb_tx_buf = kzalloc(size, GFP_KERNEL); if (!devpriv->usb_tx_buf) { kfree(devpriv->usb_rx_buf); diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h index 0e20cc5c9a69..e23e63a097b5 100644 --- a/drivers/staging/comedi/drivers/plx9080.h +++ b/drivers/staging/comedi/drivers/plx9080.h @@ -60,9 +60,9 @@ struct plx_dma_desc { #define PLX_REG_LAS1RR 0x00f0 #define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */ -#define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */ -#define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */ -#define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */ +#define PLX_LASRR_MLOC_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */ +#define PLX_LASRR_MLOC_LT1MB (BIT(1) * 1) /* Locate in 1st meg */ +#define PLX_LASRR_MLOC_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */ #define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */ #define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */ /* bits that specify range for memory space decode bits */ @@ -89,11 +89,11 @@ struct plx_dma_desc { /* Local Bus Latency Timer */ #define PLX_MARBR_LT(x) (BIT(0) * ((x) & 0xff)) #define PLX_MARBR_LT_MASK GENMASK(7, 0) -#define PLX_MARBR_LT_SHIFT 0 +#define PLX_MARBR_TO_LT(r) ((r) & PLX_MARBR_LT_MASK) /* Local Bus Pause Timer */ #define PLX_MARBR_PT(x) (BIT(8) * ((x) & 0xff)) #define PLX_MARBR_PT_MASK GENMASK(15, 8) -#define PLX_MARBR_PT_SHIFT 8 +#define PLX_MARBR_TO_PT(r) (((r) & PLX_MARBR_PT_MASK) >> 8) /* Local Bus Latency Timer Enable */ #define PLX_MARBR_LTEN BIT(16) /* Local Bus Pause Timer Enable */ @@ -166,16 +166,15 @@ struct plx_dma_desc { #define PLX_REG_LBRD1 0x00f8 /* Memory Space Local Bus Width */ -#define PLX_LBRD_MSWIDTH8 (BIT(0) * 0) /* 8 bits wide */ -#define PLX_LBRD_MSWIDTH16 (BIT(0) * 1) /* 16 bits wide */ -#define PLX_LBRD_MSWIDTH32 (BIT(0) * 2) /* 32 bits wide */ -#define PLX_LBRD_MSWIDTH32A (BIT(0) * 3) /* 32 bits wide */ +#define PLX_LBRD_MSWIDTH_8 (BIT(0) * 0) /* 8 bits wide */ +#define PLX_LBRD_MSWIDTH_16 (BIT(0) * 1) /* 16 bits wide */ +#define PLX_LBRD_MSWIDTH_32 (BIT(0) * 2) /* 32 bits wide */ +#define PLX_LBRD_MSWIDTH_32A (BIT(0) * 3) /* 32 bits wide */ #define PLX_LBRD_MSWIDTH_MASK GENMASK(1, 0) -#define PLX_LBRD_MSWIDTH_SHIFT 0 /* Memory Space Internal Wait States */ #define PLX_LBRD_MSIWS(x) (BIT(2) * ((x) & 0xf)) #define PLX_LBRD_MSIWS_MASK GENMASK(5, 2) -#define PLX_LBRD_MSIWS_SHIFT 2 +#define PLX_LBRD_TO_MSIWS(r) (((r) & PLS_LBRD_MSIWS_MASK) >> 2) /* Memory Space Ready Input Enable */ #define PLX_LBRD_MSREADYIEN BIT(6) /* Memory Space BTERM# Input Enable */ @@ -193,18 +192,17 @@ struct plx_dma_desc { /* Prefetch Counter */ #define PLX_LBRD_PFCOUNT(x) (BIT(11) * ((x) & 0xf)) #define PLX_LBRD_PFCOUNT_MASK GENMASK(14, 11) -#define PLX_LBRD_PFCOUNT_SHIFT 11 +#define PLX_LBRD_TO_PFCOUNT(r) (((r) & PLX_LBRD_PFCOUNT_MASK) >> 11) /* Expansion ROM Space Local Bus Width (LBRD0 only) */ -#define PLX_LBRD0_EROMWIDTH8 (BIT(16) * 0) /* 8 bits wide */ -#define PLX_LBRD0_EROMWIDTH16 (BIT(16) * 1) /* 16 bits wide */ -#define PLX_LBRD0_EROMWIDTH32 (BIT(16) * 2) /* 32 bits wide */ -#define PLX_LBRD0_EROMWIDTH32A (BIT(16) * 3) /* 32 bits wide */ +#define PLX_LBRD0_EROMWIDTH_8 (BIT(16) * 0) /* 8 bits wide */ +#define PLX_LBRD0_EROMWIDTH_16 (BIT(16) * 1) /* 16 bits wide */ +#define PLX_LBRD0_EROMWIDTH_32 (BIT(16) * 2) /* 32 bits wide */ +#define PLX_LBRD0_EROMWIDTH_32A (BIT(16) * 3) /* 32 bits wide */ #define PLX_LBRD0_EROMWIDTH_MASK GENMASK(17, 16) -#define PLX_LBRD0_EROMWIDTH_SHIFT 16 /* Expansion ROM Space Internal Wait States (LBRD0 only) */ #define PLX_LBRD0_EROMIWS(x) (BIT(18) * ((x) & 0xf)) #define PLX_LBRD0_EROMIWS_MASK GENMASK(21, 18) -#define PLX_LBRD0_EROMIWS_SHIFT 18 +#define PLX_LBRD0_TO_EROMIWS(r) (((r) & PLX_LBRD0_EROMIWS_MASK) >> 18) /* Expansion ROM Space Ready Input Enable (LBDR0 only) */ #define PLX_LBRD0_EROMREADYIEN BIT(22) /* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */ @@ -220,7 +218,7 @@ struct plx_dma_desc { /* PCI Target Retry Delay Clocks / 8 (LBRD0 only) */ #define PLX_LBRD0_TRDELAY(x) (BIT(28) * ((x) & 0xF)) #define PLX_LBRD0_TRDELAY_MASK GENMASK(31, 28) -#define PLX_LBRD0_TRDELAY_SHIFT 28 +#define PLX_LBRD0_TO_TRDELAY(r) (((r) & PLX_LBRD0_TRDELAY_MASK) >> 28) /* Local Range Register for Direct Master to PCI */ #define PLX_REG_DMRR 0x001c @@ -241,10 +239,10 @@ struct plx_dma_desc { /* LLOCK# Input Enable */ #define PLX_DMPBAM_LLOCKIEN BIT(2) /* Direct Master Read Prefetch Size Control (bits 12, 3) */ -#define PLX_DMPBAM_RPSIZECONT ((BIT(12) * 0) | (BIT(3) * 0)) -#define PLX_DMPBAM_RPSIZE4 ((BIT(12) * 0) | (BIT(3) * 1)) -#define PLX_DMPBAM_RPSIZE8 ((BIT(12) * 1) | (BIT(3) * 0)) -#define PLX_DMPBAM_RPSIZE16 ((BIT(12) * 1) | (BIT(3) * 1)) +#define PLX_DMPBAM_RPSIZE_CONT ((BIT(12) * 0) | (BIT(3) * 0)) +#define PLX_DMPBAM_RPSIZE_4 ((BIT(12) * 0) | (BIT(3) * 1)) +#define PLX_DMPBAM_RPSIZE_8 ((BIT(12) * 1) | (BIT(3) * 0)) +#define PLX_DMPBAM_RPSIZE_16 ((BIT(12) * 1) | (BIT(3) * 1)) #define PLX_DMPBAM_RPSIZE_MASK (BIT(12) | BIT(3)) /* Direct Master PCI Read Mode - deassert IRDY when FIFO full */ #define PLX_DMPBAM_RMIRDY BIT(4) @@ -261,10 +259,10 @@ struct plx_dma_desc { /* I/O Remap Select */ #define PLX_DMPBAM_IOREMAPSEL BIT(13) /* Direct Master Write Delay */ -#define PLX_DMPBAM_WDELAYNONE (BIT(14) * 0) -#define PLX_DMPBAM_WDELAY4 (BIT(14) * 1) -#define PLX_DMPBAM_WDELAY8 (BIT(14) * 2) -#define PLX_DMPBAM_WDELAY16 (BIT(14) * 3) +#define PLX_DMPBAM_WDELAY_NONE (BIT(14) * 0) +#define PLX_DMPBAM_WDELAY_4 (BIT(14) * 1) +#define PLX_DMPBAM_WDELAY_8 (BIT(14) * 2) +#define PLX_DMPBAM_WDELAY_16 (BIT(14) * 3) #define PLX_DMPBAM_WDELAY_MASK GENMASK(15, 14) /* Remap of Local-to-PCI Space Into PCI Address Space */ #define PLX_DMPBAM_REMAP_MASK GENMASK(31, 16) @@ -279,19 +277,19 @@ struct plx_dma_desc { /* Register Number */ #define PLX_DMCFGA_REGNUM(x) (BIT(2) * ((x) & 0x3f)) #define PLX_DMCFGA_REGNUM_MASK GENMASK(7, 2) -#define PLX_DMCFGA_REGNUM_SHIFT 2 +#define PLX_DMCFGA_TO_REGNUM(r) (((r) & PLX_DMCFGA_REGNUM_MASK) >> 2) /* Function Number */ #define PLX_DMCFGA_FUNCNUM(x) (BIT(8) * ((x) & 0x7)) #define PLX_DMCFGA_FUNCNUM_MASK GENMASK(10, 8) -#define PLX_DMCFGA_FUNCNUM_SHIFT 8 +#define PLX_DMCFGA_TO_FUNCNUM(r) (((r) & PLX_DMCFGA_FUNCNUM_MASK) >> 8) /* Device Number */ #define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f)) #define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11) -#define PLX_DMCFGA_DEVNUM_SHIFT 11 +#define PLX_DMCFGA_TO_DEVNUM(r) (((r) & PLX_DMCFGA_DEVNUM_MASK) >> 11) /* Bus Number */ #define PLX_DMCFGA_BUSNUM(x) (BIT(16) * ((x) & 0xff)) #define PLX_DMCFGA_BUSNUM_MASK GENMASK(23, 16) -#define PLX_DMCFGA_BUSNUM_SHIFT 16 +#define PLX_DMCFGA_TO_BUSNUM(r) (((r) & PLX_DMCFGA_BUSNUM_MASK) >> 16) /* Configuration Enable */ #define PLX_DMCFGA_CONFIGEN BIT(31) @@ -402,22 +400,22 @@ struct plx_dma_desc { /* PCI Read Command Code For DMA */ #define PLX_CNTRL_CCRDMA(x) (BIT(0) * ((x) & 0xf)) #define PLX_CNTRL_CCRDMA_MASK GENMASK(3, 0) -#define PLX_CNTRL_CCRDMA_SHIFT 0 +#define PLX_CNTRL_TO_CCRDMA(r) ((r) & PLX_CNTRL_CCRDMA_MASK) #define PLX_CNTRL_CCRDMA_NORMAL PLX_CNTRL_CCRDMA(14) /* value after reset */ /* PCI Write Command Code For DMA 0 */ #define PLX_CNTRL_CCWDMA(x) (BIT(4) * ((x) & 0xf)) #define PLX_CNTRL_CCWDMA_MASK GENMASK(7, 4) -#define PLX_CNTRL_CCWDMA_SHIFT 4 +#define PLX_CNTRL_TO_CCWDMA(r) (((r) & PLX_CNTRL_CCWDMA_MASK) >> 4) #define PLX_CNTRL_CCWDMA_NORMAL PLX_CNTRL_CCWDMA(7) /* value after reset */ /* PCI Memory Read Command Code For Direct Master */ #define PLX_CNTRL_CCRDM(x) (BIT(8) * ((x) & 0xf)) #define PLX_CNTRL_CCRDM_MASK GENMASK(11, 8) -#define PLX_CNTRL_CCRDM_SHIFT 8 +#define PLX_CNTRL_TO_CCRDM(r) (((r) & PLX_CNTRL_CCRDM_MASK) >> 8) #define PLX_CNTRL_CCRDM_NORMAL PLX_CNTRL_CCRDM(6) /* value after reset */ /* PCI Memory Write Command Code For Direct Master */ #define PLX_CNTRL_CCWDM(x) (BIT(12) * ((x) & 0xf)) #define PLX_CNTRL_CCWDM_MASK GENMASK(15, 12) -#define PLX_CNTRL_CCWDM_SHIFT 12 +#define PLX_CNTRL_TO_CCWDM(r) (((r) & PLX_CNTRL_CCWDM_MASK) >> 12) #define PLX_CNTRL_CCWDM_NORMAL PLX_CNTRL_CCWDM(7) /* value after reset */ /* General Purpose Output (USERO) */ #define PLX_CNTRL_USERO BIT(16) @@ -464,16 +462,15 @@ struct plx_dma_desc { #define PLX_REG_DMAMODE1 0x0094 /* Local Bus Width */ -#define PLX_DMAMODE_WIDTH8 (BIT(0) * 0) /* 8 bits wide */ -#define PLX_DMAMODE_WIDTH16 (BIT(0) * 1) /* 16 bits wide */ -#define PLX_DMAMODE_WIDTH32 (BIT(0) * 2) /* 32 bits wide */ -#define PLX_DMAMODE_WIDTH32A (BIT(0) * 3) /* 32 bits wide */ +#define PLX_DMAMODE_WIDTH_8 (BIT(0) * 0) /* 8 bits wide */ +#define PLX_DMAMODE_WIDTH_16 (BIT(0) * 1) /* 16 bits wide */ +#define PLX_DMAMODE_WIDTH_32 (BIT(0) * 2) /* 32 bits wide */ +#define PLX_DMAMODE_WIDTH_32A (BIT(0) * 3) /* 32 bits wide */ #define PLX_DMAMODE_WIDTH_MASK GENMASK(1, 0) -#define PLX_DMAMODE_WIDTH_SHIFT 0 /* Internal Wait States */ #define PLX_DMAMODE_IWS(x) (BIT(2) * ((x) & 0xf)) #define PLX_DMAMODE_IWS_MASK GENMASK(5, 2) -#define PLX_DMAMODE_SHIFT 2 +#define PLX_DMAMODE_TO_IWS(r) (((r) & PLX_DMAMODE_IWS_MASK) >> 2) /* Ready Input Enable */ #define PLX_DMAMODE_READYIEN BIT(6) /* BTERM# Input Enable */ @@ -560,35 +557,35 @@ struct plx_dma_desc { /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */ #define PLX_DMATHR_C0PLAF(x) (BIT(0) * ((x) & 0xf)) #define PLX_DMATHR_C0PLAF_MASK GENMASK(3, 0) -#define PLX_DMATHR_C0PLAF_SHIFT 0 +#define PLX_DMATHR_TO_C0PLAF(r) ((r) & PLX_DMATHR_C0PLAF_MASK) /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */ #define PLX_DMATHR_C0LPAE(x) (BIT(4) * ((x) & 0xf)) #define PLX_DMATHR_C0LPAE_MASK GENMASK(7, 4) -#define PLX_DMATHR_C0LPAE_SHIFT 4 +#define PLX_DMATHR_TO_C0LPAE(r) (((r) & PLX_DMATHR_C0LPAE_MASK) >> 4) /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */ #define PLX_DMATHR_C0LPAF(x) (BIT(8) * ((x) & 0xf)) #define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8) -#define PLX_DMATHR_C0LPAF_SHIFT 8 +#define PLX_DMATHR_TO_C0LPAF(r) (((r) & PLX_DMATHR_C0LPAF_MASK) >> 8) /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */ #define PLX_DMATHR_C0PLAE(x) (BIT(12) * ((x) & 0xf)) #define PLX_DMATHR_C0PLAE_MASK GENMASK(15, 12) -#define PLX_DMATHR_C0PLAE_SHIFT 12 +#define PLX_DMATHR_TO_C0PLAE(r) (((r) & PLX_DMATHR_C0PLAE_MASK) >> 12) /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */ #define PLX_DMATHR_C1PLAF(x) (BIT(16) * ((x) & 0xf)) #define PLX_DMATHR_C1PLAF_MASK GENMASK(19, 16) -#define PLX_DMATHR_C1PLAF_SHIFT 16 +#define PLX_DMATHR_TO_C1PLAF(r) (((r) & PLX_DMATHR_C1PLAF_MASK) >> 16) /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */ #define PLX_DMATHR_C1LPAE(x) (BIT(20) * ((x) & 0xf)) #define PLX_DMATHR_C1LPAE_MASK GENMASK(23, 20) -#define PLX_DMATHR_C1LPAE_SHIFT 20 +#define PLX_DMATHR_TO_C1LPAE(r) (((r) & PLX_DMATHR_C1LPAE_MASK) >> 20) /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */ #define PLX_DMATHR_C1LPAF(x) (BIT(24) * ((x) & 0xf)) #define PLX_DMATHR_C1LPAF_MASK GENMASK(27, 24) -#define PLX_DMATHR_C1LPAF_SHIFT 24 +#define PLX_DMATHR_TO_C1LPAF(r) (((r) & PLX_DMATHR_C1LPAF_MASK) >> 24) /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */ #define PLX_DMATHR_C1PLAE(x) (BIT(28) * ((x) & 0xf)) #define PLX_DMATHR_C1PLAE_MASK GENMASK(31, 28) -#define PLX_DMATHR_C1PLAE_SHIFT 28 +#define PLX_DMATHR_TO_C1PLAE(r) (((r) & PLX_DMATHR_C1PLAE_MASK) >> 28) /* * Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR, diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c index 4a87b4b52400..c14a02564432 100644 --- a/drivers/staging/comedi/drivers/s626.c +++ b/drivers/staging/comedi/drivers/s626.c @@ -697,134 +697,6 @@ static void s626_reset_cap_flags(struct comedi_device *dev, s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set); } -#ifdef unused -/* - * Return counter setup in a format (COUNTER_SETUP) that is consistent - * for both A and B counters. - */ -static uint16_t s626_get_mode_a(struct comedi_device *dev, - unsigned int chan) -{ - uint16_t cra; - uint16_t crb; - uint16_t setup; - unsigned int cntsrc, clkmult, clkpol, encmode; - - /* Fetch CRA and CRB register images. */ - cra = s626_debi_read(dev, S626_LP_CRA(chan)); - crb = s626_debi_read(dev, S626_LP_CRB(chan)); - - /* - * Populate the standardized counter setup bit fields. - */ - setup = - /* LoadSrc = LoadSrcA. */ - S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) | - /* LatchSrc = LatchSrcA. */ - S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) | - /* IntSrc = IntSrcA. */ - S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) | - /* IndxSrc = IndxSrcA. */ - S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) | - /* IndxPol = IndxPolA. */ - S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) | - /* ClkEnab = ClkEnabA. */ - S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb)); - - /* Adjust mode-dependent parameters. */ - cntsrc = S626_GET_CRA_CNTSRC_A(cra); - if (cntsrc & S626_CNTSRC_SYSCLK) { - /* Timer mode (CntSrcA<1> == 1): */ - encmode = S626_ENCMODE_TIMER; - /* Set ClkPol to indicate count direction (CntSrcA<0>). */ - clkpol = cntsrc & 1; - /* ClkMult must be 1x in Timer mode. */ - clkmult = S626_CLKMULT_1X; - } else { - /* Counter mode (CntSrcA<1> == 0): */ - encmode = S626_ENCMODE_COUNTER; - /* Pass through ClkPol. */ - clkpol = S626_GET_CRA_CLKPOL_A(cra); - /* Force ClkMult to 1x if not legal, else pass through. */ - clkmult = S626_GET_CRA_CLKMULT_A(cra); - if (clkmult == S626_CLKMULT_SPECIAL) - clkmult = S626_CLKMULT_1X; - } - setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) | - S626_SET_STD_CLKPOL(clkpol); - - /* Return adjusted counter setup. */ - return setup; -} - -static uint16_t s626_get_mode_b(struct comedi_device *dev, - unsigned int chan) -{ - uint16_t cra; - uint16_t crb; - uint16_t setup; - unsigned int cntsrc, clkmult, clkpol, encmode; - - /* Fetch CRA and CRB register images. */ - cra = s626_debi_read(dev, S626_LP_CRA(chan)); - crb = s626_debi_read(dev, S626_LP_CRB(chan)); - - /* - * Populate the standardized counter setup bit fields. - */ - setup = - /* IntSrc = IntSrcB. */ - S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) | - /* LatchSrc = LatchSrcB. */ - S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) | - /* LoadSrc = LoadSrcB. */ - S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) | - /* IndxPol = IndxPolB. */ - S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) | - /* ClkEnab = ClkEnabB. */ - S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) | - /* IndxSrc = IndxSrcB. */ - S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra)); - - /* Adjust mode-dependent parameters. */ - cntsrc = S626_GET_CRA_CNTSRC_B(cra); - clkmult = S626_GET_CRB_CLKMULT_B(crb); - if (clkmult == S626_CLKMULT_SPECIAL) { - /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */ - encmode = S626_ENCMODE_EXTENDER; - /* Indicate multiplier is 1x. */ - clkmult = S626_CLKMULT_1X; - /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */ - clkpol = cntsrc & 1; - } else if (cntsrc & S626_CNTSRC_SYSCLK) { - /* Timer mode (CntSrcB<1> == 1): */ - encmode = S626_ENCMODE_TIMER; - /* Indicate multiplier is 1x. */ - clkmult = S626_CLKMULT_1X; - /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */ - clkpol = cntsrc & 1; - } else { - /* If Counter mode (CntSrcB<1> == 0): */ - encmode = S626_ENCMODE_COUNTER; - /* Clock multiplier is passed through. */ - /* Clock polarity is passed through. */ - clkpol = S626_GET_CRB_CLKPOL_B(crb); - } - setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) | - S626_SET_STD_CLKPOL(clkpol); - - /* Return adjusted counter setup. */ - return setup; -} - -static uint16_t s626_get_mode(struct comedi_device *dev, - unsigned int chan) -{ - return (chan < 3) ? s626_get_mode_a(dev, chan) - : s626_get_mode_b(dev, chan); -} -#endif - /* * Set the operating mode for the specified counter. The setup * parameter is treated as a COUNTER_SETUP data type. The following @@ -1023,25 +895,6 @@ static void s626_set_enable(struct comedi_device *dev, s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set); } -#ifdef unused -static uint16_t s626_get_enable(struct comedi_device *dev, - unsigned int chan) -{ - uint16_t crb = s626_debi_read(dev, S626_LP_CRB(chan)); - - return (chan < 3) ? S626_GET_CRB_CLKENAB_A(crb) - : S626_GET_CRB_CLKENAB_B(crb); -} -#endif - -#ifdef unused -static uint16_t s626_get_latch_source(struct comedi_device *dev, - unsigned int chan) -{ - return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, S626_LP_CRB(chan))); -} -#endif - /* * Return/set the event that will trigger transfer of the preload * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow, @@ -1066,19 +919,6 @@ static void s626_set_load_trig(struct comedi_device *dev, s626_debi_replace(dev, reg, ~mask, set); } -#ifdef unused -static uint16_t s626_get_load_trig(struct comedi_device *dev, - unsigned int chan) -{ - if (chan < 3) - return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev, - S626_LP_CRA(chan))); - else - return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev, - S626_LP_CRB(chan))); -} -#endif - /* * Return/set counter interrupt source and clear any captured * index/overflow events. int_source: 0=Disabled, 1=OverflowOnly, @@ -1138,93 +978,6 @@ static void s626_set_int_src(struct comedi_device *dev, } } -#ifdef unused -static uint16_t s626_get_int_src(struct comedi_device *dev, - unsigned int chan) -{ - if (chan < 3) - return S626_GET_CRA_INTSRC_A(s626_debi_read(dev, - S626_LP_CRA(chan))); - else - return S626_GET_CRB_INTSRC_B(s626_debi_read(dev, - S626_LP_CRB(chan))); -} -#endif - -#ifdef unused -/* - * Return/set the clock multiplier. - */ -static void s626_set_clk_mult(struct comedi_device *dev, - unsigned int chan, uint16_t value) -{ - uint16_t mode; - - mode = s626_get_mode(dev, chan); - mode &= ~S626_STDMSK_CLKMULT; - mode |= S626_SET_STD_CLKMULT(value); - - s626_set_mode(dev, chan, mode, false); -} - -/* - * Return/set the clock polarity. - */ -static void s626_set_clk_pol(struct comedi_device *dev, - unsigned int chan, uint16_t value) -{ - uint16_t mode; - - mode = s626_get_mode(dev, chan); - mode &= ~S626_STDMSK_CLKPOL; - mode |= S626_SET_STD_CLKPOL(value); - - s626_set_mode(dev, chan, mode, false); -} - -/* - * Return/set the encoder mode. - */ -static void s626_set_enc_mode(struct comedi_device *dev, - unsigned int chan, uint16_t value) -{ - uint16_t mode; - - mode = s626_get_mode(dev, chan); - mode &= ~S626_STDMSK_ENCMODE; - mode |= S626_SET_STD_ENCMODE(value); - - s626_set_mode(dev, chan, mode, false); -} - -static uint16_t s626_get_index_pol(struct comedi_device *dev, - unsigned int chan) -{ - return S626_GET_STD_INDXPOL(s626_get_mode(dev, chan)); -} - -/* - * Return/set the index source. - */ -static void s626_set_index_src(struct comedi_device *dev, - unsigned int chan, uint16_t value) -{ - uint16_t mode; - - mode = s626_get_mode(dev, chan); - mode &= ~S626_STDMSK_INDXSRC; - mode |= S626_SET_STD_INDXSRC(value != 0); - - s626_set_mode(dev, chan, mode, false); -} - -static uint16_t s626_get_index_src(struct comedi_device *dev, - unsigned int chan) -{ - return S626_GET_STD_INDXSRC(s626_get_mode(dev, chan)); -} -#endif - /* * Generate an index pulse. */ @@ -1717,43 +1470,6 @@ static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl) /* End of RPS program build */ } -#ifdef unused_code -static int s626_ai_rinsn(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - struct s626_private *devpriv = dev->private; - uint8_t i; - int32_t *readaddr; - - /* Trigger ADC scan loop start */ - s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); - - /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */ - while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2)) - ; - - /* - * Init ptr to DMA buffer that holds new ADC data. We skip the - * first uint16_t in the buffer because it contains junk data from - * the final ADC of the previous poll list scan. - */ - readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1; - - /* - * Convert ADC data to 16-bit integer values and - * copy to application buffer. - */ - for (i = 0; i < devpriv->adc_items; i++) { - *data = s626_ai_reg_to_uint(*readaddr++); - data++; - } - - return i; -} -#endif - static int s626_ai_eoc(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, @@ -2500,7 +2216,8 @@ static int s626_initialize(struct comedi_device *dev) for (i = 0; i < 2; i++) { writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT); s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); - ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0); + ret = comedi_timeout(dev, NULL, + NULL, s626_i2c_handshake_eoc, 0); if (ret) return ret; } diff --git a/drivers/staging/comedi/drivers/s626.h b/drivers/staging/comedi/drivers/s626.h index 6a00a64c6f3a..4cef45263267 100644 --- a/drivers/staging/comedi/drivers/s626.h +++ b/drivers/staging/comedi/drivers/s626.h @@ -79,7 +79,7 @@ /* Address offsets, in DWORDS, from base of DMA buffer. */ #define S626_DAC_WDMABUF_OS S626_ADC_DMABUF_DWORDS -/* Interrupt enable bit in ISR and IER. */ +/* Interrupt enable bit in ISR and IER. */ #define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */ #define S626_IRQ_RPS1 0x10000000 #define S626_ISR_AFOU 0x00000800 @@ -329,7 +329,7 @@ * WS1-WS4 = CS* outputs. */ -#if S626_PLATFORM == S626_INTEL /* +#if (S626_PLATFORM == S626_INTEL) /* * Base ACON1 config: always run * A1 based on TSL1. */ diff --git a/drivers/staging/comedi/drivers/usbduxfast.c b/drivers/staging/comedi/drivers/usbduxfast.c index 10f94ec34536..608403c7586b 100644 --- a/drivers/staging/comedi/drivers/usbduxfast.c +++ b/drivers/staging/comedi/drivers/usbduxfast.c @@ -946,10 +946,8 @@ static int usbduxfast_auto_attach(struct comedi_device *dev, } devpriv->urb = usb_alloc_urb(0, GFP_KERNEL); - if (!devpriv->urb) { - dev_err(dev->class_dev, "Could not alloc. urb\n"); + if (!devpriv->urb) return -ENOMEM; - } devpriv->inbuf = kmalloc(SIZEINBUF, GFP_KERNEL); if (!devpriv->inbuf) diff --git a/drivers/staging/comedi/drivers/vmk80xx.c b/drivers/staging/comedi/drivers/vmk80xx.c index 8c7393ef762d..a004aed0147a 100644 --- a/drivers/staging/comedi/drivers/vmk80xx.c +++ b/drivers/staging/comedi/drivers/vmk80xx.c @@ -177,7 +177,7 @@ static void vmk80xx_do_bulk_msg(struct comedi_device *dev) * The max packet size attributes of the K8061 * input/output endpoints are identical */ - size = le16_to_cpu(devpriv->ep_tx->wMaxPacketSize); + size = usb_endpoint_maxp(devpriv->ep_tx); usb_bulk_msg(usb, tx_pipe, devpriv->usb_tx_buf, size, NULL, devpriv->ep_tx->bInterval); @@ -199,7 +199,7 @@ static int vmk80xx_read_packet(struct comedi_device *dev) ep = devpriv->ep_rx; pipe = usb_rcvintpipe(usb, ep->bEndpointAddress); return usb_interrupt_msg(usb, pipe, devpriv->usb_rx_buf, - le16_to_cpu(ep->wMaxPacketSize), NULL, + usb_endpoint_maxp(ep), NULL, HZ * 10); } @@ -220,7 +220,7 @@ static int vmk80xx_write_packet(struct comedi_device *dev, int cmd) ep = devpriv->ep_tx; pipe = usb_sndintpipe(usb, ep->bEndpointAddress); return usb_interrupt_msg(usb, pipe, devpriv->usb_tx_buf, - le16_to_cpu(ep->wMaxPacketSize), NULL, + usb_endpoint_maxp(ep), NULL, HZ * 10); } @@ -230,7 +230,7 @@ static int vmk80xx_reset_device(struct comedi_device *dev) size_t size; int retval; - size = le16_to_cpu(devpriv->ep_tx->wMaxPacketSize); + size = usb_endpoint_maxp(devpriv->ep_tx); memset(devpriv->usb_tx_buf, 0, size); retval = vmk80xx_write_packet(dev, VMK8055_CMD_RST); if (retval) @@ -684,12 +684,12 @@ static int vmk80xx_alloc_usb_buffers(struct comedi_device *dev) struct vmk80xx_private *devpriv = dev->private; size_t size; - size = le16_to_cpu(devpriv->ep_rx->wMaxPacketSize); + size = usb_endpoint_maxp(devpriv->ep_rx); devpriv->usb_rx_buf = kzalloc(size, GFP_KERNEL); if (!devpriv->usb_rx_buf) return -ENOMEM; - size = le16_to_cpu(devpriv->ep_tx->wMaxPacketSize); + size = usb_endpoint_maxp(devpriv->ep_tx); devpriv->usb_tx_buf = kzalloc(size, GFP_KERNEL); if (!devpriv->usb_tx_buf) { kfree(devpriv->usb_rx_buf); |