diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch new file mode 100644 index 00000000..5aac7746 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch @@ -0,0 +1,124 @@ +From 9a383d04b57ff6e3339a1d679458a3dbc02e23a9 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 18 Nov 2019 12:21:26 -0500 +Subject: [PATCH 4520/4736] Revert "drm/amdgpu: don't read registers if gfxoff + is enabled (v2)" + +This reverts commit 5e49d6f654c569c2de920babbaf5cf7c4c4a353f. + +Drop this workaround in favor of a better one. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/nv.c | 27 ++++++++++---------------- + drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++++++++++++------------------ + 2 files changed, 22 insertions(+), 36 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c +index 91b0482278c2..4a52e5d59807 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nv.c ++++ b/drivers/gpu/drm/amd/amdgpu/nv.c +@@ -221,25 +221,17 @@ static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, + return val; + } + +-static int nv_get_register_value(struct amdgpu_device *adev, ++static uint32_t nv_get_register_value(struct amdgpu_device *adev, + bool indexed, u32 se_num, +- u32 sh_num, u32 reg_offset, +- u32 *value) ++ u32 sh_num, u32 reg_offset) + { + if (indexed) { +- if (adev->pm.pp_feature & PP_GFXOFF_MASK) +- return -EINVAL; +- *value = nv_read_indexed_register(adev, se_num, sh_num, reg_offset); ++ return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); + } else { +- if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) { +- *value = adev->gfx.config.gb_addr_config; +- } else { +- if (adev->pm.pp_feature & PP_GFXOFF_MASK) +- return -EINVAL; +- *value = RREG32(reg_offset); +- } ++ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) ++ return adev->gfx.config.gb_addr_config; ++ return RREG32(reg_offset); + } +- return 0; + } + + static int nv_read_register(struct amdgpu_device *adev, u32 se_num, +@@ -255,9 +247,10 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num, + (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) + continue; + +- return nv_get_register_value(adev, +- nv_allowed_read_registers[i].grbm_indexed, +- se_num, sh_num, reg_offset, value); ++ *value = nv_get_register_value(adev, ++ nv_allowed_read_registers[i].grbm_indexed, ++ se_num, sh_num, reg_offset); ++ return 0; + } + return -EINVAL; + } +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 67e84e8493b8..a458dded99c6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -364,27 +364,19 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n + return val; + } + +-static int soc15_get_register_value(struct amdgpu_device *adev, ++static uint32_t soc15_get_register_value(struct amdgpu_device *adev, + bool indexed, u32 se_num, +- u32 sh_num, u32 reg_offset, +- u32 *value) ++ u32 sh_num, u32 reg_offset) + { + if (indexed) { +- if (adev->pm.pp_feature & PP_GFXOFF_MASK) +- return -EINVAL; +- *value = soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); ++ return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); + } else { +- if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) { +- *value = adev->gfx.config.gb_addr_config; +- } else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) { +- *value = adev->gfx.config.db_debug2; +- } else { +- if (adev->pm.pp_feature & PP_GFXOFF_MASK) +- return -EINVAL; +- *value = RREG32(reg_offset); +- } ++ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) ++ return adev->gfx.config.gb_addr_config; ++ else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) ++ return adev->gfx.config.db_debug2; ++ return RREG32(reg_offset); + } +- return 0; + } + + static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, +@@ -400,9 +392,10 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, + + en->reg_offset)) + continue; + +- return soc15_get_register_value(adev, +- soc15_allowed_read_registers[i].grbm_indexed, +- se_num, sh_num, reg_offset, value); ++ *value = soc15_get_register_value(adev, ++ soc15_allowed_read_registers[i].grbm_indexed, ++ se_num, sh_num, reg_offset); ++ return 0; + } + return -EINVAL; + } +-- +2.17.1 + |