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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch new file mode 100644 index 00000000..d2853f2b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch @@ -0,0 +1,51 @@ +From 5f7f2f8aea196df5274a3bf3a7ff96d119be54d7 Mon Sep 17 00:00:00 2001 +From: Joshua Aberback <joshua.aberback@amd.com> +Date: Fri, 1 Nov 2019 17:29:20 -0400 +Subject: [PATCH 4489/4736] drm/amd/display: Adjust DML workaround threshold + +[Why] +There is a case where the margin is between 50 and 60, but applying the +workaround causes a hang. By increasing the threshold, we are blocking more +cases from switching p-state during active, but those cases will fall back +to switching during blank, which is fine. + +[How] + - increase required margin from 50 to 60 + +Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> +Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> +Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 2 +- + .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +index 77b7574c63cb..3b224b155e8c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +@@ -2578,7 +2578,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer + + mode_lib->vba.DRAMClockChangeLatency; + + if (mode_lib->vba.DRAMClockChangeSupportsVActive && +- mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) { ++ mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) { + mode_lib->vba.DRAMClockChangeWatermark += 25; + mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; + } else { +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +index 62dfd36d830a..6482d7b99bae 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +@@ -2612,7 +2612,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP + + mode_lib->vba.DRAMClockChangeLatency; + + if (mode_lib->vba.DRAMClockChangeSupportsVActive && +- mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) { ++ mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) { + mode_lib->vba.DRAMClockChangeWatermark += 25; + mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; + } else if (mode_lib->vba.DummyPStateCheck && +-- +2.17.1 + |