diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4068-drm-amd-display-fix-code-to-control-48mhz-refclk.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4068-drm-amd-display-fix-code-to-control-48mhz-refclk.patch | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4068-drm-amd-display-fix-code-to-control-48mhz-refclk.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4068-drm-amd-display-fix-code-to-control-48mhz-refclk.patch new file mode 100644 index 00000000..27a53f0f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4068-drm-amd-display-fix-code-to-control-48mhz-refclk.patch @@ -0,0 +1,87 @@ +From 70252b3921032d75c238d0c0344c847daaca5dfa Mon Sep 17 00:00:00 2001 +From: Eric Yang <Eric.Yang2@amd.com> +Date: Thu, 18 Jul 2019 13:56:59 -0400 +Subject: [PATCH 4068/4256] drm/amd/display: fix code to control 48mhz refclk + +[Why] +The SMU message to enable this feature looks at argument. Previous code +didn't send right argument. This change will allow the feature to be +be enabled. + +[How] +Fixed one issue where SMU message to enable the feature was sent without +setting the parameter. + +Signed-off-by: Eric Yang <Eric.Yang2@amd.com> +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 7 ++++--- + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 4 ++-- + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h | 2 +- + drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +- + 4 files changed, 8 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +index c0e58434be39..a2a4c7ddc856 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +@@ -649,8 +649,9 @@ void rn_clk_mgr_construct( + pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges); + } + +- /* enable powerfeatures when displaycount goes to 0 */ +- if (!debug->disable_48mhz_pwrdwn) +- rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr); ++ if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { ++ /* enable powerfeatures when displaycount goes to 0 */ ++ rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn); ++ } + } + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c +index fd919b82e902..8e860f567d5c 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c +@@ -190,12 +190,12 @@ void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum + disp_count); + } + +-void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr) ++void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) + { + rn_vbios_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown, +- 0); ++ enable); + } + + void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h +index fe2986a2c7a2..ccc01879c9d4 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h +@@ -34,7 +34,7 @@ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int + void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz); + int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); + void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count); +-void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr); ++void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); + void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); + + #endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index 5a6e55b7d536..15914bf70008 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -804,7 +804,7 @@ static const struct dc_debug_options debug_defaults_drv = { + .disable_pplib_wm_range = false, + .scl_reset_length10 = true, + .sanity_checks = true, +- .disable_48mhz_pwrdwn = true, ++ .disable_48mhz_pwrdwn = false, + }; + + static const struct dc_debug_options debug_defaults_diags = { +-- +2.17.1 + |