diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3929-drm-amdgpu-move-gfx-ecc-functions-to-generic-gfx-fil.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3929-drm-amdgpu-move-gfx-ecc-functions-to-generic-gfx-fil.patch | 152 |
1 files changed, 152 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3929-drm-amdgpu-move-gfx-ecc-functions-to-generic-gfx-fil.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3929-drm-amdgpu-move-gfx-ecc-functions-to-generic-gfx-fil.patch new file mode 100644 index 00000000..f8addef6 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3929-drm-amdgpu-move-gfx-ecc-functions-to-generic-gfx-fil.patch @@ -0,0 +1,152 @@ +From b2b6ce6d6ec7bc017402393544f278f9ee94d090 Mon Sep 17 00:00:00 2001 +From: Tao Zhou <tao.zhou1@amd.com> +Date: Thu, 12 Sep 2019 14:06:35 +0800 +Subject: [PATCH 3929/4256] drm/amdgpu: move gfx ecc functions to generic gfx + file + +gfx ras ecc common functions could be reused among all gfx generations + +Signed-off-by: Tao Zhou <tao.zhou1@amd.com> +Reviewed-by: Guchun Chen <guchun.chen@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 33 ++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 ++++ + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 41 ++----------------------- + 3 files changed, 41 insertions(+), 39 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +index 508d521a0e59..e7d87f717737 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +@@ -618,3 +618,36 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, + adev->gfx.ras_if = NULL; + return r; + } ++ ++int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, ++ void *err_data, ++ struct amdgpu_iv_entry *entry) ++{ ++ /* TODO ue will trigger an interrupt. */ ++ if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) { ++ kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); ++ if (adev->gfx.funcs->query_ras_error_count) ++ adev->gfx.funcs->query_ras_error_count(adev, err_data); ++ amdgpu_ras_reset_gpu(adev, 0); ++ } ++ return AMDGPU_RAS_SUCCESS; ++} ++ ++int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, ++ struct amdgpu_irq_src *source, ++ struct amdgpu_iv_entry *entry) ++{ ++ struct ras_common_if *ras_if = adev->gfx.ras_if; ++ struct ras_dispatch_if ih_data = { ++ .entry = entry, ++ }; ++ ++ if (!ras_if) ++ return 0; ++ ++ ih_data.head = *ras_if; ++ ++ DRM_ERROR("CP ECC ERROR IRQ\n"); ++ amdgpu_ras_interrupt_dispatch(adev, &ih_data); ++ return 0; ++} +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +index 59c5464c96be..179dd4e980b7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +@@ -360,4 +360,10 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, + void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); + int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, + void *ras_ih_info); ++int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, ++ void *err_data, ++ struct amdgpu_iv_entry *entry); ++int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, ++ struct amdgpu_irq_src *source, ++ struct amdgpu_iv_entry *entry); + #endif +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index edeac8eb8cc6..b238f8b45336 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -4201,15 +4201,11 @@ static int gfx_v9_0_early_init(void *handle) + return 0; + } + +-static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev, +- void *err_data, +- struct amdgpu_iv_entry *entry); +- + static int gfx_v9_0_ecc_late_init(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct ras_ih_if ih_info = { +- .cb = gfx_v9_0_process_ras_data_cb, ++ .cb = amdgpu_gfx_process_ras_data_cb, + }; + int r; + +@@ -5454,20 +5450,6 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, + return 0; + } + +-static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev, +- void *err_data, +- struct amdgpu_iv_entry *entry) +-{ +- /* TODO ue will trigger an interrupt. */ +- if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) { +- kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); +- if (adev->gfx.funcs->query_ras_error_count) +- adev->gfx.funcs->query_ras_error_count(adev, err_data); +- amdgpu_ras_reset_gpu(adev, 0); +- } +- return AMDGPU_RAS_SUCCESS; +-} +- + static const struct { + const char *name; + uint32_t ip; +@@ -5876,25 +5858,6 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, + return 0; + } + +-static int gfx_v9_0_cp_ecc_error_irq(struct amdgpu_device *adev, +- struct amdgpu_irq_src *source, +- struct amdgpu_iv_entry *entry) +-{ +- struct ras_common_if *ras_if = adev->gfx.ras_if; +- struct ras_dispatch_if ih_data = { +- .entry = entry, +- }; +- +- if (!ras_if) +- return 0; +- +- ih_data.head = *ras_if; +- +- DRM_ERROR("CP ECC ERROR IRQ\n"); +- amdgpu_ras_interrupt_dispatch(adev, &ih_data); +- return 0; +-} +- + static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { + .name = "gfx_v9_0", + .early_init = gfx_v9_0_early_init, +@@ -6058,7 +6021,7 @@ static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { + + static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { + .set = gfx_v9_0_set_cp_ecc_error_state, +- .process = gfx_v9_0_cp_ecc_error_irq, ++ .process = amdgpu_gfx_cp_ecc_error_irq, + }; + + +-- +2.17.1 + |