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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3925-drm-amdgpu-remove-gfx9-NGG.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3925-drm-amdgpu-remove-gfx9-NGG.patch390
1 files changed, 390 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3925-drm-amdgpu-remove-gfx9-NGG.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3925-drm-amdgpu-remove-gfx9-NGG.patch
new file mode 100644
index 00000000..76a6f619
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3925-drm-amdgpu-remove-gfx9-NGG.patch
@@ -0,0 +1,390 @@
+From 07f53a0f4b1f1c67c01959654d8a958d601ec01c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 19 Sep 2019 22:04:43 -0400
+Subject: [PATCH 3925/4256] drm/amdgpu: remove gfx9 NGG
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Never used.
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 41 -----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 25 ---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 --
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 195 ------------------------
+ 5 files changed, 277 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 8c2c52fe43a9..24f3b548f368 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -151,11 +151,6 @@ extern char *amdgpu_disable_cu;
+ extern char *amdgpu_virtual_display;
+ extern uint amdgpu_pp_feature_mask;
+ extern int amdgpu_ssg_enabled;
+-extern int amdgpu_ngg;
+-extern int amdgpu_prim_buf_per_se;
+-extern int amdgpu_pos_buf_per_se;
+-extern int amdgpu_cntl_sb_buf_per_se;
+-extern int amdgpu_param_buf_per_se;
+ extern int amdgpu_job_hang_limit;
+ extern int amdgpu_lbpw;
+ extern int amdgpu_compute_multipipe;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 50f962a78a61..9f7118ab1e93 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -131,11 +131,6 @@ char *amdgpu_disable_cu = NULL;
+ char *amdgpu_virtual_display = NULL;
+ /* OverDrive(bit 14) disabled by default*/
+ uint amdgpu_pp_feature_mask = 0xffffbfff;
+-int amdgpu_ngg = 0;
+-int amdgpu_prim_buf_per_se = 0;
+-int amdgpu_pos_buf_per_se = 0;
+-int amdgpu_cntl_sb_buf_per_se = 0;
+-int amdgpu_param_buf_per_se = 0;
+ int amdgpu_job_hang_limit = 0;
+ int amdgpu_lbpw = -1;
+ int amdgpu_compute_multipipe = -1;
+@@ -464,42 +459,6 @@ MODULE_PARM_DESC(virtual_display,
+ "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
+ module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
+
+-/**
+- * DOC: ngg (int)
+- * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
+- */
+-MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
+-module_param_named(ngg, amdgpu_ngg, int, 0444);
+-
+-/**
+- * DOC: prim_buf_per_se (int)
+- * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
+- */
+-MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
+-module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
+-
+-/**
+- * DOC: pos_buf_per_se (int)
+- * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
+- */
+-MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
+-module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
+-
+-/**
+- * DOC: cntl_sb_buf_per_se (int)
+- * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
+- */
+-MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
+-module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
+-
+-/**
+- * DOC: param_buf_per_se (int)
+- * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
+- * The default is 0 (depending on gfx).
+- */
+-MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
+-module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
+-
+ /**
+ * DOC: job_hang_limit (int)
+ * Set how much time allow a job hang and not drop it. The default is 0.
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 6ed0560d7299..59c5464c96be 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -200,28 +200,6 @@ struct amdgpu_gfx_funcs {
+ int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
+ };
+
+-struct amdgpu_ngg_buf {
+- struct amdgpu_bo *bo;
+- uint64_t gpu_addr;
+- uint32_t size;
+- uint32_t bo_size;
+-};
+-
+-enum {
+- NGG_PRIM = 0,
+- NGG_POS,
+- NGG_CNTL,
+- NGG_PARAM,
+- NGG_BUF_MAX
+-};
+-
+-struct amdgpu_ngg {
+- struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
+- uint32_t gds_reserve_addr;
+- uint32_t gds_reserve_size;
+- bool init;
+-};
+-
+ struct sq_work {
+ struct work_struct work;
+ unsigned ih_data;
+@@ -310,9 +288,6 @@ struct amdgpu_gfx {
+ uint32_t grbm_soft_reset;
+ uint32_t srbm_soft_reset;
+
+- /* NGG */
+- struct amdgpu_ngg ngg;
+-
+ /* gfx off */
+ bool gfx_off_state; /* true: enabled, false: disabled */
+ struct mutex gfx_off_mutex;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 9be4c182242f..75965119271b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -781,17 +781,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ dev_info.vce_harvest_config = adev->vce.harvest_config;
+ dev_info.gc_double_offchip_lds_buf =
+ adev->gfx.config.double_offchip_lds_buf;
+-
+- if (amdgpu_ngg) {
+- dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
+- dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
+- dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
+- dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
+- dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
+- dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
+- dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
+- dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
+- }
+ dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
+ dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
+ dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 946e21869a8e..c1f5970d59e6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1953,190 +1953,6 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
+- struct amdgpu_ngg_buf *ngg_buf,
+- int size_se,
+- int default_size_se)
+-{
+- int r;
+-
+- if (size_se < 0) {
+- dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
+- return -EINVAL;
+- }
+- size_se = size_se ? size_se : default_size_se;
+-
+- ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
+- r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
+- PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+- &ngg_buf->bo,
+- &ngg_buf->gpu_addr,
+- NULL);
+- if (r) {
+- dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
+- return r;
+- }
+- ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
+-
+- return r;
+-}
+-
+-static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
+-{
+- int i;
+-
+- for (i = 0; i < NGG_BUF_MAX; i++)
+- amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
+- &adev->gfx.ngg.buf[i].gpu_addr,
+- NULL);
+-
+- memset(&adev->gfx.ngg.buf[0], 0,
+- sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
+-
+- adev->gfx.ngg.init = false;
+-
+- return 0;
+-}
+-
+-static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
+-{
+- int r;
+-
+- if (!amdgpu_ngg || adev->gfx.ngg.init == true)
+- return 0;
+-
+- /* GDS reserve memory: 64 bytes alignment */
+- adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
+- adev->gds.gds_size -= adev->gfx.ngg.gds_reserve_size;
+- adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
+- adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
+-
+- /* Primitive Buffer */
+- r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
+- amdgpu_prim_buf_per_se,
+- 64 * 1024);
+- if (r) {
+- dev_err(adev->dev, "Failed to create Primitive Buffer\n");
+- goto err;
+- }
+-
+- /* Position Buffer */
+- r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
+- amdgpu_pos_buf_per_se,
+- 256 * 1024);
+- if (r) {
+- dev_err(adev->dev, "Failed to create Position Buffer\n");
+- goto err;
+- }
+-
+- /* Control Sideband */
+- r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
+- amdgpu_cntl_sb_buf_per_se,
+- 256);
+- if (r) {
+- dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
+- goto err;
+- }
+-
+- /* Parameter Cache, not created by default */
+- if (amdgpu_param_buf_per_se <= 0)
+- goto out;
+-
+- r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
+- amdgpu_param_buf_per_se,
+- 512 * 1024);
+- if (r) {
+- dev_err(adev->dev, "Failed to create Parameter Cache\n");
+- goto err;
+- }
+-
+-out:
+- adev->gfx.ngg.init = true;
+- return 0;
+-err:
+- gfx_v9_0_ngg_fini(adev);
+- return r;
+-}
+-
+-static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
+-{
+- struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
+- int r;
+- u32 data, base;
+-
+- if (!amdgpu_ngg)
+- return 0;
+-
+- /* Program buffer size */
+- data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
+- adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
+- data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
+- adev->gfx.ngg.buf[NGG_POS].size >> 8);
+- WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
+-
+- data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
+- adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
+- data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
+- adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
+- WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
+-
+- /* Program buffer base address */
+- base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
+- data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
+- WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
+-
+- base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
+- data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
+- WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
+-
+- base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
+- data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
+- WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
+-
+- base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
+- data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
+- WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
+-
+- base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
+- data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
+- WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
+-
+- base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
+- data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
+- WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
+-
+- /* Clear GDS reserved memory */
+- r = amdgpu_ring_alloc(ring, 17);
+- if (r) {
+- DRM_ERROR("amdgpu: NGG failed to lock ring %s (%d).\n",
+- ring->name, r);
+- return r;
+- }
+-
+- gfx_v9_0_write_data_to_reg(ring, 0, false,
+- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
+- (adev->gds.gds_size +
+- adev->gfx.ngg.gds_reserve_size));
+-
+- amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
+- amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
+- PACKET3_DMA_DATA_DST_SEL(1) |
+- PACKET3_DMA_DATA_SRC_SEL(2)));
+- amdgpu_ring_write(ring, 0);
+- amdgpu_ring_write(ring, 0);
+- amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
+- amdgpu_ring_write(ring, 0);
+- amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
+- adev->gfx.ngg.gds_reserve_size);
+-
+- gfx_v9_0_write_data_to_reg(ring, 0, false,
+- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
+-
+- amdgpu_ring_commit(ring);
+-
+- return 0;
+-}
+-
+ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
+ int mec, int pipe, int queue)
+ {
+@@ -2304,10 +2120,6 @@ static int gfx_v9_0_sw_init(void *handle)
+ if (r)
+ return r;
+
+- r = gfx_v9_0_ngg_init(adev);
+- if (r)
+- return r;
+-
+ return 0;
+ }
+
+@@ -2341,7 +2153,6 @@ static int gfx_v9_0_sw_fini(void *handle)
+ amdgpu_gfx_kiq_fini(adev);
+
+ gfx_v9_0_mec_fini(adev);
+- gfx_v9_0_ngg_fini(adev);
+ amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
+ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
+ amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
+@@ -3882,12 +3693,6 @@ static int gfx_v9_0_hw_init(void *handle)
+ if (r)
+ return r;
+
+- if (adev->asic_type != CHIP_ARCTURUS) {
+- r = gfx_v9_0_ngg_en(adev);
+- if (r)
+- return r;
+- }
+-
+ return r;
+ }
+
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-26 12:28:24 +0000