diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3842-drm-amd-display-update-odm-mode-validation-to-be-in-.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3842-drm-amd-display-update-odm-mode-validation-to-be-in-.patch | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3842-drm-amd-display-update-odm-mode-validation-to-be-in-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3842-drm-amd-display-update-odm-mode-validation-to-be-in-.patch new file mode 100644 index 00000000..6e03c996 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3842-drm-amd-display-update-odm-mode-validation-to-be-in-.patch @@ -0,0 +1,113 @@ +From 3ce73c2b6ec251fba6b91c0e65b7bb6938f5b9e4 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Fri, 30 Aug 2019 16:32:13 -0400 +Subject: [PATCH 3842/4256] drm/amd/display: update odm mode validation to be + in line with policy + +Previously 8k30 worked with dsc and odm combine due to a workaround that ran +the formula a second time with dsc support enable should dsc validation fail. +This worked when clocks were low enough for formula to enable odm to lower +voltage, however now broke due to increased clocks. + +This change updates the ODM combine policy within the formula to properly +reflect our current policy within DC, only enabling ODM when we have to, as +well as adding a check for viewport width when dsc is enabled. + +As a side effect the redundant call to dml when odm is required is now +unnecessary. + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 22 +------------------ + .../dc/dml/dcn20/display_mode_vba_20v2.c | 9 +++++++- + 2 files changed, 9 insertions(+), 22 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index d1901ab5fb8c..8d81c65157d4 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -2246,11 +2246,7 @@ bool dcn20_fast_validate_bw( + bool out = false; + + int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit; +- bool odm_capable = context->bw_ctx.dml.ip.odm_capable; + bool force_split = false; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +- bool failed_non_odm_dsc = false; +-#endif + int split_threshold = dc->res_pool->pipe_count / 2; + bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC; + +@@ -2327,24 +2323,8 @@ bool dcn20_fast_validate_bw( + goto validate_out; + } + +- context->bw_ctx.dml.ip.odm_capable = 0; +- + vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); + +- context->bw_ctx.dml.ip.odm_capable = odm_capable; +- +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +- /* 1 dsc per stream dsc validation */ +- if (vlevel <= context->bw_ctx.dml.soc.num_states) +- if (!dcn20_validate_dsc(dc, context)) { +- failed_non_odm_dsc = true; +- vlevel = context->bw_ctx.dml.soc.num_states + 1; +- } +-#endif +- +- if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable) +- vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); +- + if (vlevel > context->bw_ctx.dml.soc.num_states) + goto validate_fail; + +@@ -2480,7 +2460,7 @@ bool dcn20_fast_validate_bw( + } + #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* Actual dsc count per stream dsc validation*/ +- if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) { ++ if (!dcn20_validate_dsc(dc, context)) { + context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = + DML_FAIL_DSC_VALIDATION_FAILURE; + goto validate_fail; +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +index 0fafd693ffb4..841ed6c23f93 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +@@ -38,6 +38,7 @@ + + #define BPP_INVALID 0 + #define BPP_BLENDED_PIPE 0xffffffff ++#define DCN20_MAX_DSC_IMAGE_WIDTH 5184 + + static double adjust_ReturnBW( + struct display_mode_lib *mode_lib, +@@ -3901,6 +3902,10 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode + mode_lib->vba.MaximumSwathWidthInLineBuffer); + } + for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { ++ double MaxMaxDispclkRoundedDown = RoundToDFSGranularityDown( ++ mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], ++ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); ++ + for (j = 0; j < 2; j++) { + mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown( + mode_lib->vba.MaxDispclk[i], +@@ -3925,7 +3930,9 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode + && i == mode_lib->vba.soc.num_states) + mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 + * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); +- if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) { ++ if (mode_lib->vba.ODMCapability == false || ++ (locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown ++ && (!locals->DSCEnabled[k] || locals->HActive[k] <= DCN20_MAX_DSC_IMAGE_WIDTH))) { + locals->ODMCombineEnablePerState[i][k] = false; + mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine; + } else { +-- +2.17.1 + |