diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3745-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3745-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch | 188 |
1 files changed, 188 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3745-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3745-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch new file mode 100644 index 00000000..20ade8ee --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3745-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch @@ -0,0 +1,188 @@ +From 1cf6a881d1889000886c14e105da27e846b89c08 Mon Sep 17 00:00:00 2001 +From: Hawking Zhang <Hawking.Zhang@amd.com> +Date: Tue, 3 Sep 2019 06:48:00 +0800 +Subject: [PATCH 3745/4256] drm/amdgpu/nbio: switch to + amdgpu_nbio_ras_late_init helper function + +amdgpu_nbio_ras_late_init is used to init nbio specfic +ras debugfs/sysfs node and nbio specific interrupt handler. +It can be shared among nbio generations + +Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> +Reviewed-by: Tao Zhou <tao.zhou1@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c | 70 ++++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 + + drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 49 +---------------- + 4 files changed, 74 insertions(+), 49 deletions(-) + create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c + +diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile +index 3baa143714ab..655e5f0cf7b2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/Makefile ++++ b/drivers/gpu/drm/amd/amdgpu/Makefile +@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ + amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \ + amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_sem.o \ + amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_vm_sdma.o amdgpu_pmu.o \ +- amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o ++ amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o smu_v11_0_i2c.o + + amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c +new file mode 100644 +index 000000000000..65373ad03763 +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (C) 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "amdgpu.h" ++#include "amdgpu_ras.h" ++ ++int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev) ++{ ++ int r; ++ struct ras_ih_if ih_info = { ++ .cb = NULL, ++ }; ++ struct ras_fs_if fs_info = { ++ .sysfs_name = "pcie_bif_err_count", ++ .debugfs_name = "pcie_bif_err_inject", ++ }; ++ ++ if (!adev->nbio.ras_if) { ++ adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); ++ if (!adev->nbio.ras_if) ++ return -ENOMEM; ++ adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF; ++ adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; ++ adev->nbio.ras_if->sub_block_index = 0; ++ strcpy(adev->nbio.ras_if->name, "pcie_bif"); ++ } ++ ih_info.head = fs_info.head = *adev->nbio.ras_if; ++ r = amdgpu_ras_late_init(adev, adev->nbio.ras_if, ++ &fs_info, &ih_info); ++ if (r) ++ goto free; ++ ++ if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { ++ r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0); ++ if (r) ++ goto late_fini; ++ r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); ++ if (r) ++ goto late_fini; ++ } else { ++ r = 0; ++ goto free; ++ } ++ ++ return 0; ++late_fini: ++ amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info); ++free: ++ kfree(adev->nbio.ras_if); ++ adev->nbio.ras_if = NULL; ++ return r; ++} +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +index 51078da6188f..c5255a7fd65a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +@@ -92,4 +92,6 @@ struct amdgpu_nbio { + const struct amdgpu_nbio_funcs *funcs; + }; + ++int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev); ++ + #endif +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +index f25c6a9c6718..bfa919190fb4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +@@ -474,53 +474,6 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a + return 0; + } + +-static int nbio_v7_4_ras_late_init(struct amdgpu_device *adev) +-{ +- int r; +- struct ras_ih_if ih_info = { +- .cb = NULL, +- }; +- struct ras_fs_if fs_info = { +- .sysfs_name = "pcie_bif_err_count", +- .debugfs_name = "pcie_bif_err_inject", +- }; +- +- if (!adev->nbio.ras_if) { +- adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); +- if (!adev->nbio.ras_if) +- return -ENOMEM; +- adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF; +- adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; +- adev->nbio.ras_if->sub_block_index = 0; +- strcpy(adev->nbio.ras_if->name, "pcie_bif"); +- } +- ih_info.head = fs_info.head = *adev->nbio.ras_if; +- r = amdgpu_ras_late_init(adev, adev->nbio.ras_if, +- &fs_info, &ih_info); +- if (r) +- goto free; +- +- if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { +- r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0); +- if (r) +- goto late_fini; +- r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); +- if (r) +- goto late_fini; +- } else { +- r = 0; +- goto free; +- } +- +- return 0; +-late_fini: +- amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info); +-free: +- kfree(adev->nbio.ras_if); +- adev->nbio.ras_if = NULL; +- return r; +-} +- + const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { + .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, +@@ -546,5 +499,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { + .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring, + .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt, + .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt, +- .ras_late_init = nbio_v7_4_ras_late_init, ++ .ras_late_init = amdgpu_nbio_ras_late_init, + }; +-- +2.17.1 + |