1 files changed, 36 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3718-drm-amd-display-OTC-underflow-fix.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3718-drm-amd-display-OTC-underflow-fix.patch
new file mode 100644
index 00000000..4858bfd0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3718-drm-amd-display-OTC-underflow-fix.patch
@@ -0,0 +1,36 @@
+From dedffd08ed8a6514f28a5c0bb427d6b125d19243 Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Mon, 19 Aug 2019 16:45:05 -0400
+Subject: [PATCH 3718/4256] drm/amd/display: OTC underflow fix
+
+[Why] Underflow occurs on some display setups(repro'd on 3x4K HDR) on boot,
+mode set, and hot-plugs with. Underflow occurs because mem clk
+is not set high after disabling pstate switching. This behaviour occurs
+because some calculations assumed displays were synchronized.
+
+[How] Add a condition to check if timing sync is disabled so that
+synchronized vblank can be set to false.
+
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 353e3e7cb929..62e9a9826c97 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1757,7 +1757,7 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipe_cnt = i;
+ 			continue;
+ 		}
+-		if (!resource_are_streams_timing_synchronizable(
++		if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
+ 				res_ctx->pipe_ctx[pipe_cnt].stream,
+ 				res_ctx->pipe_ctx[i].stream)) {
+ 			synchronized_vblank = false;
+-- 
+2.17.1
+