diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3651-drm-amd-display-Correct-order-of-RV-family-clk-manag.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3651-drm-amd-display-Correct-order-of-RV-family-clk-manag.patch | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3651-drm-amd-display-Correct-order-of-RV-family-clk-manag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3651-drm-amd-display-Correct-order-of-RV-family-clk-manag.patch new file mode 100644 index 00000000..2af0778b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3651-drm-amd-display-Correct-order-of-RV-family-clk-manag.patch @@ -0,0 +1,48 @@ +From d946392e6b120aee16a1c4ace2187fe2538c6e83 Mon Sep 17 00:00:00 2001 +From: Roman Li <Roman.Li@amd.com> +Date: Thu, 8 Aug 2019 15:11:37 -0400 +Subject: [PATCH 3651/4256] drm/amd/display: Correct order of RV family clk + managers for Renoir + +Need to check for renoir first. + +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Roman Li <Roman.Li@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +index 66277a9a4ec2..8da1256bc144 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +@@ -109,6 +109,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p + + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case FAMILY_RV: ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) { ++ rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); ++ break; ++ } ++#endif /* DCN2_1 */ + if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) { + rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); + break; +@@ -118,12 +124,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p + rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); + break; + } +-#if defined(CONFIG_DRM_AMD_DC_DCN2_1) +- if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) { +- rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); +- break; +- } +-#endif /* DCN2_1 */ + break; + #endif /* Family RV */ + +-- +2.17.1 + |