diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3637-drm-amd-display-Add-Renoir-hubbub-registers-list.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3637-drm-amd-display-Add-Renoir-hubbub-registers-list.patch | 204 |
1 files changed, 204 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3637-drm-amd-display-Add-Renoir-hubbub-registers-list.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3637-drm-amd-display-Add-Renoir-hubbub-registers-list.patch new file mode 100644 index 00000000..2510309a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3637-drm-amd-display-Add-Renoir-hubbub-registers-list.patch @@ -0,0 +1,204 @@ +From 672c8be27830ad644001ced55606725784bbdb15 Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 28 Aug 2019 10:22:02 -0500 +Subject: [PATCH 3637/4256] drm/amd/display: Add Renoir hubbub registers list + +These are the registers used to program the hubbub hw. + +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 73 +++++++++++++++++++ + .../drm/amd/display/dc/dcn20/dcn20_hubbub.h | 10 +++ + .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 35 +++++++++ + 3 files changed, 118 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +index c8ae3023fda2..69d903d68661 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +@@ -121,6 +121,26 @@ struct dcn_hubbub_registers { + uint32_t DCN_VM_AGP_BASE; + uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB; + uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A; ++ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B; ++ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C; ++ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D; ++ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A; ++ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B; ++ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C; ++ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D; ++ uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A; ++ uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B; ++ uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C; ++ uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D; ++ uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; ++ uint32_t DCHVM_CTRL0; ++ uint32_t DCHVM_MEM_CTRL; ++ uint32_t DCHVM_CLK_CTRL; ++ uint32_t DCHVM_RIOMMU_CTRL0; ++ uint32_t DCHVM_RIOMMU_STAT0; ++#endif + }; + + /* set field name */ +@@ -212,15 +232,68 @@ struct dcn_hubbub_registers { + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\ + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++#define HUBBUB_HVM_REG_FIELD_LIST(type) \ ++ type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\ ++ type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\ ++ type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\ ++ type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\ ++ type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ ++ type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ ++ type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\ ++ type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\ ++ type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\ ++ type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\ ++ type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\ ++ type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\ ++ type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\ ++ type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\ ++ type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\ ++ type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\ ++ type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\ ++ type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\ ++ type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\ ++ type HOSTVM_INIT_REQ; \ ++ type HVM_GPUVMRET_PWR_REQ_DIS; \ ++ type HVM_GPUVMRET_FORCE_REQ; \ ++ type HVM_GPUVMRET_POWER_STATUS; \ ++ type HVM_DISPCLK_R_GATE_DIS; \ ++ type HVM_DISPCLK_G_GATE_DIS; \ ++ type HVM_DCFCLK_R_GATE_DIS; \ ++ type HVM_DCFCLK_G_GATE_DIS; \ ++ type TR_REQ_REQCLKREQ_MODE; \ ++ type TW_RSP_COMPCLKREQ_MODE; \ ++ type HOSTVM_PREFETCH_REQ; \ ++ type HOSTVM_POWERSTATUS; \ ++ type RIOMMU_ACTIVE; \ ++ type HOSTVM_PREFETCH_DONE ++#endif + + struct dcn_hubbub_shift { + DCN_HUBBUB_REG_FIELD_LIST(uint8_t); + HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ HUBBUB_HVM_REG_FIELD_LIST(uint8_t); ++#endif + }; + + struct dcn_hubbub_mask { + DCN_HUBBUB_REG_FIELD_LIST(uint32_t); + HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ HUBBUB_HVM_REG_FIELD_LIST(uint32_t); ++#endif + }; + + struct dc; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h +index 0d0caa6de935..626117d3b4e9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h +@@ -29,6 +29,16 @@ + #include "dcn10/dcn10_hubbub.h" + #include "dcn20_vmid.h" + ++#define HUBBUB_REG_LIST_DCN20_COMMON()\ ++ HUBBUB_REG_LIST_DCN_COMMON(), \ ++ SR(DCHUBBUB_CRC_CTRL), \ ++ SR(DCN_VM_FB_LOCATION_BASE),\ ++ SR(DCN_VM_FB_LOCATION_TOP),\ ++ SR(DCN_VM_FB_OFFSET),\ ++ SR(DCN_VM_AGP_BOT),\ ++ SR(DCN_VM_AGP_TOP),\ ++ SR(DCN_VM_AGP_BASE) ++ + #define TO_DCN20_HUBBUB(hubbub)\ + container_of(hubbub, struct dcn20_hubbub, base) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +index c4ed8f1b9424..d5c8615af45e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +@@ -148,6 +148,17 @@ + uint32_t VMID_SETTINGS_0 + + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++#define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \ ++ DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \ ++ uint32_t FLIP_PARAMETERS_3;\ ++ uint32_t FLIP_PARAMETERS_4;\ ++ uint32_t FLIP_PARAMETERS_5;\ ++ uint32_t FLIP_PARAMETERS_6;\ ++ uint32_t VBLANK_PARAMETERS_5;\ ++ uint32_t VBLANK_PARAMETERS_6 ++#endif ++ + #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ + DCN_HUBP_REG_FIELD_BASE_LIST(type); \ + type DMDATA_ADDRESS_HIGH;\ +@@ -173,17 +184,41 @@ + type SURFACE_TRIPLE_BUFFER_ENABLE;\ + type VMID + ++#ifdef CONFIG_DRM_AMD_DC_DCN2_1 ++#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \ ++ DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\ ++ type REFCYC_PER_VM_GROUP_FLIP;\ ++ type REFCYC_PER_VM_REQ_FLIP;\ ++ type REFCYC_PER_VM_GROUP_VBLANK;\ ++ type REFCYC_PER_VM_REQ_VBLANK;\ ++ type REFCYC_PER_PTE_GROUP_FLIP_C; \ ++ type REFCYC_PER_META_CHUNK_FLIP_C; \ ++ type VM_GROUP_SIZE ++#endif ++ + + struct dcn_hubp2_registers { ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ DCN21_HUBP_REG_COMMON_VARIABLE_LIST; ++#else + DCN2_HUBP_REG_COMMON_VARIABLE_LIST; ++#endif + }; + + struct dcn_hubp2_shift { ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); ++#else + DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); ++#endif + }; + + struct dcn_hubp2_mask { ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); ++#else + DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); ++#endif + }; + + struct dcn20_hubp { +-- +2.17.1 + |