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path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch
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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch81
1 files changed, 81 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch
new file mode 100644
index 00000000..02e3cd3b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch
@@ -0,0 +1,81 @@
+From 2ad74e74f64fbd31111582fc37d6adc1b7154dae Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 10 Jul 2019 18:50:20 +0800
+Subject: [PATCH 3288/4256] drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc
+ header
+
+gc 10.1.2 introduced this new register
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../include/asic_reg/gc/gc_10_1_0_offset.h | 2 +
+ .../include/asic_reg/gc/gc_10_1_0_sh_mask.h | 39 +++++++++++++++++++
+ 2 files changed, 41 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+index 1dbc7cefbc05..075867d4b1da 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+@@ -10107,6 +10107,8 @@
+ #define mmCGTT_IA_CLK_CTRL_BASE_IDX 1
+ #define mmCGTT_WD_CLK_CTRL 0x5086
+ #define mmCGTT_WD_CLK_CTRL_BASE_IDX 1
++#define mmCGTT_GS_NGG_CLK_CTRL 0x5087
++#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
+ #define mmCGTT_PA_CLK_CTRL 0x5088
+ #define mmCGTT_PA_CLK_CTRL_BASE_IDX 1
+ #define mmCGTT_SC_CLK_CTRL0 0x5089
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+index 6c2a421fe8b7..e7db6f9f9c86 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+@@ -37872,6 +37872,45 @@
+ #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
+ #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L
+ #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
++//CGTT_GS_NGG_CLK_CTRL
++#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
++#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT 0x10
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
++#define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE__SHIFT 0x1c
++#define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE__SHIFT 0x1d
++#define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
++#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
++#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
++#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
++#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
++#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
++#define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE_MASK 0x10000000L
++#define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE_MASK 0x20000000L
++#define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L
++#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+ //CGTT_PA_CLK_CTRL
+ #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+ #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+--
+2.17.1
+