diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3217-drm-amdgpu-add-define-for-gfx-ras-subblock.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3217-drm-amdgpu-add-define-for-gfx-ras-subblock.patch | 470 |
1 files changed, 470 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3217-drm-amdgpu-add-define-for-gfx-ras-subblock.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3217-drm-amdgpu-add-define-for-gfx-ras-subblock.patch new file mode 100644 index 00000000..ab57e943 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3217-drm-amdgpu-add-define-for-gfx-ras-subblock.patch @@ -0,0 +1,470 @@ +From 915c10e08f420ab049cc46351589a34e886864dc Mon Sep 17 00:00:00 2001 +From: Dennis Li <Dennis.Li@amd.com> +Date: Fri, 19 Jul 2019 15:22:29 +0800 +Subject: [PATCH 3217/4256] drm/amdgpu: add define for gfx ras subblock + +Change-Id: Ib4b019b2bcbe6ef0b85ef170e7cf032bfa400553 +Signed-off-by: Dennis Li <Dennis.Li@amd.com> +Reviewed-by: Tao Zhou <tao.zhou1@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 230 ++++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 201 +++++++++++++++++++++ + 2 files changed, 431 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +index 2c86a5135ec9..2765f2dbb1e6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +@@ -52,6 +52,236 @@ enum amdgpu_ras_block { + #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST + #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) + ++enum amdgpu_ras_gfx_subblock { ++ /* CPC */ ++ AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, ++ AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = ++ AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, ++ AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, ++ AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, ++ AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, ++ AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, ++ AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, ++ AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, ++ AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = ++ AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, ++ /* CPF */ ++ AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = ++ AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, ++ AMDGPU_RAS_BLOCK__GFX_CPF_TAG, ++ AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, ++ /* CPG */ ++ AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = ++ AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, ++ AMDGPU_RAS_BLOCK__GFX_CPG_TAG, ++ AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, ++ /* GDS */ ++ AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, ++ AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, ++ AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, ++ AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, ++ AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = ++ AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, ++ /* SPI */ ++ AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, ++ /* SQ */ ++ AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, ++ AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, ++ AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, ++ AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, ++ /* SQC (3 ranges) */ ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, ++ /* SQC range 0 */ ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, ++ /* SQC range 1 */ ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, ++ /* SQC range 2 */ ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = ++ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = ++ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, ++ /* TA */ ++ AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = ++ AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, ++ AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, ++ AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, ++ AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, ++ AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, ++ /* TCA */ ++ AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = ++ AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = ++ AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, ++ /* TCC (5 sub-ranges) */ ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, ++ /* TCC range 0 */ ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, ++ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, ++ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, ++ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, ++ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, ++ AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, ++ AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = ++ AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, ++ /* TCC range 1 */ ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = ++ AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, ++ /* TCC range 2 */ ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, ++ AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, ++ AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, ++ AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, ++ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = ++ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, ++ /* TCC range 3 */ ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = ++ AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, ++ /* TCC range 4 */ ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, ++ AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = ++ AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = ++ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, ++ /* TCI */ ++ AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, ++ /* TCP */ ++ AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = ++ AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, ++ AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, ++ AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, ++ AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, ++ AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = ++ AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, ++ /* TD */ ++ AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = ++ AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, ++ AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, ++ AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, ++ /* EA (3 sub-ranges) */ ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, ++ /* EA range 0 */ ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, ++ AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, ++ AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = ++ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, ++ /* EA range 1 */ ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, ++ AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, ++ AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = ++ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, ++ /* EA range 2 */ ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, ++ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, ++ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = ++ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = ++ AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, ++ /* UTC VM L2 bank */ ++ AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, ++ /* UTC VM walker */ ++ AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, ++ /* UTC ATC L2 2MB cache */ ++ AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, ++ /* UTC ATC L2 4KB cache */ ++ AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, ++ AMDGPU_RAS_BLOCK__GFX_MAX ++}; ++ + enum amdgpu_ras_error_type { + AMDGPU_RAS_ERROR__NONE = 0, + AMDGPU_RAS_ERROR__PARITY = 1, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index b6569f221b51..e10bc8749333 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -117,6 +117,207 @@ MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); + #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c + #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 + ++enum ta_ras_gfx_subblock { ++ /*CPC*/ ++ TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, ++ TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, ++ TA_RAS_BLOCK__GFX_CPC_UCODE, ++ TA_RAS_BLOCK__GFX_DC_STATE_ME1, ++ TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, ++ TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, ++ TA_RAS_BLOCK__GFX_DC_STATE_ME2, ++ TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, ++ TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, ++ TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, ++ /* CPF*/ ++ TA_RAS_BLOCK__GFX_CPF_INDEX_START, ++ TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, ++ TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, ++ TA_RAS_BLOCK__GFX_CPF_TAG, ++ TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, ++ /* CPG*/ ++ TA_RAS_BLOCK__GFX_CPG_INDEX_START, ++ TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, ++ TA_RAS_BLOCK__GFX_CPG_DMA_TAG, ++ TA_RAS_BLOCK__GFX_CPG_TAG, ++ TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, ++ /* GDS*/ ++ TA_RAS_BLOCK__GFX_GDS_INDEX_START, ++ TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, ++ TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, ++ TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, ++ TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, ++ TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, ++ TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, ++ /* SPI*/ ++ TA_RAS_BLOCK__GFX_SPI_SR_MEM, ++ /* SQ*/ ++ TA_RAS_BLOCK__GFX_SQ_INDEX_START, ++ TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, ++ TA_RAS_BLOCK__GFX_SQ_LDS_D, ++ TA_RAS_BLOCK__GFX_SQ_LDS_I, ++ TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ ++ TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, ++ /* SQC (3 ranges)*/ ++ TA_RAS_BLOCK__GFX_SQC_INDEX_START, ++ /* SQC range 0*/ ++ TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, ++ TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = ++ TA_RAS_BLOCK__GFX_SQC_INDEX0_START, ++ TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, ++ TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, ++ TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, ++ TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, ++ TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, ++ TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, ++ TA_RAS_BLOCK__GFX_SQC_INDEX0_END = ++ TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, ++ /* SQC range 1*/ ++ TA_RAS_BLOCK__GFX_SQC_INDEX1_START, ++ TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = ++ TA_RAS_BLOCK__GFX_SQC_INDEX1_START, ++ TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, ++ TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, ++ TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, ++ TA_RAS_BLOCK__GFX_SQC_INDEX1_END = ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, ++ /* SQC range 2*/ ++ TA_RAS_BLOCK__GFX_SQC_INDEX2_START, ++ TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = ++ TA_RAS_BLOCK__GFX_SQC_INDEX2_START, ++ TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, ++ TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, ++ TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, ++ TA_RAS_BLOCK__GFX_SQC_INDEX2_END = ++ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, ++ TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, ++ /* TA*/ ++ TA_RAS_BLOCK__GFX_TA_INDEX_START, ++ TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, ++ TA_RAS_BLOCK__GFX_TA_FS_AFIFO, ++ TA_RAS_BLOCK__GFX_TA_FL_LFIFO, ++ TA_RAS_BLOCK__GFX_TA_FX_LFIFO, ++ TA_RAS_BLOCK__GFX_TA_FS_CFIFO, ++ TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, ++ /* TCA*/ ++ TA_RAS_BLOCK__GFX_TCA_INDEX_START, ++ TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, ++ TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, ++ TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, ++ /* TCC (5 sub-ranges)*/ ++ TA_RAS_BLOCK__GFX_TCC_INDEX_START, ++ /* TCC range 0*/ ++ TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, ++ TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, ++ TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, ++ TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, ++ TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, ++ TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, ++ TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, ++ TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, ++ TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, ++ TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, ++ /* TCC range 1*/ ++ TA_RAS_BLOCK__GFX_TCC_INDEX1_START, ++ TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, ++ TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, ++ TA_RAS_BLOCK__GFX_TCC_INDEX1_END = ++ TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, ++ /* TCC range 2*/ ++ TA_RAS_BLOCK__GFX_TCC_INDEX2_START, ++ TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, ++ TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, ++ TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, ++ TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, ++ TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, ++ TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, ++ TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, ++ TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, ++ TA_RAS_BLOCK__GFX_TCC_INDEX2_END = ++ TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, ++ /* TCC range 3*/ ++ TA_RAS_BLOCK__GFX_TCC_INDEX3_START, ++ TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, ++ TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, ++ TA_RAS_BLOCK__GFX_TCC_INDEX3_END = ++ TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, ++ /* TCC range 4*/ ++ TA_RAS_BLOCK__GFX_TCC_INDEX4_START, ++ TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = ++ TA_RAS_BLOCK__GFX_TCC_INDEX4_START, ++ TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, ++ TA_RAS_BLOCK__GFX_TCC_INDEX4_END = ++ TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, ++ TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, ++ /* TCI*/ ++ TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, ++ /* TCP*/ ++ TA_RAS_BLOCK__GFX_TCP_INDEX_START, ++ TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, ++ TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, ++ TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, ++ TA_RAS_BLOCK__GFX_TCP_VM_FIFO, ++ TA_RAS_BLOCK__GFX_TCP_DB_RAM, ++ TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, ++ TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, ++ TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, ++ /* TD*/ ++ TA_RAS_BLOCK__GFX_TD_INDEX_START, ++ TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, ++ TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, ++ TA_RAS_BLOCK__GFX_TD_CS_FIFO, ++ TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, ++ /* EA (3 sub-ranges)*/ ++ TA_RAS_BLOCK__GFX_EA_INDEX_START, ++ /* EA range 0*/ ++ TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, ++ TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, ++ TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, ++ TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, ++ TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, ++ TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, ++ TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, ++ TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, ++ TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, ++ TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, ++ /* EA range 1*/ ++ TA_RAS_BLOCK__GFX_EA_INDEX1_START, ++ TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, ++ TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, ++ TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, ++ TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, ++ TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, ++ TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, ++ TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, ++ TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, ++ /* EA range 2*/ ++ TA_RAS_BLOCK__GFX_EA_INDEX2_START, ++ TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, ++ TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, ++ TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, ++ TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, ++ TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, ++ TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, ++ /* UTC VM L2 bank*/ ++ TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, ++ /* UTC VM walker*/ ++ TA_RAS_BLOCK__UTC_VML2_WALKER, ++ /* UTC ATC L2 2MB cache*/ ++ TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, ++ /* UTC ATC L2 4KB cache*/ ++ TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, ++ TA_RAS_BLOCK__GFX_MAX ++}; + static const struct soc15_reg_golden golden_settings_gc_9_0[] = + { + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), +-- +2.17.1 + |