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-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3141-drm-amdgpu-Fix-amdgpu_display_supported_domains-logi.patch156
1 files changed, 156 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3141-drm-amdgpu-Fix-amdgpu_display_supported_domains-logi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3141-drm-amdgpu-Fix-amdgpu_display_supported_domains-logi.patch
new file mode 100644
index 00000000..45a9650c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3141-drm-amdgpu-Fix-amdgpu_display_supported_domains-logi.patch
@@ -0,0 +1,156 @@
+From fbeb9e7c8c1c0019193e95fa37eb1655a8fbdff4 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 26 Jul 2019 09:24:35 -0400
+Subject: [PATCH 3141/4256] drm/amdgpu: Fix amdgpu_display_supported_domains
+ logic.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add restriction to dissallow GTT domain if the relevant BO
+doesn't have USWC flag set to avoid the APU hang scenario.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 16 +++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 12 ++++++------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
+ 6 files changed, 22 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index f1df323f1da5..543f7a8f6c76 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -189,7 +189,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
+ }
+
+ if (!adev->enable_virtual_display) {
+- r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
++ r = amdgpu_bo_pin(new_abo,
++ amdgpu_display_supported_domains(adev, new_abo->flags));
+ if (unlikely(r != 0)) {
+ DRM_ERROR("failed to pin new abo buffer before flip\n");
+ goto unreserve;
+@@ -493,20 +494,25 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
+ .create_handle = drm_gem_fb_create_handle,
+ };
+
+-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
++uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
++ uint64_t bo_flags)
+ {
+ uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
+
+ #if defined(CONFIG_DRM_AMD_DC)
+ /*
+- * if amdgpu_bo_validate_uswc returns false it means that USWC mappings
++ * if amdgpu_bo_support_uswc returns false it means that USWC mappings
+ * is not supported for this board. But this mapping is required
+ * to avoid hang caused by placement of scanout BO in GTT on certain
+ * APUs. So force the BO placement to VRAM in case this architecture
+ * will not allow USWC mappings.
++ * Also, don't allow GTT domain if the BO doens't have USWC falg set.
+ */
+- if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&
+- adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) &&
++ if (adev->asic_type >= CHIP_CARRIZO &&
++ adev->asic_type <= CHIP_RAVEN &&
++ (adev->flags & AMD_IS_APU) &&
++ (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
++ amdgpu_bo_support_uswc(bo_flags) &&
+ amdgpu_device_asic_has_dc_support(adev->asic_type))
+ domain |= AMDGPU_GEM_DOMAIN_GTT;
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
+index ba7b9fb53864..4bed3ce31ae8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
+@@ -38,7 +38,8 @@
+ int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+ void amdgpu_display_update_priority(struct amdgpu_device *adev);
+-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev);
++uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
++ uint64_t bo_flags);
+ struct drm_framebuffer *
+ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
+ struct drm_file *file_priv,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+index b9d9b4e6c8bf..91f023c928dc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+@@ -301,7 +301,7 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
+ struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ struct ttm_operation_ctx ctx = { true, false };
+- u32 domain = amdgpu_display_supported_domains(adev);
++ u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
+ int ret;
+ bool reads = (direction == DMA_BIDIRECTIONAL ||
+ direction == DMA_FROM_DEVICE);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+index ce594ef5af4d..72ffe2aa0e6e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+@@ -132,21 +132,21 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
+ int aligned_size, size;
+ int height = mode_cmd->height;
+ u32 cpp;
++ u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
++ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
++ AMDGPU_GEM_CREATE_VRAM_CLEARED |
++ AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+
+ cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
+
+ /* need to align pitch with crtc limits */
+ mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
+ fb_tiled);
+- domain = amdgpu_display_supported_domains(adev);
++ domain = amdgpu_display_supported_domains(adev, flags);
+ height = ALIGN(mode_cmd->height, 8);
+ size = mode_cmd->pitches[0] * height;
+ aligned_size = ALIGN(size, PAGE_SIZE);
+- ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
+- AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+- AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+- AMDGPU_GEM_CREATE_VRAM_CLEARED |
+- AMDGPU_GEM_CREATE_CPU_GTT_USWC,
++ ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags,
+ ttm_bo_type_kernel, NULL, &gobj);
+ if (ret) {
+ pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+index 1b51194036b5..3642abd765b6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+@@ -847,7 +847,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
+ args->size = (u64)args->pitch * args->height;
+ args->size = ALIGN(args->size, PAGE_SIZE);
+ domain = amdgpu_bo_get_preferred_pin_domain(adev,
+- amdgpu_display_supported_domains(adev));
++ amdgpu_display_supported_domains(adev, flags));
+ r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
+ ttm_bo_type_device, NULL, &gobj);
+ if (r)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index a21d46ecc886..d981cbcd2ce2 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4437,7 +4437,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
+ return r;
+
+ if (plane->type != DRM_PLANE_TYPE_CURSOR)
+- domain = amdgpu_display_supported_domains(adev);
++ domain = amdgpu_display_supported_domains(adev, rbo->flags);
+ else
+ domain = AMDGPU_GEM_DOMAIN_VRAM;
+
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-26 05:39:59 +0000