diff options
Diffstat (limited to 'meta/recipes-devtools/gcc/gcc/0004-CVE-2021-35465.patch')
| -rw-r--r-- | meta/recipes-devtools/gcc/gcc/0004-CVE-2021-35465.patch | 304 |
1 files changed, 304 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc/0004-CVE-2021-35465.patch b/meta/recipes-devtools/gcc/gcc/0004-CVE-2021-35465.patch new file mode 100644 index 0000000000..9f7a38ed2e --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc/0004-CVE-2021-35465.patch @@ -0,0 +1,304 @@ +From 809330ab8450261e05919b472783bf15e4b000f7 Mon Sep 17 00:00:00 2001 +From: Richard Earnshaw <rearnsha@arm.com> +Date: Tue, 6 Jul 2021 15:10:18 +0100 +Subject: [PATCH] arm: Add tests for VLLDM mitigation [PR102035] + +New tests for the erratum mitigation. + +gcc/testsuite: + PR target/102035 + * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c: New test. + * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c: Likewise. + +CVE: CVE-2021-35465 +Upstream-Status: Backport[https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=809330ab8450261e05919b472783bf15e4b000f7] +Signed-off-by: Pgowda <pgowda.cve@gmail.com> + +--- + .../arm/cmse/mainline/8_1m/soft/cmse-13a.c | 31 +++++++++++++++++++ + .../arm/cmse/mainline/8_1m/soft/cmse-7a.c | 28 +++++++++++++++++ + .../arm/cmse/mainline/8_1m/soft/cmse-8a.c | 30 ++++++++++++++++++ + .../cmse/mainline/8_1m/softfp-sp/cmse-7a.c | 27 ++++++++++++++++ + .../cmse/mainline/8_1m/softfp-sp/cmse-8a.c | 29 +++++++++++++++++ + .../arm/cmse/mainline/8_1m/softfp/cmse-13a.c | 30 ++++++++++++++++++ + .../arm/cmse/mainline/8_1m/softfp/cmse-7a.c | 27 ++++++++++++++++ + .../arm/cmse/mainline/8_1m/softfp/cmse-8a.c | 29 +++++++++++++++++ + 8 files changed, 231 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c + create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c + create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c + create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c + create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c + create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c + create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c + create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c + +diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c +--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c 1969-12-31 16:00:00.000000000 -0800 ++++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c 2021-11-11 20:38:44.286766084 -0800 +@@ -0,0 +1,31 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mcmse -mfloat-abi=soft -mfix-cmse-cve-2021-35465" } */ ++/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */ ++ ++#include "../../../cmse-13.x" ++ ++/* Checks for saving and clearing prior to function call. */ ++/* Shift on the same register as blxns. */ ++/* { dg-final { scan-assembler "lsrs\t(r\[1,4-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "lsls\t(r\[1,4-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ ++/* { dg-final { scan-assembler-not "mov\tr2, r4" } } */ ++/* { dg-final { scan-assembler-not "mov\tr3, r4" } } */ ++/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler "vlstm\tsp" } } */ ++/* Check the right registers are cleared and none appears twice. */ ++/* { dg-final { scan-assembler "clrm\t\{(r1, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ ++/* Check that the right number of registers is cleared and thus only one ++ register is missing. */ ++/* { dg-final { scan-assembler "clrm\t\{((r\[1,4-9\]|r10|fp|ip), ){9}APSR\}" } } */ ++/* Check that no cleared register is used for blxns. */ ++/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[1,4-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ ++/* Check for v8.1-m variant of erratum work-around. */ ++/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ ++/* { dg-final { scan-assembler "vlldm\tsp" } } */ ++/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler-not "vmov" } } */ ++/* { dg-final { scan-assembler-not "vmsr" } } */ ++ ++/* Now we check that we use the correct intrinsic to call. */ ++/* { dg-final { scan-assembler "blxns" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c +--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c 1969-12-31 16:00:00.000000000 -0800 ++++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c 2021-11-11 20:38:44.286766084 -0800 +@@ -0,0 +1,28 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mcmse -mfloat-abi=soft -mfix-cmse-cve-2021-35465" } */ ++/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */ ++ ++#include "../../../cmse-7.x" ++ ++/* Checks for saving and clearing prior to function call. */ ++/* Shift on the same register as blxns. */ ++/* { dg-final { scan-assembler "lsrs\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "lsls\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler "vlstm\tsp" } } */ ++/* Check the right registers are cleared and none appears twice. */ ++/* { dg-final { scan-assembler "clrm\t\{(r0, )?(r1, )?(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ ++/* Check that the right number of registers is cleared and thus only one ++ register is missing. */ ++/* { dg-final { scan-assembler "clrm\t\{((r\[0-9\]|r10|fp|ip), ){12}APSR\}" } } */ ++/* Check that no cleared register is used for blxns. */ ++/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[0-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ ++/* Check for v8.1-m variant of erratum work-around. */ ++/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ ++/* { dg-final { scan-assembler "vlldm\tsp" } } */ ++/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler-not "vmov" } } */ ++/* { dg-final { scan-assembler-not "vmsr" } } */ ++ ++/* Now we check that we use the correct intrinsic to call. */ ++/* { dg-final { scan-assembler "blxns" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c +--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c 1969-12-31 16:00:00.000000000 -0800 ++++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c 2021-11-11 20:38:44.286766084 -0800 +@@ -0,0 +1,30 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mcmse -mfloat-abi=soft -mfix-cmse-cve-2021-35465" } */ ++/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */ ++ ++#include "../../../cmse-8.x" ++ ++/* Checks for saving and clearing prior to function call. */ ++/* Shift on the same register as blxns. */ ++/* { dg-final { scan-assembler "lsrs\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "lsls\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ ++/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */ ++/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler "vlstm\tsp" } } */ ++/* Check the right registers are cleared and none appears twice. */ ++/* { dg-final { scan-assembler "clrm\t\{(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ ++/* Check that the right number of registers is cleared and thus only one ++ register is missing. */ ++/* { dg-final { scan-assembler "clrm\t\{((r\[2-9\]|r10|fp|ip), ){10}APSR\}" } } */ ++/* Check that no cleared register is used for blxns. */ ++/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[2-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ ++/* Check for v8.1-m variant of erratum work-around. */ ++/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ ++/* { dg-final { scan-assembler "vlldm\tsp" } } */ ++/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler-not "vmov" } } */ ++/* { dg-final { scan-assembler-not "vmsr" } } */ ++ ++/* Now we check that we use the correct intrinsic to call. */ ++/* { dg-final { scan-assembler "blxns" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c +--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c 1969-12-31 16:00:00.000000000 -0800 ++++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c 2021-11-11 20:38:44.286766084 -0800 +@@ -0,0 +1,30 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16 -mfix-cmse-cve-2021-35465" } */ ++/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ ++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */ ++ ++#include "../../../cmse-13.x" ++ ++/* Checks for saving and clearing prior to function call. */ ++/* Shift on the same register as blxns. */ ++/* { dg-final { scan-assembler "lsrs\t(r\[1,4-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "lsls\t(r\[1,4-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ ++/* { dg-final { scan-assembler-not "mov\tr2, r4" } } */ ++/* { dg-final { scan-assembler-not "mov\tr3, r4" } } */ ++/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler "vlstm\tsp" } } */ ++/* Check the right registers are cleared and none appears twice. */ ++/* { dg-final { scan-assembler "clrm\t\{(r1, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ ++/* Check that the right number of registers is cleared and thus only one ++ register is missing. */ ++/* { dg-final { scan-assembler "clrm\t\{((r\[1,4-9\]|r10|fp|ip), ){9}APSR\}" } } */ ++/* Check that no cleared register is used for blxns. */ ++/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[1,4-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ ++/* Check for v8.1-m variant of erratum work-around. */ ++/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ ++/* { dg-final { scan-assembler "vlldm\tsp" } } */ ++/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++ ++/* Now we check that we use the correct intrinsic to call. */ ++/* { dg-final { scan-assembler "blxns" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c +--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c 1969-12-31 16:00:00.000000000 -0800 ++++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c 2021-11-11 20:38:44.286766084 -0800 +@@ -0,0 +1,27 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16 -mfix-cmse-cve-2021-35465" } */ ++/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ ++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */ ++ ++#include "../../../cmse-7.x" ++ ++/* Checks for saving and clearing prior to function call. */ ++/* Shift on the same register as blxns. */ ++/* { dg-final { scan-assembler "lsrs\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "lsls\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler "vlstm\tsp" } } */ ++/* Check the right registers are cleared and none appears twice. */ ++/* { dg-final { scan-assembler "clrm\t\{(r0, )?(r1, )?(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ ++/* Check that the right number of registers is cleared and thus only one ++ register is missing. */ ++/* { dg-final { scan-assembler "clrm\t\{((r\[0-9\]|r10|fp|ip), ){12}APSR\}" } } */ ++/* Check that no cleared register is used for blxns. */ ++/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[0-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ ++/* Check for v8.1-m variant of erratum work-around. */ ++/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ ++/* { dg-final { scan-assembler "vlldm\tsp" } } */ ++/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++ ++/* Now we check that we use the correct intrinsic to call. */ ++/* { dg-final { scan-assembler "blxns" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c +--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c 1969-12-31 16:00:00.000000000 -0800 ++++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c 2021-11-11 20:38:44.290766017 -0800 +@@ -0,0 +1,29 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16 -mfix-cmse-cve-2021-35465" } */ ++/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ ++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */ ++ ++#include "../../../cmse-8.x" ++ ++/* Checks for saving and clearing prior to function call. */ ++/* Shift on the same register as blxns. */ ++/* { dg-final { scan-assembler "lsrs\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "lsls\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ ++/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */ ++/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler "vlstm\tsp" } } */ ++/* Check the right registers are cleared and none appears twice. */ ++/* { dg-final { scan-assembler "clrm\t\{(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ ++/* Check that the right number of registers is cleared and thus only one ++ register is missing. */ ++/* { dg-final { scan-assembler "clrm\t\{((r\[2-9\]|r10|fp|ip), ){10}APSR\}" } } */ ++/* Check that no cleared register is used for blxns. */ ++/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[2-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ ++/* Check for v8.1-m variant of erratum work-around. */ ++/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ ++/* { dg-final { scan-assembler "vlldm\tsp" } } */ ++/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++ ++/* Now we check that we use the correct intrinsic to call. */ ++/* { dg-final { scan-assembler "blxns" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c +--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c 1969-12-31 16:00:00.000000000 -0800 ++++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c 2021-11-11 20:38:44.286766084 -0800 +@@ -0,0 +1,27 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16 -mfix-cmse-cve-2021-35465" } */ ++/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ ++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */ ++ ++#include "../../../cmse-7.x" ++ ++/* Checks for saving and clearing prior to function call. */ ++/* Shift on the same register as blxns. */ ++/* { dg-final { scan-assembler "lsrs\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "lsls\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler "vlstm\tsp" } } */ ++/* Check the right registers are cleared and none appears twice. */ ++/* { dg-final { scan-assembler "clrm\t\{(r0, )?(r1, )?(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ ++/* Check that the right number of registers is cleared and thus only one ++ register is missing. */ ++/* { dg-final { scan-assembler "clrm\t\{((r\[0-9\]|r10|fp|ip), ){12}APSR\}" } } */ ++/* Check that no cleared register is used for blxns. */ ++/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[0-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ ++/* Check for v8.1-m variant of erratum work-around. */ ++/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ ++/* { dg-final { scan-assembler "vlldm\tsp" } } */ ++/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++ ++/* Now we check that we use the correct intrinsic to call. */ ++/* { dg-final { scan-assembler "blxns" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c +--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c 1969-12-31 16:00:00.000000000 -0800 ++++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c 2021-11-11 20:38:44.286766084 -0800 +@@ -0,0 +1,29 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16 -mfix-cmse-cve-2021-35465" } */ ++/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ ++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */ ++ ++#include "../../../cmse-8.x" ++ ++/* Checks for saving and clearing prior to function call. */ ++/* Shift on the same register as blxns. */ ++/* { dg-final { scan-assembler "lsrs\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler "lsls\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ ++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ ++/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */ ++/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++/* { dg-final { scan-assembler "vlstm\tsp" } } */ ++/* Check the right registers are cleared and none appears twice. */ ++/* { dg-final { scan-assembler "clrm\t\{(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ ++/* Check that the right number of registers is cleared and thus only one ++ register is missing. */ ++/* { dg-final { scan-assembler "clrm\t\{((r\[2-9\]|r10|fp|ip), ){10}APSR\}" } } */ ++/* Check that no cleared register is used for blxns. */ ++/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[2-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ ++/* Check for v8.1-m variant of erratum work-around. */ ++/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ ++/* { dg-final { scan-assembler "vlldm\tsp" } } */ ++/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ ++ ++/* Now we check that we use the correct intrinsic to call. */ ++/* { dg-final { scan-assembler "blxns" } } */ |