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From 9e45ca7bd65fe327e01e93d3c539c9d8cf049b79 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Fri, 3 Aug 2018 15:41:39 +0530
Subject: [PATCH 42/54] re-arrangement of the compare branches
---
gcc/config/microblaze/microblaze.c | 28 ++-----
gcc/config/microblaze/microblaze.md | 141 +++++++++++++++++-------------------
2 files changed, 73 insertions(+), 96 deletions(-)
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index ba7ade4..fab79d9 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -3695,11 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
{
comp_reg = cmp_op0;
condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
- if (mode == Pmode)
- emit_jump_insn (gen_condjump (condition, label1));
- else
- emit_jump_insn (gen_long_condjump (condition, label1));
-
+ emit_jump_insn (gen_condjump (condition, label1));
}
else if (code == EQ || code == NE)
@@ -3710,10 +3706,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
else
emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
- if (mode == SImode)
- emit_jump_insn (gen_condjump (condition, label1));
- else
- emit_jump_insn (gen_long_condjump (condition, label1));
+ emit_jump_insn (gen_condjump (condition, label1));
}
else
{
@@ -3746,10 +3739,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
comp_reg = cmp_op0;
condition = gen_rtx_fmt_ee (signed_condition (code),
mode, comp_reg, const0_rtx);
- if (mode == SImode)
- emit_jump_insn (gen_condjump (condition, label1));
- else
- emit_jump_insn (gen_long_condjump (condition, label1));
+ emit_jump_insn (gen_condjump (condition, label1));
}
else if (code == EQ)
{
@@ -3764,10 +3754,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
cmp_op1));
}
condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
- if (mode == SImode)
- emit_jump_insn (gen_condjump (condition, label1));
- else
- emit_jump_insn (gen_long_condjump (condition, label1));
+ emit_jump_insn (gen_condjump (condition, label1));
}
else if (code == NE)
@@ -3783,10 +3770,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
cmp_op1));
}
condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
- if (mode == SImode)
- emit_jump_insn (gen_condjump (condition, label1));
- else
- emit_jump_insn (gen_long_condjump (condition, label1));
+ emit_jump_insn (gen_condjump (condition, label1));
}
else
{
@@ -3828,7 +3812,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
- emit_jump_insn (gen_long_condjump (condition, operands[3]));
+ emit_jump_insn (gen_condjump (condition, operands[3]));
}
/* Implement TARGET_FRAME_POINTER_REQUIRED. */
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 0f41ac6..2213d6e 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -2268,7 +2268,27 @@ else
(label_ref (match_operand 1))
(pc)))])
-(define_insn "branch_zero64"
+(define_insn "branch_zero_64"
+ [(set (pc)
+ (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
+ [(match_operand:SI 1 "register_operand" "d")
+ (const_int 0)])
+ (match_operand:SI 2 "pc_or_label_operand" "")
+ (match_operand:SI 3 "pc_or_label_operand" "")))
+ ]
+ "TARGET_MB_64"
+ {
+ if (operands[3] == pc_rtx)
+ return "bea%C0i%?\t%z1,%2";
+ else
+ return "bea%N0i%?\t%z1,%3";
+ }
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")
+ (set_attr "length" "4")]
+)
+
+(define_insn "long_branch_zero"
[(set (pc)
(if_then_else (match_operator 0 "ordered_comparison_operator"
[(match_operand 1 "register_operand" "d")
@@ -2279,9 +2299,9 @@ else
"TARGET_MB_64"
{
if (operands[3] == pc_rtx)
- return "bea%C0i%?\t%z1,%2";
+ return "beal%C0i%?\t%z1,%2";
else
- return "bea%N0i%?\t%z1,%3";
+ return "beal%N0i%?\t%z1,%3";
}
[(set_attr "type" "branch")
(set_attr "mode" "none")
@@ -2310,9 +2330,9 @@ else
(define_insn "branch_compare64"
[(set (pc)
- (if_then_else (match_operator 0 "cmp_op"
- [(match_operand 1 "register_operand" "d")
- (match_operand 2 "register_operand" "d")
+ (if_then_else (match_operator:SI 0 "cmp_op"
+ [(match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")
])
(label_ref (match_operand 3))
(pc)))
@@ -2349,6 +2369,47 @@ else
(set_attr "length" "12")]
)
+(define_insn "long_branch_compare"
+ [(set (pc)
+ (if_then_else (match_operator 0 "cmp_op"
+ [(match_operand 1 "register_operand" "d")
+ (match_operand 2 "register_operand" "d")
+ ])
+ (label_ref (match_operand 3))
+ (pc)))
+ (clobber(reg:DI R_TMP))]
+ "TARGET_MB_64"
+ {
+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
+ enum rtx_code code = GET_CODE (operands[0]);
+
+ if (code == GT || code == LE)
+ {
+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
+ code = swap_condition (code);
+ }
+ else if (code == GTU || code == LEU)
+ {
+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
+ code = swap_condition (code);
+ }
+ else if (code == GE || code == LT)
+ {
+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
+ }
+ else if (code == GEU || code == LTU)
+ {
+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
+ }
+
+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
+ return "beal%C0i%?\tr18,%3";
+ }
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")
+ (set_attr "length" "12")]
+)
+
(define_insn "branch_compare"
[(set (pc)
(if_then_else (match_operator:SI 0 "cmp_op"
@@ -2431,74 +2492,6 @@ else
})
-;; Used to implement comparison instructions
-(define_expand "long_condjump"
- [(set (pc)
- (if_then_else (match_operand 0)
- (label_ref (match_operand 1))
- (pc)))])
-
-(define_insn "long_branch_zero"
- [(set (pc)
- (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
- [(match_operand:DI 1 "register_operand" "d")
- (const_int 0)])
- (match_operand:DI 2 "pc_or_label_operand" "")
- (match_operand:DI 3 "pc_or_label_operand" "")))
- ]
- "TARGET_MB_64"
- {
- if (operands[3] == pc_rtx)
- return "beal%C0i%?\t%z1,%2";
- else
- return "beal%N0i%?\t%z1,%3";
- }
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "4")]
-)
-
-(define_insn "long_branch_compare"
- [(set (pc)
- (if_then_else (match_operator:DI 0 "cmp_op"
- [(match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")
- ])
- (label_ref (match_operand 3))
- (pc)))
- (clobber(reg:DI R_TMP))]
- "TARGET_MB_64"
- {
- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
- enum rtx_code code = GET_CODE (operands[0]);
-
- if (code == GT || code == LE)
- {
- output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
- code = swap_condition (code);
- }
- else if (code == GTU || code == LEU)
- {
- output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
- code = swap_condition (code);
- }
- else if (code == GE || code == LT)
- {
- output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
- }
- else if (code == GEU || code == LTU)
- {
- output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
- }
-
- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
- return "beal%C0i%?\tr18,%3";
- }
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "12")]
-)
-
;;----------------------------------------------------------------
;; Unconditional branches
;;----------------------------------------------------------------
--
2.7.4
|
