From 0b2061ac7706df97da3e8b3c01c6a5cfc504c16e Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati Date: Sat, 26 Aug 2017 19:21:35 -0700 Subject: [PATCH] MicroBlaze add optimized lshrsi3 When barrel shifter is not present Add optimized lshrsi3 When barrel shifter is not present, the immediate value is greater than #5 and optimization is -OS, the compiler will generate shift operation using loop. Changelog 2013-11-26 David Holsgrove * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn ChangeLog/testsuite 2014-02-12 David Holsgrove * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. Signed-off-by: Nagaraju Mekala Signed-off-by: David Holsgrove Signed-off-by: Mahesh Bodapati Signed-off-by: Manjukumar Matha Upstream-Status: Pending --- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ .../gcc.target/microblaze/others/lshrsi_Os_1.c | 13 +++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index 8c0a97e032..abbe97c15f 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -1615,6 +1615,27 @@ (set_attr "length" "4,4")] ) +(define_insn "*lshrsi3_with_size_opt" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "(INTVAL (operands[2]) > 5 && optimize_size)" + { + operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + + output_asm_insn ("ori\t%3,r0,%2", operands); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,%1,r0", operands); + + output_asm_insn ("addik\t%3,%3,-1", operands); + output_asm_insn ("bneid\t%3,.-4", operands); + return "srl\t%0,%0"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "20")] +) + (define_insn "*lshrsi_inline" [(set (match_operand:SI 0 "register_operand" "=&d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c new file mode 100644 index 0000000000..32a3be7c76 --- /dev/null +++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c @@ -0,0 +1,13 @@ +/* { dg-options "-Os -mno-xl-barrel-shift" } */ + +void testfunc(void) +{ + unsigned volatile int z = 8192; + z >>= 8; +} +/* { dg-final { scan-assembler-not "\bsrli" } } */ +/* { dg-final { scan-assembler "\ori\tr18,r0" } } */ +/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */ +/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */ +/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */ +/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */ -- 2.14.2