/*
 * microZed DTS for generic boot.
 */

/ {
	model = "Avnet microZed";
	chosen {
		bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/ram rw";
		linux,stdout-path = "/axi@0/serial@e0001000";
	} ;
	ps7_ddr_0: memory@0 {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	} ;
	ps7_axi_interconnect_0: amba@0 {
		ps7_ethernet_0: ps7-ethernet@e000b000 {
			phy-handle = <&phy0>;
			phy-mode = "rgmii-id";
			phy0: phy@0 {
				compatible = "marvell,88e1512";
				device_type = "ethernet-phy";
				reg = <0>;
			} ;
		} ;
		ps7_qspi_0: ps7-qspi@e000d000 {
			flash@0 {
				compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor";
				reg = <0x0>;
				spi-max-frequency = <50000000>;
				#address-cells = <1>;
				#size-cells = <1>;
				partition@qspi-fsbl-uboot {
					label = "qspi-fsbl-uboot";
					reg = <0x0 0x100000>;
				};
				partition@qspi-linux {
					label = "qspi-linux";
					reg = <0x100000 0x500000>;
				};
				partition@qspi-device-tree {
					label = "qspi-device-tree";
					reg = <0x600000 0x20000>;
				};
				partition@qspi-rootfs {
					label = "qspi-rootfs";
					reg = <0x620000 0x5E0000>;
				};
				partition@qspi-bitstream {
					label = "qspi-bitstream";
					reg = <0xC00000 0x400000>;
				};
			};
		} ;
		ps7_usb_0: ps7-usb@e0002000 {
			xlnx,phy-reset-gpio = <&ps7_gpio_0 7 0>; /* MIO USB PHY Reset */
			usb-phy = <&usb0_phy>;
		} ;

		/* Disabled Devices */
		ps7_sd_1: ps7-sdio@e0101000 { compatible = "invalid"; };
		ps7_uart_0: serial@e0000000 { compatible = "invalid"; };
		ps7_ethernet_1: ps7-ethernet@e000c000 { compatible = "invalid"; };
		ps7_i2c_0: ps7-i2c@e0004000 { compatible = "invalid"; };
		ps7_i2c_1: ps7-i2c@e0005000 { compatible = "invalid"; };
		ps7_wdt_0: ps7-wdt@f8005000 { compatible = "invalid"; };
		ps7_can_0: ps7-can@e0008000 { compatible = "invalid"; };
		ps7_can_1: ps7-can@e0009000 { compatible = "invalid"; };
		ps7_usb_1: ps7-usb@e0003000 { compatible = "invalid"; };
	} ;

	usb0_phy: usb-phy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		reset-gpios = <&ps7_gpio_0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */
	} ;
} ;