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Update components for 2019.1 release
- u-boot-xlnx
- linux-xlnx
- arm-trusted-firmware
- QEMU
- recipes-multimedia/vcu
- xrt and zocl
- pmu-firmware
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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configuration
Move the appropriate backend code for the ZynqMP FPGA configuration from
the interface subdirectory of the xilfpga library into the src directory
so that the files are picked up by the Makefile. Otherwise the FPGA
configuration code is non-functional.
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Tested-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Andreas Galauner <andreas@galauner.de>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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This patch ports the pmu-firmware recipe from meta-xilinx-bsp to be used
with the standalone/baremetal toolchain and also upgrades it to the
latest release at this point.
The recipe was trimmed down, and a few changes had to be made to make it
compatible with the baremetal layer, DEPENDS, pass include dir, license
and such.
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Modifies the CC variable so the Xilinx linker is found correctly when
building newlib and libgloss.
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Upstream gcc expects to have libxil available when linking, we can get
the required symbols (weak) from libgloss.
We copy libgloss as libxil to comply with upstream behavior and avoid
linking errors.
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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components
This layer is meant to augment Yocto/OE functionality to provide a
toolchain to build standalone components for Xilinx architectures.
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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