diff options
Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch')
| -rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch new file mode 100644 index 00000000..e340c506 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch @@ -0,0 +1,36 @@ +From 732b5a44a0a032da5ebb775b5df2ee2a36af988f Mon Sep 17 00:00:00 2001 +From: Nathan Rossi <nathan@nathanrossi.com> +Date: Sun, 5 Nov 2017 22:17:39 +1000 +Subject: [PATCH] MicroBlaze fix mask for barrel shift instructions + +As of v10.0 the bsi (bslli/bsrai/bsrli/bsefi/bsifi) instructions have +bits 16 and 17 defined as 'Insert' and 'Extract' respectively to support +bit field insert/extract operations. For the bslli/bsrai/bsrli +instructions these bits must be 0, as such update the opcode mask so +that the bslli/bsrai/bsrli instructions do not also match the bsefi and +bsifi instructions. + +Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> +Upstream-Status: Pending + +--- + opcodes/microblaze-opc.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 4bc400a..9482d81 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -161,9 +161,9 @@ struct op_code_struct + {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, + {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, + {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, +- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, +- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, +- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, ++ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst }, ++ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst }, ++ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst }, + {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, + {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, + {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, |