diff options
67 files changed, 5995 insertions, 845 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch deleted file mode 100644 index 93af6514..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 12cd383fbef719cc1a84cc80ff171073409a8557 Mon Sep 17 00:00:00 2001 -From: eager <eager@138bc75d-0d04-0410-961f-82ee72b054a4> -Date: Sat, 27 May 2017 18:29:40 +0000 -Subject: [PATCH] Revert: 2016-01-21 Ajit Agarwal - <ajitkum@xilinx.com> - - See https://gcc.gnu.org/ml/gcc/2017-05/msg00221.html. - - * config/microblaze/microblaze.h - (FIXED_REGISTERS): Update in macro. - (CALL_USED_REGISTERS): Update in macro. - -git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248540 138bc75d-0d04-0410-961f-82ee72b054a4 -Upstream-Status: Backport [from post gcc-7] ---- - gcc/config/microblaze/microblaze.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 66e4ef5c3d..2c9ece1d6c 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -269,14 +269,14 @@ extern enum pipeline_type microblaze_pipe; - #define FIXED_REGISTERS \ - { \ - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ -- 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 1, 1, 1 \ - } - - #define CALL_USED_REGISTERS \ - { \ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ -- 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 1, 1, 1 \ - } - #define GP_REG_FIRST 0 --- -2.14.2 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch deleted file mode 100644 index 42bfd3c1..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch +++ /dev/null @@ -1,32 +0,0 @@ -From f17cdebf4e0defaefce927176ddeb9717de073d2 Mon Sep 17 00:00:00 2001 -From: law <law@138bc75d-0d04-0410-961f-82ee72b054a4> -Date: Mon, 15 Jan 2018 06:02:19 +0000 -Subject: [PATCH] PR target/83013 - - * config/microblaze/microblaze.c (microblaze_asm_output_ident): - Use .pushsection/.popsection. - -git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@256681 138bc75d-0d04-0410-961f-82ee72b054a4 -Upstream-Status: Backport [backport from trunk pre-release v8] ---- - gcc/config/microblaze/microblaze.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index d0f86fd460..a98aca1235 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3371,7 +3371,9 @@ microblaze_asm_output_ident (const char *string) - else - section_asm_op = READONLY_DATA_SECTION_ASM_OP; - -- buf = ACONCAT ((section_asm_op, "\n\t.ascii \"", string, "\\0\"\n", NULL)); -+ buf = ACONCAT (("\t.pushsection", section_asm_op, -+ "\n\t.ascii \"", string, "\\0\"\n", -+ "\t.popsection\n", NULL)); - symtab->finalize_toplevel_asm (build_string (strlen (buf), buf)); - } - --- -2.15.1 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch deleted file mode 100644 index c0a427ea..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch +++ /dev/null @@ -1,36 +0,0 @@ -From ab2cb6320138c173b20fee8ce6e8d4afa4696384 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:16 -0700 -Subject: [PATCH] dejagnu static testing on qemu, suppress warnings - -For dejagnu static testing on qemu, suppress warnings about multiple -definitions from the test function and libc in line with method used by -powerpc. Dynamic linking and using a qemu binary which understands -sysroot resolves all test failures with builtins - -Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -index ba16b09c41..ada149912b 100644 ---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -@@ -48,6 +48,10 @@ if { [istarget *-*-eabi*] - lappend additional_flags "-Wl,--allow-multiple-definition" - } - -+if [istarget "microblaze*-*-linux*"] { -+ lappend additional_flags "-Wl,-zmuldefs" -+} -+ - foreach src [lsort [find $srcdir/$subdir *.c]] { - if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { - c-torture-execute [list $src \ --- -2.14.2 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch deleted file mode 100644 index 464f59e3..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 1a9dcdb578452ecd53e0aec65fe6279233218778 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:26 -0700 -Subject: [PATCH] Fix the Microblaze crash with msmall-divides flag - -Fix the Microblaze crash with msmall-divides flag Compiler is crashing -when we use msmall-divides and mxl-barrel-shift flag. This is because -when use above flags microblaze_expand_divide function will be called -for division operation. In microblaze_expand_divide function we are -using sub_reg but MicroBlaze doesn't have subreg register due to this -compiler was crashing. Changed the logic to avoid sub_reg call - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index bba6983b65..15080db539 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3527,8 +3527,7 @@ microblaze_expand_divide (rtx operands[]) - mem_rtx = gen_rtx_MEM (QImode, - gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); - -- insn = emit_insn (gen_movqi (regqi, mem_rtx)); -- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); -+ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); - jump = emit_jump_insn_after (gen_jump (div_end_label), insn); - JUMP_LABEL (jump) = div_end_label; - LABEL_NUSES (div_end_label) = 1; --- -2.14.2 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch deleted file mode 100644 index 4041e11f..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 25b161dd222311cca0e6ab46b7f3be444bd4bbe8 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:32 -0700 -Subject: [PATCH] Disable fivopts by default Turn off ivopts by default. - Interferes with cse. - -Changelog - -2013-03-18 Edgar E. Iglesias <edgar.iglesias@xilinx.com> - - * gcc/common/config/microblaze/microblaze-common.c - (microblaze_option_optimization_table): Disable fivopts by default. - -Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> -Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/common/config/microblaze/microblaze-common.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c -index 4975663305..8ddc4c3cbe 100644 ---- a/gcc/common/config/microblaze/microblaze-common.c -+++ b/gcc/common/config/microblaze/microblaze-common.c -@@ -27,6 +27,8 @@ - /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ - static const struct default_options microblaze_option_optimization_table[] = - { -+ /* Turn off ivopts by default. It messes up cse. */ -+ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, - { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, - { OPT_LEVELS_NONE, 0, NULL, 0 } - }; --- -2.14.2 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch deleted file mode 100644 index 00e79b93..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 1b9bd76840fc1e67770a23c58bf18a24a25eb2b9 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:36 -0700 -Subject: [PATCH] Modified MicroBlaze trap instruction - -Modified trap instruction The instruction was wrongly written to brki -r0,-1 it should be bri r0. Modified with the correct instruction - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.md | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index abbe97c15f..a3954a24b6 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2343,7 +2343,7 @@ - (define_insn "trap" - [(trap_if (const_int 1) (const_int 0))] - "" -- "brki\tr0,-1" -+ "bri\t0" - [(set_attr "type" "trap")] - ) - --- -2.14.2 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch deleted file mode 100644 index 6de17024..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch +++ /dev/null @@ -1,64 +0,0 @@ -From cf85f09a0fade1e7827828a3dc9a526c212f3be7 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:39 -0700 -Subject: [PATCH] Inline Expansion of fsqrt builtin - -Inline Expansion of fsqrt builtin. The changes are made in the patch for -the inline expansion of the fsqrt builtin with fqrt instruction. The -sqrt math function takes double as argument and return double as -argument. The pattern is selected while expanding the unary op through -expand_unop which passes DFmode and the DFmode pattern was not there -returning zero. Thus the sqrt math function is not inlined and expanded. -The pattern with DFmode argument is added. Also the source and -destination argument is not same the DF through two different -consecutive registers with lower 32 bit is the argument passed to sqrt -and the higher 32 bit is zero. If the source and destinations are -different the DFmode 64 bits registers is not set properly giving the -problem in runtime. Such changes are taken care in the implementation of -the pattern for DFmode for inline expansion of the sqrt. - -ChangeLog: - -2015-06-16 Ajit Agarwal <ajitkum@xilinx.com> - Nagaraju Mekala <nagaraju.mekala@xilinx.com> - - * config/microblaze/microblaze.md (sqrtdf2): New - pattern. - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index a3954a24b6..13f8803428 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -449,6 +449,20 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+(define_insn "sqrtdf2" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] -+ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" -+ { -+ if (REGNO (operands[0]) == REGNO (operands[1])) -+ return "fsqrt\t%0,%1"; -+ else -+ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; -+ } -+ [(set_attr "type" "fsqrt") -+ (set_attr "mode" "SF") -+ (set_attr "length" "4")]) -+ - (define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:SF 1 "register_operand" "d")))] --- -2.14.2 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch deleted file mode 100644 index ff8e6107..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch +++ /dev/null @@ -1,72 +0,0 @@ -From fabd23a354496701b4a9ebf6931485b0d61c7bbe Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:45 -0700 -Subject: [PATCH] MicroBlaze correct the const high double immediate value - -With this patch the loading of the DI mode immediate values will be -using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE -functions, as CONST_DOUBLE_HIGH was returning the sign extension value -even of the unsigned long long constants also - -ChangeLog: - -2016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> - - * microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE & - REAL_VALUE_TO_TARGET_DOUBLE - * long.c (new): Added new testcase - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.c | 6 ++++-- - gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++ - 2 files changed, 14 insertions(+), 2 deletions(-) - create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index e7697bf30d..96bf6e1cab 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2493,14 +2493,16 @@ print_operand (FILE * file, rtx op, int letter) - else if (letter == 'h' || letter == 'j') - { - long val[2]; -+ long l[2]; - if (code == CONST_DOUBLE) - { - if (GET_MODE (op) == DFmode) - REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); - else - { -- val[0] = CONST_DOUBLE_HIGH (op); -- val[1] = CONST_DOUBLE_LOW (op); -+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); -+ val[1] = l[WORDS_BIG_ENDIAN == 0]; -+ val[0] = l[WORDS_BIG_ENDIAN != 0]; - } - } - else if (code == CONST_INT) -diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c -new file mode 100644 -index 0000000000..4d4518619d ---- /dev/null -+++ b/gcc/testsuite/gcc.target/microblaze/long.c -@@ -0,0 +1,10 @@ -+/* { dg-options "-O0" } */ -+#define BASEADDR 0xF0000000ULL -+int main () -+{ -+ unsigned long long start; -+ start = (unsigned long long) BASEADDR; -+ return 0; -+} -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */ -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */ --- -2.14.2 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch deleted file mode 100644 index 7ea28ee8..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 2149d85f1f7375dd97bf961b2bdb693d6d931c13 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:46 -0700 -Subject: [PATCH] Fix internal compiler error with msmall-divides - -This patch will fix the internal error microblaze_expand_divide function -which comes because of rtx PLUS where the mem_rtx is of type SI and the -operand is of type QImode. This patch modifies the mem_rtx as QImode and -Plus as QImode to fix the error. - -ChangeLog: - -2016-02-23 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> - - * microblaze.c (microblaze_expand_divide): Update - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 96bf6e1cab..a41121264e 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3719,7 +3719,7 @@ microblaze_expand_divide (rtx operands[]) - emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); - emit_insn (gen_addsi3 (regt1, regt1, operands[2])); - mem_rtx = gen_rtx_MEM (QImode, -- gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); -+ gen_rtx_PLUS (QImode, regt1, div_table_rtx)); - - insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); - jump = emit_jump_insn_after (gen_jump (div_end_label), insn); --- -2.14.2 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch deleted file mode 100644 index eaae5667..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch +++ /dev/null @@ -1,51 +0,0 @@ -From e2a7a582945d24ede55393462a3360f377f45478 Mon Sep 17 00:00:00 2001 -From: Nathan Rossi <nathan@nathanrossi.com> -Date: Sun, 5 Nov 2017 23:03:54 +1000 -Subject: [PATCH] MicroBlaze fix signed bit fields with bit field instructions - -The 'extv' definition is expected to sign extended the result based on -the width of the bit field. - - https://gcc.gnu.org/onlinedocs/gccint/Standard-Names.html#index-extvm-instruction-pattern - -The MicroBlaze 'bsefi' instruction does not sign extended, it zero -extends. There is no option for the instruction to sign extended the -result and no simple instruction or expression to implement a variant -length sign extend (only sext8/sext16 instructions exist). - -As such these definitions needs to be changed to the zero extended -variant of 'extv' which is 'extzv'. This change updates the existing -definitions to allow for signed bit fields to function correctly and be -sign extended. - -Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.md | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index ef53c3069e..b52be42d6e 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2476,7 +2476,7 @@ - DONE; - }") - --(define_expand "extvsi" -+(define_expand "extzvsi" - [(set (match_operand:SI 0 "register_operand" "r") - (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "I") -@@ -2485,7 +2485,7 @@ - "" - ) - --(define_insn "extv_32" -+(define_insn "extzv_32" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "I") --- -2.14.2 - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch new file mode 100644 index 00000000..5d29531d --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch @@ -0,0 +1,35 @@ +From 7fbf19ba660c72a1d4817780cad5c4ae52cbe0b5 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 11 Jan 2017 13:13:57 +0530 +Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic + Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> + +Conflicts: + + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +--- + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +index 9f0b24a..1cb4f97 100644 +--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*] + lappend additional_flags "-Wl,--allow-multiple-definition" + } + ++<<<<<<< HEAD ++======= ++if [istarget "microblaze*-*-linux*"] { ++ lappend additional_flags "-Wl,-zmuldefs" ++ lappend additional_flags "-fPIC" ++} ++ ++>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic + foreach src [lsort [find $srcdir/$subdir *.c]] { + if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { + c-torture-execute [list $src \ +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch new file mode 100644 index 00000000..503b1ecf --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch @@ -0,0 +1,31 @@ +From 4b675eeabceea22ec51abfa7c37e11a631e58659 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 11 Jan 2017 14:31:10 +0530 +Subject: [PATCH 02/54] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This + particular testcase fails with a timeout. Instead, fail it at compile-time + for microblaze. This speeds up the testsuite without removing it from the + FAIL reports. + +Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> +--- + gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C +index 66411cd..d951fee 100644 +--- a/gcc/testsuite/g++.dg/opt/memcpy1.C ++++ b/gcc/testsuite/g++.dg/opt/memcpy1.C +@@ -4,6 +4,10 @@ + // { dg-do compile } + // { dg-options "-O" } + ++#if defined (__MICROBLAZE__) ++#error "too slow on mb. Investigate." ++#endif ++ + typedef unsigned char uint8_t; + typedef uint8_t uint8; + __extension__ typedef __SIZE_TYPE__ size_t; +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch new file mode 100644 index 00000000..39058496 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch @@ -0,0 +1,116 @@ +From 03d4d7335be2b2f72c199ab5177685b6dfd1a9d6 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 11 Jan 2017 15:28:38 +0530 +Subject: [PATCH 03/54] [LOCAL]: Testsuite - explicitly add -fivopts for tests + that depend on it (test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt + exist in 4.6 branch) + +Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> +--- + gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C | 2 +- + gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/loop-2.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/loop-4.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/loop-5.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/pr19590.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +- + 8 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C +index 438db88..ede883e 100644 +--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C ++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C +@@ -1,5 +1,5 @@ + /* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */ +-/* { dg-options "-O2 -fdump-tree-ivopts-details" } */ ++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */ + + void test (int *b, int *e, int stride) + { +diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C +index 07ff1b7..a09710c 100644 +--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C ++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C +@@ -1,5 +1,5 @@ + // { dg-do compile } +-// { dg-options "-O2 -fdump-tree-ivopts-details" } ++// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } + + class MinimalVec3 + { +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c +index bda2516..22c8a5d 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c +@@ -1,7 +1,7 @@ + /* A test for strength reduction and induction variable elimination. */ + + /* { dg-do compile } */ +-/* { dg-options "-O1 -fdump-tree-optimized" } */ ++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */ + /* { dg-require-effective-target size32plus } */ + + /* Size of this structure should be sufficiently weird so that no memory +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c +index f0770ab..65d74c8 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c +@@ -1,7 +1,7 @@ + /* A test for strength reduction and induction variable elimination. */ + + /* { dg-do compile } */ +-/* { dg-options "-O1 -fdump-tree-optimized" } */ ++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */ + /* { dg-require-effective-target size32plus } */ + + /* Size of this structure should be sufficiently weird so that no memory +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c +index 5f42857..9bc86ee 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c +@@ -1,7 +1,7 @@ + /* A test for induction variable merging. */ + + /* { dg-do compile } */ +-/* { dg-options "-O1 -fdump-tree-optimized" } */ ++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */ + + void foo(long); + +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c +index 0fa5600..94caa44 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */ ++/* { dg-options "-O2 -fivopts -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */ + extern void g(void); + + void +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c +index 2c6cfc6..648e6e6 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -fdump-tree-ivopts" } */ ++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */ + + void vnum_test8(int *data) + { +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c +index e911bfc..5d3e7e0 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-Os -fdump-tree-optimized" } */ ++/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */ + + /* Slightly changed testcase from PR middle-end/40815. */ + void bar(char*, char*, int); +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch new file mode 100644 index 00000000..e16528b6 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch @@ -0,0 +1,35 @@ +From a4c99f7f7775f105eb6f1dfbdf304e6b7e498e2e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 11 Jan 2017 15:46:28 +0530 +Subject: [PATCH 04/54] [LOCAL]: For dejagnu static testing on qemu, suppress + warnings about multiple definitions from the test function and libc in line + with method used by powerpc. Dynamic linking and using a qemu binary which + understands sysroot resolves all test failures with builtins + +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +--- + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +index 1cb4f97..bdfa08a 100644 +--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*] + lappend additional_flags "-Wl,--allow-multiple-definition" + } + +-<<<<<<< HEAD +-======= + if [istarget "microblaze*-*-linux*"] { + lappend additional_flags "-Wl,-zmuldefs" +- lappend additional_flags "-fPIC" + } + +->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic + foreach src [lsort [find $srcdir/$subdir *.c]] { + if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { + c-torture-execute [list $src \ +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch index 6fad8bf7..33688f14 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch @@ -1,7 +1,8 @@ -From 8bcdd551f7fe585126ea3173ece976fbc646c34a Mon Sep 17 00:00:00 2001 +From 6b0de6811796b6834d426263eaa855b65c9b3389 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:20 -0700 -Subject: [PATCH] Add MicroBlaze to target-supports for atomic builtin tests +Date: Wed, 11 Jan 2017 15:50:35 +0530 +Subject: [PATCH 05/54] [Patch, testsuite]: Add MicroBlaze to target-supports + for atomic buil. .tin tests MicroBlaze added to supported targets for atomic builtin tests. @@ -13,18 +14,15 @@ Changelog/testsuite check_effective_target_sync_int_long. Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/testsuite/lib/target-supports.exp | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp -index 342af270ab..b0f510e596 100644 +index c591acd..94353cc 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp -@@ -6715,6 +6715,7 @@ proc check_effective_target_sync_int_long { } { +@@ -7428,6 +7428,7 @@ proc check_effective_target_sync_int_long { } { && [check_effective_target_arm_acq_rel]) || [istarget bfin*-*linux*] || [istarget hppa*-*linux*] @@ -33,5 +31,5 @@ index 342af270ab..b0f510e596 100644 || [istarget powerpc*-*-*] || [istarget crisv32-*-*] || [istarget cris-*-*] -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch index b428d121..b428d121 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch index 069329fc..3e2368f2 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch @@ -1,8 +1,8 @@ -From 4622988b62335af6ef17d58bf10940419fd0f99f Mon Sep 17 00:00:00 2001 +From 0d2cca275f3e85ae42dac7888d862975d65ffb36 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:21 -0700 -Subject: [PATCH] Update MicroBlaze strings test for new scan-assembly output - resulting in use of $LC label +Date: Wed, 11 Jan 2017 16:20:01 +0530 +Subject: [PATCH 06/54] [Patch, testsuite]: Update MicroBlaze strings test for + new scan-assembly output resulting in use of $LC label ChangeLog/testsuite @@ -12,15 +12,12 @@ ChangeLog/testsuite to include $LC label. Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c -index 7a63faf79f..0403b7bdca 100644 +index 7a63faf..0403b7b 100644 --- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c +++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c @@ -1,13 +1,15 @@ @@ -42,5 +39,5 @@ index 7a63faf79f..0403b7bdca 100644 somefunc (string2); } -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch index dbfeb52b..bcd5dbad 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch @@ -1,11 +1,9 @@ -From 037809e91bfed9c501ecd5272ff6d3ce96edf76c Mon Sep 17 00:00:00 2001 +From b6f828da3caa827d8ccc08bbf260a2a01b2b2613 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:22 -0700 -Subject: [PATCH] Allow MicroBlaze .weakext pattern in testsuite - -Allow MicroBlaze .weakext pattern in regex match Extend regex pattern to -include optional ext at the end of .weak to match the MicroBlaze weak -label .weakext +Date: Thu, 12 Jan 2017 16:14:15 +0530 +Subject: [PATCH 07/54] [Patch, testsuite]: Allow MicroBlaze .weakext pattern + in regex match Extend regex pattern to include optional ext at the end of + .weak to match the MicroBlaze weak label .weakext ChangeLog/testsuite @@ -16,9 +14,10 @@ ChangeLog/testsuite * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise. Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + +Conflicts: + + gcc/testsuite/g++.dg/abi/rtti3.C --- gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++-- gcc/testsuite/g++.dg/abi/thunk3.C | 2 +- @@ -26,13 +25,13 @@ Upstream-Status: Pending 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C -index 0316bcb5de..5a39a0811f 100644 +index 0cc7d3e..f284cd9 100644 --- a/gcc/testsuite/g++.dg/abi/rtti3.C +++ b/gcc/testsuite/g++.dg/abi/rtti3.C @@ -3,8 +3,8 @@ // { dg-require-weak "" } - // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } } + // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } -// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } } -// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } +// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } } @@ -41,7 +40,7 @@ index 0316bcb5de..5a39a0811f 100644 // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } } diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C -index f2347f79ec..dcec8a771a 100644 +index f2347f7..dcec8a7 100644 --- a/gcc/testsuite/g++.dg/abi/thunk3.C +++ b/gcc/testsuite/g++.dg/abi/thunk3.C @@ -1,5 +1,5 @@ @@ -52,17 +51,17 @@ index f2347f79ec..dcec8a771a 100644 struct Base diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C -index fa5fbd4327..79cb311cab 100644 +index 6e8f124..d1d34fe 100644 --- a/gcc/testsuite/g++.dg/abi/thunk4.C +++ b/gcc/testsuite/g++.dg/abi/thunk4.C @@ -1,6 +1,6 @@ // { dg-require-weak "" } - // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } } + // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } -// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } +// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } struct Base -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch index 6b9dd991..6232535d 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch @@ -1,25 +1,21 @@ -From 23a04c06c2a689fed151eeb94c45ea9b512036ae Mon Sep 17 00:00:00 2001 +From d27a2545486da9c6a4d3d5ca06b4affb83f8d0a1 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:23 -0700 -Subject: [PATCH] Add MicroBlaze to check_profiling_available Testsuite - -Add MicroBlaze to check_profiling_available Testsuite, add -microblaze*-*-* target in check_profiling_available inline with other -archs setting profiling_available_saved to 0 +Date: Thu, 12 Jan 2017 16:34:27 +0530 +Subject: [PATCH 08/54] [Patch, testsuite]: Add MicroBlaze to + check_profiling_available Testsuite, add microblaze*-*-* target in + check_profiling_available inline with other archs setting + profiling_available_saved to 0 Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/testsuite/lib/target-supports.exp | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp -index b0f510e596..fffb690e49 100644 +index 94353cc..ecfbe4d 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp -@@ -625,6 +625,7 @@ proc check_profiling_available { test_what } { +@@ -676,6 +676,7 @@ proc check_profiling_available { test_what } { || [istarget m68k-*-elf] || [istarget m68k-*-uclinux*] || [istarget mips*-*-elf*] @@ -28,5 +24,5 @@ index b0f510e596..fffb690e49 100644 || [istarget mn10300-*-elf*] || [istarget moxie-*-elf*] -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch index c21ca816..db730f43 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch @@ -1,25 +1,21 @@ -From c1e8a1419e8f5d18e7135fb4fe3bf21941125008 Mon Sep 17 00:00:00 2001 +From 8711bdfe27bce04d35ba93a1d18ccccd61371829 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:24 -0700 -Subject: [PATCH] Fix atomic side effects. - -In atomic_compare_and_swapsi, add side effects to prevent incorrect -assumptions during optimization. Previously, the outputs were considered -unused; this generated assembly code with undefined side effects after -invocation of the atomic. +Date: Thu, 12 Jan 2017 16:41:43 +0530 +Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic side effects. In + atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions + during optimization. Previously, the outputs were considered unused; this + generated assembly code with undefined side effects after invocation of the + atomic. Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.md | 3 +++ gcc/config/microblaze/sync.md | 21 +++++++++++++-------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 8a372d7ebb..59d629b559 100644 +index f698e54..93f5fa2 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -41,6 +41,9 @@ @@ -33,7 +29,7 @@ index 8a372d7ebb..59d629b559 100644 (define_c_enum "unspec" [ diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md -index 8125bd8d63..edf4bdd811 100644 +index b34bd54..8e694e9 100644 --- a/gcc/config/microblaze/sync.md +++ b/gcc/config/microblaze/sync.md @@ -18,14 +18,19 @@ @@ -65,5 +61,5 @@ index 8125bd8d63..edf4bdd811 100644 "" { -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch index f4bc16e8..5058529a 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch @@ -1,22 +1,18 @@ -From a5957bdf7acfde0a65eeba90bae11f5619bf96af Mon Sep 17 00:00:00 2001 +From 92015c19e5d1baabd62067bf1cfc4522e85d1b25 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:25 -0700 -Subject: [PATCH] Fix atomic boolean return value. - -In atomic_compare_and_swapsi, fix boolean return value. Previously, it -contained zero if successful and non-zero if unsuccessful. +Date: Thu, 12 Jan 2017 16:45:45 +0530 +Subject: [PATCH 10/54] [Patch, microblaze]: Fix atomic boolean return value. + In atomic_compare_and_swapsi, fix boolean return value. Previously, it + contained zero if successful and non-zero if unsuccessful. Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/sync.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md -index edf4bdd811..aadb414728 100644 +index 8e694e9..8ddb10d 100644 --- a/gcc/config/microblaze/sync.md +++ b/gcc/config/microblaze/sync.md @@ -34,15 +34,16 @@ @@ -40,5 +36,5 @@ index edf4bdd811..aadb414728 100644 } ) -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch new file mode 100644 index 00000000..2451c938 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch @@ -0,0 +1,33 @@ +From 658476aef537c0c2d031eb1c7a001f00c1d9bf7b Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Thu, 12 Jan 2017 16:50:17 +0530 +Subject: [PATCH 11/54] [Patch, microblaze]: Fix the Microblaze crash with + msmall-divides flag Compiler is crashing when we use msmall-divides and + mxl-barrel-shift flag. This is because when use above flags + microblaze_expand_divide function will be called for division operation. In + microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't + have subreg register due to this compiler was crashing. Changed the logic to + avoid sub_reg call + +Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> +--- + gcc/config/microblaze/microblaze.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 9a4a287..cbe8cb7 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3575,8 +3575,7 @@ microblaze_expand_divide (rtx operands[]) + mem_rtx = gen_rtx_MEM (QImode, + gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); + +- insn = emit_insn (gen_movqi (regqi, mem_rtx)); +- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); ++ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + JUMP_LABEL (jump) = div_end_label; + LABEL_NUSES (div_end_label) = 1; +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch index 6005e216..b58df873 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch @@ -1,26 +1,21 @@ -From c32df2ec3d269d19b631a17cea2b6d19bbb98c27 Mon Sep 17 00:00:00 2001 +From 64f1a238641616c9cca5823d7ca99e76a7c2a490 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:27 -0700 -Subject: [PATCH] Add MicroBlaze ashrsi_3_with_size_opt +Date: Thu, 12 Jan 2017 16:52:56 +0530 +Subject: [PATCH 12/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added + ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os + optimization is used. lshrsi3_with_size_opt is being removed as it has + conflicts with unsigned int variables -Added ashrsi3_with_size_opt Added ashrsi3_with_size_opt pattern to -optimize the sra instructions when the -Os optimization is used. -lshrsi3_with_size_opt is being removed as it has conflicts with unsigned -int variables - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> --- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 59d629b559..8c0a97e032 100644 +index 93f5fa2..fe90a14 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md -@@ -1505,6 +1505,27 @@ +@@ -1506,6 +1506,27 @@ (set_attr "length" "4,4")] ) @@ -49,5 +44,5 @@ index 59d629b559..8c0a97e032 100644 [(set (match_operand:SI 0 "register_operand" "=&d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch index e75bebeb..6af0f10e 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch @@ -1,12 +1,10 @@ -From 79ea36649467aea6045a49c7d016f8f9245efb8c Mon Sep 17 00:00:00 2001 +From ed23e22fb25a2d3dc357c0743f51b2735fc46a6a Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:29 -0700 -Subject: [PATCH] MicroBlaze fixed missing save of r18 in fast_interrupt - -Fixed missing save of r18 in fast_interrupt. Register 18 is used as a -clobber register, and must be stored when entering a fast_interrupt. -Before this fix, register 18 was only saved if it was used directly in -the interrupt function. +Date: Thu, 12 Jan 2017 17:50:03 +0530 +Subject: [PATCH 13/54] [Patch, microblaze]: Fixed missing save of r18 in + fast_interrupt. Register 18 is used as a clobber register, and must be stored + when entering a fast_interrupt. Before this fix, register 18 was only saved + if it was used directly in the interrupt function. However, if the fast_interrupt function called a function that used r18, the register would not be saved, and thus be mangled @@ -21,18 +19,15 @@ Changelog Signed-off-by: Klaus Petersen <klauspetersen@gmail.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 15080db539..558796cad9 100644 +index cbe8cb7..6f0b4f4 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -1943,7 +1943,7 @@ microblaze_must_save_register (int regno) +@@ -1967,7 +1967,7 @@ microblaze_must_save_register (int regno) { if (df_regs_ever_live_p (regno) || regno == MB_ABI_MSR_SAVE_REG @@ -42,5 +37,5 @@ index 15080db539..558796cad9 100644 || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM))) return 1; -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch index f5de718e..f47265b0 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch @@ -1,21 +1,18 @@ -From 6ed57ee8219e5d09a294b329dd7c531a1868dc8a Mon Sep 17 00:00:00 2001 +From 582558f3c18d096885ab24e645899f310b148b5c Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:31 -0700 -Subject: [PATCH] MicroBlaze use bralid for profiler calls +Date: Tue, 17 Jan 2017 10:57:19 +0530 +Subject: [PATCH 14/54] [Patch, microblaze]: Use bralid for profiler calls + Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> -Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index ccd77e8b4d..0dd8b853e2 100644 +index 0d3718f..88e0351 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h -@@ -519,7 +519,7 @@ typedef struct microblaze_args +@@ -486,7 +486,7 @@ typedef struct microblaze_args #define FUNCTION_PROFILER(FILE, LABELNO) { \ { \ @@ -25,5 +22,5 @@ index ccd77e8b4d..0dd8b853e2 100644 } -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch new file mode 100644 index 00000000..acfa083f --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch @@ -0,0 +1,42 @@ +From b60068cbdd3c830e541fbd35f2ed119245911461 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 11:10:21 +0530 +Subject: [PATCH 15/54] [Patch, microblaze]: Disable fivopts by default Turn + off ivopts by default. Interferes with cse. + +Changelog + +2013-03-18 Edgar E. Iglesias <edgar.iglesias@xilinx.com> + + * gcc/common/config/microblaze/microblaze-common.c + (microblaze_option_optimization_table): Disable fivopts by default. + +Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +--- + gcc/common/config/microblaze/microblaze-common.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c +index 3e75675..fe45f2e 100644 +--- a/gcc/common/config/microblaze/microblaze-common.c ++++ b/gcc/common/config/microblaze/microblaze-common.c +@@ -24,6 +24,15 @@ + #include "common/common-target.h" + #include "common/common-target-def.h" + ++/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ ++static const struct default_options microblaze_option_optimization_table[] = ++ { ++ /* Turn off ivopts by default. It messes up cse. */ ++ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, ++ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, ++ { OPT_LEVELS_NONE, 0, NULL, 0 } ++ }; ++ + #undef TARGET_DEFAULT_TARGET_FLAGS + #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT + +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch index b0195718..dbd7b2e2 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch @@ -1,30 +1,25 @@ -From a68e94fc57bcf60cb730894e49dde55d081397f5 Mon Sep 17 00:00:00 2001 +From 640628680ff6f028ad6d5fef2e41da29664f036f Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:28 -0700 -Subject: [PATCH] Removed MicroBlaze moddi3 routinue +Date: Thu, 12 Jan 2017 17:36:16 +0530 +Subject: [PATCH 16/54] [Patch, microblaze]: Removed moddi3 routinue Using the + default moddi3 function as the existing implementation has many bugs -Removed moddi3 routinue Using the default moddi3 function as the -existing implementation has many bugs - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +Signed-off-by:Nagaraju <nmekala@xilix.com> --- - libgcc/config/microblaze/moddi3.S | 115 ---------------------------------- + libgcc/config/microblaze/moddi3.S | 121 ---------------------------------- libgcc/config/microblaze/t-microblaze | 3 +- - 2 files changed, 1 insertion(+), 117 deletions(-) + 2 files changed, 1 insertion(+), 123 deletions(-) delete mode 100644 libgcc/config/microblaze/moddi3.S diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S deleted file mode 100644 -index bcea079476..0000000000 +index a8f17d7..0000000 --- a/libgcc/config/microblaze/moddi3.S +++ /dev/null -@@ -1,115 +0,0 @@ +@@ -1,121 +0,0 @@ -################################### -# --# Copyright (C) 2009-2017 Free Software Foundation, Inc. +-# Copyright (C) 2009-2018 Free Software Foundation, Inc. -# -# Contributed by Michael Eager <eager@eagercon.com>. -# @@ -54,6 +49,12 @@ index bcea079476..0000000000 -####################################### - - +-/* An executable stack is *not* required for these functions. */ +-#ifdef __linux__ +-.section .note.GNU-stack,"",%progbits +-.previous +-#endif +- - .globl __moddi3 - .ent __moddi3 -__moddi3: @@ -138,7 +139,7 @@ index bcea079476..0000000000 - .end __moddi3 - diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze -index 96959f0292..8d954a4957 100644 +index 96959f0..8d954a4 100644 --- a/libgcc/config/microblaze/t-microblaze +++ b/libgcc/config/microblaze/t-microblaze @@ -1,8 +1,7 @@ @@ -152,5 +153,5 @@ index 96959f0292..8d954a4957 100644 $(srcdir)/config/microblaze/muldi3_hard.S \ $(srcdir)/config/microblaze/mulsi3.S \ -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch index 5239d2bd..6fb1b32f 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch @@ -1,8 +1,8 @@ -From 02d8afd50a868e827ac8b6b6243c69922cd694ed Mon Sep 17 00:00:00 2001 +From c0e74b79cc1db2f68dd560154225da1e5ddfd920 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:34 -0700 -Subject: [PATCH] Add INIT_PRIORITY support Added TARGET_ASM_CONSTRUCTOR and - TARGET_ASM_DESTRUCTOR macros. +Date: Tue, 17 Jan 2017 14:41:58 +0530 +Subject: [PATCH 17/54] [Patch, microblaze]: Add INIT_PRIORITY support Added + TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros. These macros allows users to control the order of initialization of objects defined at namespace scope with the init_priority @@ -19,20 +19,17 @@ Changelog microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR. -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> +Signed-off-by:nagaraju <nmekala@xilix.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 558796cad9..c1b0172bcf 100644 +index 6f0b4f4..53b44df 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -2530,6 +2530,53 @@ print_operand_address (FILE * file, rtx addr) +@@ -2554,6 +2554,53 @@ print_operand_address (FILE * file, rtx addr) } } @@ -86,7 +83,7 @@ index 558796cad9..c1b0172bcf 100644 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol is used, so that we don't emit an .extern for it in microblaze_asm_file_end. */ -@@ -3775,6 +3822,12 @@ microblaze_machine_dependent_reorg (void) +@@ -3841,6 +3888,12 @@ microblaze_starting_frame_offset (void) #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table @@ -100,5 +97,5 @@ index 558796cad9..c1b0172bcf 100644 #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch index 049ce3fe..ab2473a3 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch @@ -1,12 +1,9 @@ -From 0b2061ac7706df97da3e8b3c01c6a5cfc504c16e Mon Sep 17 00:00:00 2001 +From 2cba68c3e27ffaea77cc5469233cf4dcb9383142 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:35 -0700 -Subject: [PATCH] MicroBlaze add optimized lshrsi3 When barrel shifter is not - present - -Add optimized lshrsi3 When barrel shifter is not present, the immediate -value is greater than #5 and optimization is -OS, the compiler will -generate shift operation using loop. +Date: Tue, 17 Jan 2017 15:23:57 +0530 +Subject: [PATCH 18/54] [Patch, microblaze]: Add optimized lshrsi3 When barrel + shifter is not present, the immediate value is greater than #5 and + optimization is -OS, the compiler will generate shift operation using loop. Changelog @@ -20,11 +17,8 @@ ChangeLog/testsuite * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> +Signed-off-by:Nagaraju <nmekala@xilix.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ .../gcc.target/microblaze/others/lshrsi_Os_1.c | 13 +++++++++++++ @@ -32,10 +26,10 @@ Upstream-Status: Pending create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 8c0a97e032..abbe97c15f 100644 +index fe90a14..c063ffc 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md -@@ -1615,6 +1615,27 @@ +@@ -1616,6 +1616,27 @@ (set_attr "length" "4,4")] ) @@ -65,7 +59,7 @@ index 8c0a97e032..abbe97c15f 100644 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c new file mode 100644 -index 0000000000..32a3be7c76 +index 0000000..32a3be7 --- /dev/null +++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c @@ -0,0 +1,13 @@ @@ -83,5 +77,5 @@ index 0000000000..32a3be7c76 +/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */ +/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */ -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch new file mode 100644 index 00000000..5afcff43 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch @@ -0,0 +1,29 @@ +From e8b05b5105655d276c93864ab90e15bfbe46cf74 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 15:42:15 +0530 +Subject: [PATCH 19/54] [Patch, microblaze]: Modified trap instruction The + instruction was wrongly written to brki r0,-1 it should be bri r0. Modified + with the correct instruction + +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + :Ajit Agarwal <ajitkum@xilinx.com> +--- + gcc/config/microblaze/microblaze.md | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index c063ffc..7bbdbe1 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2344,7 +2344,7 @@ + (define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" +- "brki\tr0,-1" ++ "bri\t0" + [(set_attr "type" "trap")] + ) + +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch index ead929ab..6e07ac4f 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch @@ -1,26 +1,20 @@ -From f5416ee7ddc6e4853e57ed15fb2bf630de2c3b12 Mon Sep 17 00:00:00 2001 +From 0cc6aabbd3f7b331c3995f11efec545499297358 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:37 -0700 -Subject: [PATCH] Reducing Stack space for arguments Currently in Microblaze - target stack space +Date: Tue, 17 Jan 2017 16:42:44 +0530 +Subject: [PATCH 20/54] [Patch, microblaze]: Reducing Stack space for arguments + Currently in Microblaze target stack space for arguments in register is being + allocated even if there are no arguments in the function. This patch will + optimize the extra 24 bytes that are being allocated. -Reducing Stack space for arguments Currently in Microblaze target stack -space for arguments in register is being allocated even if there are no -arguments in the function. This patch will optimize the extra 24 bytes -that are being allocated. +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + :Ajit Agarwal <ajitkum@xilinx.com> ChangeLog: -2015-04-17 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> +2015-04-17 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> - * microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New - * microblaze.c (REG_PARM_STACK_SPACE): Modify - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New + *microblaze.c (REG_PARM_STACK_SPACE): Modify --- gcc/config/microblaze/microblaze-protos.h | 1 + gcc/config/microblaze/microblaze.c | 134 +++++++++++++++++++++++++++++- @@ -28,10 +22,10 @@ Upstream-Status: Pending 3 files changed, 136 insertions(+), 3 deletions(-) diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h -index b56e052ae4..a1408629cc 100644 +index 4cbba0c..f8a56f7 100644 --- a/gcc/config/microblaze/microblaze-protos.h +++ b/gcc/config/microblaze/microblaze-protos.h -@@ -57,6 +57,7 @@ extern int symbol_mentioned_p (rtx); +@@ -58,6 +58,7 @@ extern int symbol_mentioned_p (rtx); extern int label_mentioned_p (rtx); extern bool microblaze_cannot_force_const_mem (machine_mode, rtx); extern void microblaze_eh_return (rtx op0); @@ -40,10 +34,10 @@ index b56e052ae4..a1408629cc 100644 /* Declare functions in microblaze-c.c. */ diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index c1b0172bcf..f46dffff0d 100644 +index 53b44df..0dec362 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -1965,6 +1965,138 @@ microblaze_must_save_register (int regno) +@@ -1989,6 +1989,138 @@ microblaze_must_save_register (int regno) return 0; } @@ -182,7 +176,7 @@ index c1b0172bcf..f46dffff0d 100644 /* Return the bytes needed to compute the frame pointer from the current stack pointer. -@@ -3275,7 +3407,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, +@@ -3298,7 +3430,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, emit_insn (gen_indirect_jump (temp2)); /* Run just enough of rest_of_compilation. This sequence was @@ -192,10 +186,10 @@ index c1b0172bcf..f46dffff0d 100644 shorten_branches (insn); final_start_function (insn, file, 1); diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 0dd8b853e2..82e7e890be 100644 +index 88e0351..9f74ec8 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h -@@ -467,9 +467,9 @@ extern struct microblaze_frame_info current_frame_info; +@@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info; #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 @@ -208,5 +202,5 @@ index 0dd8b853e2..82e7e890be 100644 #define STACK_BOUNDARY 32 -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch new file mode 100644 index 00000000..b04ee580 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch @@ -0,0 +1,159 @@ +From f846bd900d5277dd9defb5fe0625f97e3417ee61 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 17:04:37 +0530 +Subject: [PATCH 21/54] [Patch, microblaze]: Add cbranchsi4_reg This patch + optimizes the generation of pcmpne/pcmpeq instruction if the compare + instruction has no immediate values.For the immediate values the xor + instruction is generated + +Signed-off-by: Nagaraju Mekala <nmekala@xilix.com> +Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> + +ChangeLog: +2015-01-13 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> + + *microblaze.md (cbranchsi4_reg): New + *microblaze.c (microblaze_expand_conditional_branch_reg): New + +Conflicts: + + gcc/config/microblaze/microblaze-protos.h +--- + gcc/config/microblaze/microblaze-protos.h | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c | 14 +++++++------- + gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------ + gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c | 2 +- + 8 files changed, 19 insertions(+), 19 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index f8a56f7..c39e2e9 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -32,7 +32,7 @@ extern int microblaze_expand_shift (rtx *); + extern bool microblaze_expand_move (machine_mode, rtx *); + extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); + extern void microblaze_expand_divide (rtx *); +-extern void microblaze_expand_conditional_branch (machine_mode, rtx *); ++extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_sf (rtx *); + extern int microblaze_can_use_return_insn (void); +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c +index 4041a24..ccc6a46 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 <= f3) +- print ("le"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c +index 3902b83..1dd5fe6 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 < f3) +- print ("lt"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c +index 8555974..d6f80fb 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 == f3) +- print ("eq"); ++ f1 = f2 + f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c +index 79cc5f9..d117724 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c +@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3) + /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if(f1==f2 && f1<=f3) +- print ("f1 eq f2 && f1 le f3"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c +index ebfb170..7582297 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c +@@ -5,17 +5,17 @@ volatile float f1, f2, f3; + void float_func () + { + /* { dg-final { scan-assembler-not "fcmp" } } */ +- if (f2 <= f3) +- print ("le"); ++ if (f2 <= f3) ++ f1 = f3; + else if (f2 == f3) +- print ("eq"); ++ f1 = f3; + else if (f2 < f3) +- print ("lt"); ++ f1 = f3; + else if (f2 > f3) +- print ("gt"); ++ f1 = f3; + else if (f2 >= f3) +- print ("ge"); ++ f1 = f3; + else if (f2 != f3) +- print ("ne"); ++ f1 = f3; + + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c +index 1d6ba80..532c035 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c +@@ -74,16 +74,16 @@ void float_cmp_func () + { + /* { dg-final { scan-assembler-not "fcmp" } } */ + if (f2 <= f3) +- print ("le"); ++ f1 = f3; + else if (f2 == f3) +- print ("eq"); ++ f1 = f3; + else if (f2 < f3) +- print ("lt"); ++ f1 = f3; + else if (f2 > f3) +- print ("gt"); ++ f1 = f3; + else if (f2 >= f3) +- print ("ge"); ++ f1 = f3; + else if (f2 != f3) +- print ("ne"); ++ f1 = f3; + + } +diff --git a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c +index fdcde1f..580b4db 100644 +--- a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c ++++ b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c +@@ -5,4 +5,4 @@ void trap () + __builtin_trap (); + } + +-/* { dg-final { scan-assembler "brki\tr0,-1" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler "bri\t0" } } */ +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch new file mode 100644 index 00000000..beeb80fd --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch @@ -0,0 +1,58 @@ +From 7d70a287544dd915b66a5658a3857ebecb8b3583 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 17:11:04 +0530 +Subject: [PATCH 22/54] [Patch,microblaze]: Inline Expansion of fsqrt builtin. + The changes are made in the patch for the inline expansion of the fsqrt + builtin with fqrt instruction. The sqrt math function takes double as + argument and return double as argument. The pattern is selected while + expanding the unary op through expand_unop which passes DFmode and the DFmode + pattern was not there returning zero. Thus the sqrt math function is not + inlined and expanded. The pattern with DFmode argument is added. Also the + source and destination argument is not same the DF through two different + consecutive registers with lower 32 bit is the argument passed to sqrt and + the higher 32 bit is zero. If the source and destinations are different the + DFmode 64 bits registers is not set properly giving the problem in runtime. + Such changes are taken care in the implementation of the pattern for DFmode + for inline expansion of the sqrt. + +ChangeLog: +2015-06-16 Ajit Agarwal <ajitkum@xilinx.com> + Nagaraju Mekala <nmekala@xilinx.com> + + * config/microblaze/microblaze.md (sqrtdf2): New + pattern. + +Signed-off-by:Ajit Agarwal ajitkum@xilinx.com + Nagaraju Mekala nmekala@xilinx.com +--- + gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 7bbdbe1..3a53e24 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -449,6 +449,20 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "sqrtdf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] ++ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" ++ { ++ if (REGNO (operands[0]) == REGNO (operands[1])) ++ return "fsqrt\t%0,%1"; ++ else ++ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; ++ } ++ [(set_attr "type" "fsqrt") ++ (set_attr "mode" "SF") ++ (set_attr "length" "4")]) ++ + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch new file mode 100644 index 00000000..8f5bed52 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch @@ -0,0 +1,47 @@ +From a28768eec0a9d5137196bed8e8c6d284cf4c3cbc Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 17:33:31 +0530 +Subject: [PATCH 23/54] [Patch] OPT: Update heuristics for loop-invariant for + address arithme. .tic. + +The changes are made in the patch to update the heuristics +for loop invariant for address arithmetic. The heuristics is +changed to calculate the estimated register pressure cost when +ira based register pressure is not enabled. The estimated +register pressure cost modifies the existing calculation cost +associated to perform the Loop invariant code motion for address +arithmetic. + +ChangeLog: +2015-06-17 Ajit Agarwal <ajitkum@xilinx.com> + Nagaraju Mekala <nmekala@xilinx.com> + + * loop-invariant.c (gain_for_invariant): update the + heuristics for estimate_reg_pressure_cost. + +Signed-off-by:Ajit Agarwal ajitkum@xilinx.com + Nagaraju Mekala nmekala@xilinx.com +--- + gcc/loop-invariant.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c +index bd31a51..8e22ca0 100644 +--- a/gcc/loop-invariant.c ++++ b/gcc/loop-invariant.c +@@ -1466,10 +1466,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed, + + if (! flag_ira_loop_pressure) + { +- size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0], +- regs_used, speed, call_p) +- - estimate_reg_pressure_cost (new_regs[0], +- regs_used, speed, call_p)); ++ size_cost = estimate_reg_pressure_cost (regs_needed[0], ++ regs_used, speed, call_p); + } + else if (ret < 0) + return -1; +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch index 03ea8b19..85a749e5 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch @@ -1,16 +1,14 @@ -From 2d90c10cf4d95999f68f474305828c7dfc51af18 Mon Sep 17 00:00:00 2001 -From: Nathan Rossi <nathan@nathanrossi.com> -Date: Thu, 12 Nov 2015 16:09:31 +1000 -Subject: [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' insn definitions - -Change adddi3 to handle DI immediates as the second operand, this -requires modification to the output template however reduces the need to -specify seperate templates for 16-bit positive/negative immediate -operands. The use of 32-bit immediates for the addi and addic -instructions is handled by the assembler, which will emit the imm -instructions when required. This conveniently handles the optimizable -cases where the immediate constant value does not need the higher half -words of the operands upper/lower words. +From be9c512be09fa4ef67870ab0456eb3781394dac3 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 18:07:24 +0530 +Subject: [PATCH 24/54] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' + insn definitions Change adddi3 to handle DI immediates as the second operand, + this requires modification to the output template however reduces the need to + specify seperate templates for 16-bit positive/negative immediate operands. + The use of 32-bit immediates for the addi and addic instructions is handled + by the assembler, which will emit the imm instructions when required. This + conveniently handles the optimizable cases where the immediate constant value + does not need the higher half words of the operands upper/lower words. Change the constraints of the subdi3 instruction definition such that it does not match the second operand as an immediate value. This is because @@ -20,16 +18,15 @@ instruction to perform a forward arithmetic subtraction (it only provides reverse 'rD = IMM - rA'). Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> -Upstream-Status: Unsubmitted --- gcc/config/microblaze/microblaze.md | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index b3a0011fd7..8a372d7ebb 100644 +index 3a53e24..949e103 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md -@@ -483,17 +483,16 @@ +@@ -500,17 +500,16 @@ ;; Adding 2 DI operands in register or reg/imm (define_insn "adddi3" @@ -52,7 +49,7 @@ index b3a0011fd7..8a372d7ebb 100644 ;;---------------------------------------------------------------- ;; Subtraction -@@ -530,7 +529,7 @@ +@@ -547,7 +546,7 @@ (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=&d") (minus:DI (match_operand:DI 1 "register_operand" "d") @@ -62,5 +59,5 @@ index b3a0011fd7..8a372d7ebb 100644 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" [(set_attr "type" "darith") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch index d8eb7695..17f25448 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch @@ -1,42 +1,36 @@ -From f269f552e1abf182dc3749e0f29b1529fc82644a Mon Sep 17 00:00:00 2001 +From c8ee051fa3e0ad05b19eb6141a7cb72245b412b7 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:42 -0700 -Subject: [PATCH] Update MicroBlaze ashlsi3 & movsf patterns +Date: Tue, 17 Jan 2017 18:18:41 +0530 +Subject: [PATCH 25/54] [Patch, microblaze]: Update ashlsi3 & movsf patterns + This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand + of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal + patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our + instruction doesn't support so using gen_int_mode function -This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in -print_operand of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and -movsf_internal patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating -64-bit value which our instruction doesn't support so using gen_int_mode -function +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + :Ajit Agarwal <ajitkum@xilinx.com> ChangeLog: +2016-01-07 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> -2016-01-07 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> - - * microblaze.md (ashlsi3_with_mul_nodelay, + *microblaze.md (ashlsi3_with_mul_nodelay, ashlsi3_with_mul_delay, movsf_internal): Updated the patterns to use gen_int_mode function - * microblaze.c (print_operand): - updated the 'F' case to use "unsinged int" instead - of HOST_WIDE_INT_PRINT_HEX - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *microblaze.c (print_operand): + updated the 'F' case to use "unsinged int" instead + of HOST_WIDE_INT_PRINT_HEX --- gcc/config/microblaze/microblaze.c | 2 +- gcc/config/microblaze/microblaze.md | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index f46dffff0d..663b20a022 100644 +index 0dec362..daf0269 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -2507,7 +2507,7 @@ print_operand (FILE * file, rtx op, int letter) +@@ -2531,7 +2531,7 @@ print_operand (FILE * file, rtx op, int letter) unsigned long value_long; REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), value_long); @@ -46,7 +40,7 @@ index f46dffff0d..663b20a022 100644 else { diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 13f8803428..b9c62b6d0f 100644 +index 949e103..bc675ca 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -1366,7 +1366,10 @@ @@ -74,5 +68,5 @@ index 13f8803428..b9c62b6d0f 100644 [(set_attr "type" "no_delay_arith") (set_attr "mode" "SI") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch index 6faa6251..506714bd 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch @@ -1,27 +1,25 @@ -From 17353cc4ba521f5ad928a1ede61cf03110e366ae Mon Sep 17 00:00:00 2001 +From 64e76f3be6ad78044ea2b89b555a07758c2b2950 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:43 -0700 -Subject: [PATCH] 8-stage pipeline for microblaze +Date: Tue, 17 Jan 2017 19:50:34 +0530 +Subject: [PATCH 26/54] [Patch, microblaze]: 8-stage pipeline for microblaze + This patch adds the support for the 8-stage pipeline. The new 8-stage + pipeline reduces the latencies of float & integer division drastically -This patch adds the support for the 8-stage pipeline. The new 8-stage -pipeline reduces the latencies of float & integer division drastically +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> ChangeLog: +2016-01-18 Nagaraju Mekala <nmekala@xilix.com> -2016-01-18 Nagaraju Mekala <nagaraju.mekala@xilinx.com> + *microblaze.md (define_automaton mbpipe_8): New - * microblaze.md (define_automaton mbpipe_8): New - * microblaze.c (microblaze_option_override): Update - Updated the logic to generate only when MB version is 10.0 - * microblaze.h (pipeline_type): Update - Update the enum with MICROBLAZE_PIPE_8 - * microblaze.opt (mxl-frequency): New - New flag added for 8-stage pipeline + *microblaze.c (microblaze_option_override): Update + Updated the logic to generate only when MB version is 10.0 -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *microblaze.h (pipeline_type): Update + Update the enum with MICROBLAZE_PIPE_8 + + *microblaze.opt (mxl-frequency): New + New flag added for 8-stage pipeline --- gcc/config/microblaze/microblaze.c | 13 ++++++ gcc/config/microblaze/microblaze.h | 3 +- @@ -30,10 +28,10 @@ Upstream-Status: Pending 4 files changed, 96 insertions(+), 3 deletions(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 663b20a022..e7697bf30d 100644 +index daf0269..3832d16 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -1773,6 +1773,19 @@ microblaze_option_override (void) +@@ -1772,6 +1772,19 @@ microblaze_option_override (void) warning (0, "-mxl-reorder requires -mxl-pattern-compare for -mcpu=v8.30.a"); TARGET_REORDER = 0; } @@ -54,7 +52,7 @@ index 663b20a022..e7697bf30d 100644 if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) error ("-mxl-multiply-high requires -mno-xl-soft-mul"); diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 82e7e890be..3f48e48f10 100644 +index 9f74ec8..2ac5aeec 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h @@ -27,7 +27,8 @@ @@ -68,7 +66,7 @@ index 82e7e890be..3f48e48f10 100644 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index b9c62b6d0f..61d6412dac 100644 +index bc675ca..6395533 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -35,6 +35,7 @@ @@ -179,7 +177,7 @@ index b9c62b6d0f..61d6412dac 100644 (set_attr "length" "4")]) diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt -index 8847c3daf8..85a9929d74 100644 +index 8242998..c8e6f00 100644 --- a/gcc/config/microblaze/microblaze.opt +++ b/gcc/config/microblaze/microblaze.opt @@ -129,3 +129,7 @@ Use hardware prefetch instruction @@ -191,5 +189,5 @@ index 8847c3daf8..85a9929d74 100644 +Target Mask(AREA_OPTIMIZED_2) +Use 8 stage pipeline (frequency optimization) -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch new file mode 100644 index 00000000..95b9b2aa --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch @@ -0,0 +1,142 @@ +From 5147c831c6a78d9b95138b679bb2ca7624abc3a1 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 18 Jan 2017 11:08:40 +0530 +Subject: [PATCH 27/54] [Patch,rtl Optimization]: Better register pressure + estimate for loop . .invariant code motion + +Calculate the loop liveness used for regs for calculating the register pressure +in the cost estimation. Loop liveness is based on the following properties. +We only need to find the set of objects that are live at the birth or the header +of the loop. We don't need to calculate the live through the loop by considering +live in and live out of all the basic blocks of the loop. This is based on the +point that the set of objects that are live-in at the birth or header of the loop +will be live-in at every node in the loop. + +If a v live is out at the header of the loop then the variable is live-in at every node +in the loop. To prove this, consider a loop L with header h such that the variable v +defined at d is live-in at h. Since v is live at h, d is not part of L. This follows i +from the dominance property, i.e. h is strictly dominated by d. Furthermore, there +exists a path from h to a use of v which does not go through d. For every node p in +the loop, since the loop is strongly connected and node is a component of the CFG, +there exists a path, consisting only of nodes of L from p to h. Concatenating these +two paths proves that v is live-in and live-out of p. + +Calculate the live-out and live-in for the exit edge of the loop. This patch considers +liveness for not only the loop latch but also the liveness outside the loops. + +ChangeLog: +2016-01-22 Ajit Agarwal <ajitkum@xilinx.com> + + * loop-invariant.c + (find_invariants_to_move): Add the logic of regs_used based + on liveness. + * cfgloopanal.c + (estimate_reg_pressure_cost): Update the heuristics in presence + of call_p. + +Signed-off-by:Ajit Agarwal ajitkum@xilinx.com. +--- + gcc/cfgloopanal.c | 4 +++- + gcc/loop-invariant.c | 63 +++++++++++++++++++++++++++++++++++++++------------- + 2 files changed, 50 insertions(+), 17 deletions(-) + +diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c +index 3af0b2d..123dc6b 100644 +--- a/gcc/cfgloopanal.c ++++ b/gcc/cfgloopanal.c +@@ -411,7 +411,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed, + if (regs_needed + target_res_regs <= available_regs) + return 0; + +- if (regs_needed <= available_regs) ++ if ((regs_needed <= available_regs) ++ || (call_p && (regs_needed <= ++ (available_regs + target_clobbered_regs)))) + /* If we are close to running out of registers, try to preserve + them. */ + cost = target_reg_cost [speed] * n_new; +diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c +index 8e22ca0..c9ec8df 100644 +--- a/gcc/loop-invariant.c ++++ b/gcc/loop-invariant.c +@@ -1520,7 +1520,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed, + size_cost = 0; + } + +- return comp_cost - size_cost; ++ return comp_cost - size_cost + 1; + } + + /* Finds invariant with best gain for moving. Returns the gain, stores +@@ -1614,22 +1614,53 @@ find_invariants_to_move (bool speed, bool call_p) + /* REGS_USED is actually never used when the flag is on. */ + regs_used = 0; + else +- /* We do not really do a good job in estimating number of +- registers used; we put some initial bound here to stand for +- induction variables etc. that we do not detect. */ ++ /* The logic used in estimating the number of regs_used is changed. ++ Now it will be based on liveness of the loop. */ + { +- unsigned int n_regs = DF_REG_SIZE (df); +- +- regs_used = 2; +- +- for (i = 0; i < n_regs; i++) +- { +- if (!DF_REGNO_FIRST_DEF (i) && DF_REGNO_LAST_USE (i)) +- { +- /* This is a value that is used but not changed inside loop. */ +- regs_used++; +- } +- } ++ int i; ++ edge e; ++ vec<edge> edges; ++ bitmap_head regs_live; ++ ++ bitmap_initialize (®s_live, ®_obstack); ++ edges = get_loop_exit_edges (curr_loop); ++ ++ /* Loop liveness is based on the following properties. ++ We only need to find the set of objects that are live at the ++ birth or the header of the loop. ++ We don't need to calculate the live through the loop considering ++ live-in and live-out of all the basic blocks of the loop. This is ++ based on the point that the set of objects that are live-in at the ++ birth or header of the loop will be live-in at every block in the ++ loop. ++ ++ If a v live out at the header of the loop then the variable is ++ live-in at every node in the Loop. To prove this, consider a loop ++ L with header h such that the variable v defined at d is live-in ++ at h. Since v is live at h, d is not part of L. This follows from ++ the dominance property, i.e. h is strictly dominated by d. Furthermore, ++ there exists a path from h to a use of v which does not go through d. ++ For every node of the loop, p, since the loop is strongly connected ++ component of the CFG, there exists a path, consisting only of nodes ++ of L from p to h. Concatenating these two paths prove that v is ++ live-in and live-out of p. */ ++ ++ bitmap_ior_into (®s_live, DF_LR_IN (curr_loop->header)); ++ bitmap_ior_into (®s_live, DF_LR_OUT (curr_loop->header)); ++ ++ /* Calculate the live-out and live-in for the exit edge of the loop. ++ This considers liveness for not only the loop latch but also the ++ liveness outside the loops. */ ++ ++ FOR_EACH_VEC_ELT (edges, i, e) ++ { ++ bitmap_ior_into (®s_live, DF_LR_OUT (e->src)); ++ bitmap_ior_into (®s_live, DF_LR_IN (e->dest)); ++ } ++ ++ regs_used = bitmap_count_bits (®s_live) + 2; ++ bitmap_clear (®s_live); ++ edges.release (); + } + + if (! flag_ira_loop_pressure) +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch new file mode 100644 index 00000000..3643ff19 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch @@ -0,0 +1,69 @@ +From 2715b235b3db423bf35b9304a2ba5daa86b1680e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 18 Jan 2017 11:25:48 +0530 +Subject: [PATCH 28/54] [Patch, microblaze]: Correct the const high double + immediate value With this patch the loading of the DI mode immediate values + will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE + functions, as CONST_DOUBLE_HIGH was returning the sign extension value even + of the unsigned long long constants also + +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> + +ChangeLog: +2016-02-03 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> + + *microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE & + REAL_VALUE_TO_TARGET_DOUBLE + *long.c (new): Added new testcase +--- + gcc/config/microblaze/microblaze.c | 8 ++++++-- + gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++ + 2 files changed, 16 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 3832d16..29cd54f 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2517,14 +2517,18 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; ++ long l[2]; + if (code == CONST_DOUBLE) + { + if (GET_MODE (op) == DFmode) + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); + else + { +- val[0] = CONST_DOUBLE_HIGH (op); +- val[1] = CONST_DOUBLE_LOW (op); ++ REAL_VALUE_TYPE rv; ++ REAL_VALUE_FROM_CONST_DOUBLE (rv, op); ++ REAL_VALUE_TO_TARGET_DOUBLE (rv, l); ++ val[1] = l[WORDS_BIG_ENDIAN == 0]; ++ val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } + else if (code == CONST_INT) +diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c +new file mode 100644 +index 0000000..4d45186 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/microblaze/long.c +@@ -0,0 +1,10 @@ ++/* { dg-options "-O0" } */ ++#define BASEADDR 0xF0000000ULL ++int main () ++{ ++ unsigned long long start; ++ start = (unsigned long long) BASEADDR; ++ return 0; ++} ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */ ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */ +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch new file mode 100644 index 00000000..b4b9d2ec --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch @@ -0,0 +1,36 @@ +From 7e025a0b22eee87bf9597267918bd16fc87c85c2 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 18 Jan 2017 11:49:58 +0530 +Subject: [PATCH 29/54] [Fix, microblaze]: Fix internal compiler error with + msmall-divides This patch will fix the internal error + microblaze_expand_divide function which comes because of rtx PLUS where the + mem_rtx is of type SI and the operand is of type QImode. This patch modifies + the mem_rtx as QImode and Plus as QImode to fix the error. + +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> +ChangeLog: + 2016-02-23 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> + + *microblaze.c (microblaze_expand_divide): Update +--- + gcc/config/microblaze/microblaze.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 29cd54f..f8a417c 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3769,7 +3769,7 @@ microblaze_expand_divide (rtx operands[]) + emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); + emit_insn (gen_addsi3 (regt1, regt1, operands[2])); + mem_rtx = gen_rtx_MEM (QImode, +- gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); ++ gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + + insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch index 97422aea..52fd4bea 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch @@ -1,7 +1,8 @@ -From 34049c9fcaa256befad032cbcd8aa74beecf13dc Mon Sep 17 00:00:00 2001 +From 27a69d1873221747121360d0a1dffc4336a1d0cc Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:47 -0700 -Subject: [PATCH] Fix the calculation of high word in a long long 64-bit +Date: Wed, 18 Jan 2017 12:03:39 +0530 +Subject: [PATCH 30/54] [patch,microblaze]: Fix the calculation of high word in + a long long 6. .4-bit This patch will change the calculation of high word in a long long 64-bit. Earlier to this patch the high word of long long word (0xF0000000ULL) is @@ -11,29 +12,25 @@ removes the condition of checking high word = 0 & low word < 0. This check is not required for the correctness of calculating 32-bit high and low words in a 64-bit long long. -ChangeLog: - -2016-03-01 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> - * config/microblaze/microblaze.c (print_operand): Remove the - condition of checking high word = 0 & low word < 0. - * testsuite/gcc.target/microblaze/others/long.c: Add -O0 option. +ChangeLog: +2016-03-01 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *config/microblaze/microblaze.c (print_operand): Remove the condition of checking + high word = 0 & low word < 0. + *testsuite/gcc.target/microblaze/others/long.c: Add -O0 option. --- gcc/config/microblaze/microblaze.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index a41121264e..2ed64971fb 100644 +index f8a417c..70d8d03 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -2509,9 +2509,6 @@ print_operand (FILE * file, rtx op, int letter) +@@ -2535,9 +2535,6 @@ print_operand (FILE * file, rtx op, int letter) { val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; val[1] = INTVAL (op) & 0x00000000ffffffffLL; @@ -44,5 +41,5 @@ index a41121264e..2ed64971fb 100644 fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); } -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch index 02940e2f..57144523 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch @@ -1,32 +1,26 @@ -From 90b6f833bd59f89d4192a3dc787fc2c9115b9c00 Mon Sep 17 00:00:00 2001 +From 35569bb20a5bb881f7f275d901a0be3408b16622 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:48 -0700 -Subject: [PATCH] Add new bit-field instructions +Date: Wed, 18 Jan 2017 12:14:51 +0530 +Subject: [PATCH 31/54] [Patch, microblaze]: Add new bit-field instructions + This patches adds new bsefi and bsifi instructions. BSEFI- The instruction + shall extract a bit field from a register and place it right-adjusted in the + destination register. The other bits in the destination register shall be set + to zero BSIFI- The instruction shall insert a right-adjusted bit field from a + register at another position in the destination register. The rest of the + bits in the destination register shall be unchanged -This patches adds new bsefi and bsifi instructions. BSEFI- The -instruction shall extract a bit field from a register and place it -right-adjusted in the destination register. The other bits in the -destination register shall be set to zero BSIFI- The instruction shall -insert a right-adjusted bit field from a register at another position in -the destination register. The rest of the bits in the destination -register shall be unchanged +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> ChangeLog: + 2016-02-03 Nagaraju Mekala <nmekala@xilix.com> -2016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - - * microblaze.md (Update): Added new patterns - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *microblaze.md (Update): Added new patterns --- gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 61d6412dac..7a00629922 100644 +index 6395533..5a2dd13 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -980,6 +980,8 @@ @@ -122,5 +116,5 @@ index 61d6412dac..7a00629922 100644 + (include "sync.md") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch index c3e4bc9e..dce1bc58 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch @@ -1,24 +1,21 @@ -From 3eada9d81437d378ef24f11a8bd046fee5b3505a Mon Sep 17 00:00:00 2001 +From 3db8f0c3124d3001d3c10e6d400943f3ec57616b Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:49 -0700 -Subject: [PATCH] Fix bug in MB version calculation +Date: Wed, 18 Jan 2017 12:42:10 +0530 +Subject: [PATCH 32/54] [Patch, microblaze]: Fix bug in MB version calculation + This patch fixes the bug in microblaze_version_to_int function. Earlier the + conversion of vXX.YY.Z to int has a bug which is fixed now. -This patch fixes the bug in microblaze_version_to_int function. Earlier -the conversion of vXX.YY.Z to int has a bug which is fixed now. - -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com> + Nagaraju Mekala <nmekala@xilix.com> --- gcc/config/microblaze/microblaze.c | 147 ++++++++++++++++++------------------- 1 file changed, 70 insertions(+), 77 deletions(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 2ed64971fb..55dba83882 100644 +index 70d8d03..30a0fcf 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -239,6 +239,63 @@ section *sdata2_section; +@@ -238,6 +238,63 @@ section *sdata2_section; #define TARGET_HAVE_TLS true #endif @@ -82,7 +79,7 @@ index 2ed64971fb..55dba83882 100644 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ static bool microblaze_const_double_ok (rtx op, machine_mode mode) -@@ -1267,8 +1324,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, +@@ -1266,8 +1323,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, { if (TARGET_BARREL_SHIFT) { @@ -92,7 +89,7 @@ index 2ed64971fb..55dba83882 100644 *total = COSTS_N_INSNS (1); else *total = COSTS_N_INSNS (2); -@@ -1329,8 +1385,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, +@@ -1328,8 +1384,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, } else if (!TARGET_SOFT_MUL) { @@ -102,7 +99,7 @@ index 2ed64971fb..55dba83882 100644 *total = COSTS_N_INSNS (1); else *total = COSTS_N_INSNS (3); -@@ -1610,72 +1665,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, +@@ -1609,72 +1664,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, return 0; } @@ -176,7 +173,7 @@ index 2ed64971fb..55dba83882 100644 microblaze_section_threshold = (global_options_set.x_g_switch_value ? g_switch_value -@@ -1696,13 +1692,13 @@ microblaze_option_override (void) +@@ -1695,13 +1691,13 @@ microblaze_option_override (void) /* Check the MicroBlaze CPU version for any special action to be done. */ if (microblaze_select_cpu == NULL) microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU; @@ -193,7 +190,7 @@ index 2ed64971fb..55dba83882 100644 if (ver < 0) { /* No hardware exceptions in earlier versions. So no worries. */ -@@ -1713,8 +1709,7 @@ microblaze_option_override (void) +@@ -1712,8 +1708,7 @@ microblaze_option_override (void) microblaze_pipe = MICROBLAZE_PIPE_3; } else if (ver == 0 @@ -203,7 +200,7 @@ index 2ed64971fb..55dba83882 100644 { #if 0 microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY); -@@ -1731,11 +1726,9 @@ microblaze_option_override (void) +@@ -1730,11 +1725,9 @@ microblaze_option_override (void) #endif microblaze_no_unsafe_delay = 0; microblaze_pipe = MICROBLAZE_PIPE_5; @@ -218,7 +215,7 @@ index 2ed64971fb..55dba83882 100644 { /* Pattern compares are to be turned on by default only when compiling for MB v5.00.'z'. */ -@@ -1743,7 +1736,7 @@ microblaze_option_override (void) +@@ -1742,7 +1735,7 @@ microblaze_option_override (void) } } @@ -227,7 +224,7 @@ index 2ed64971fb..55dba83882 100644 if (ver < 0) { if (TARGET_MULTIPLY_HIGH) -@@ -1751,7 +1744,7 @@ microblaze_option_override (void) +@@ -1750,7 +1743,7 @@ microblaze_option_override (void) "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater"); } @@ -236,7 +233,7 @@ index 2ed64971fb..55dba83882 100644 microblaze_has_clz = 1; if (ver < 0) { -@@ -1760,7 +1753,7 @@ microblaze_option_override (void) +@@ -1759,7 +1752,7 @@ microblaze_option_override (void) } /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */ @@ -246,5 +243,5 @@ index 2ed64971fb..55dba83882 100644 { if (TARGET_REORDER == 1) -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch index 1d877be6..15111477 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch @@ -1,23 +1,19 @@ -From 0c740ddd203433ef8d979348c085269f8b97cbfc Mon Sep 17 00:00:00 2001 +From f3e259923788176ebb323155cc089e68c6de0895 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:50 -0700 -Subject: [PATCH] MicroBlaze fixing the bug in the bit-field instruction. +Date: Wed, 18 Jan 2017 13:57:48 +0530 +Subject: [PATCH 33/54] Fixing the bug in the bit-field instruction. Bit field + instruction should be generated only if mcpu >10.0 -Bit field instruction should be generated only if mcpu >10.0 - -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.c | 3 +++ gcc/config/microblaze/microblaze.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 55dba83882..4f6d399bba 100644 +index 30a0fcf..835e906 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -159,6 +159,9 @@ int microblaze_no_unsafe_delay; +@@ -163,6 +163,9 @@ int microblaze_no_unsafe_delay; /* Set to one if the targeted core has the CLZ insn. */ int microblaze_has_clz = 0; @@ -28,7 +24,7 @@ index 55dba83882..4f6d399bba 100644 version having only a particular type of pipeline. There can still be options on the CPU to scale pipeline features up or down. :( diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 3f48e48f10..712525f856 100644 +index 2ac5aeec..991d0f7 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h @@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[]; @@ -48,5 +44,5 @@ index 3f48e48f10..712525f856 100644 /* The default is to support PIC. */ #define TARGET_SUPPORTS_PIC 1 -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch new file mode 100644 index 00000000..f22f2f3f --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch @@ -0,0 +1,32 @@ +From 52cf8e91f06ce9259d4d94bb8ea5cb327825b806 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 18 Jan 2017 20:57:10 +0530 +Subject: [PATCH 34/54] [Patch, microblaze]: Macros used in Xilinx internal + patches has been removed in gcc 6.2 version so modified the code accordingly. + +--- + gcc/config/microblaze/microblaze.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 835e906..2e3b4c9 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2520,11 +2520,9 @@ print_operand (FILE * file, rtx op, int letter) + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); + else + { +- REAL_VALUE_TYPE rv; +- REAL_VALUE_FROM_CONST_DOUBLE (rv, op); +- REAL_VALUE_TO_TARGET_DOUBLE (rv, l); +- val[1] = l[WORDS_BIG_ENDIAN == 0]; +- val[0] = l[WORDS_BIG_ENDIAN != 0]; ++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); ++ val[1] = l[WORDS_BIG_ENDIAN == 0]; ++ val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } + else if (code == CONST_INT) +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch index 3786a71a..00d67bcf 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch @@ -1,21 +1,17 @@ -From fdb99f97b41f7cd06b81e668b88463d0fc2cbe87 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:54 -0700 -Subject: [PATCH] Fixing the issue with MicroBlaze builtin_alloc +From 727b0f7ae03279177559f5d85d8920352bd853b2 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Thu, 23 Feb 2017 17:09:04 +0530 +Subject: [PATCH 35/54] Fixing the issue with the builtin_alloc. register r18 + was not properly handling the stack pattern which was resolved by using free + available register -Fixing the issue with the builtin_alloc. Register r18 was not properly -handling the stack pattern which was resolved by using free available -register - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +signed-off-by:nagaraju mekala <nmekala@xilinx.com> --- gcc/config/microblaze/microblaze.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 7a00629922..68c3b22bd4 100644 +index 5a2dd13..8072ffc 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -2076,10 +2076,10 @@ @@ -44,5 +40,5 @@ index 7a00629922..68c3b22bd4 100644 } ) -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch new file mode 100644 index 00000000..54ccd9a0 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch @@ -0,0 +1,49 @@ +From 7156e379a67fa47a5fb9ede1448c0d528dbda65b Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Thu, 2 Mar 2017 19:02:31 +0530 +Subject: [PATCH 36/54] [Patch,Microblaze]:reverting the cost check before + propagating constants. + +--- + gcc/cprop.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/cprop.c b/gcc/cprop.c +index e4df509..deb706b 100644 +--- a/gcc/cprop.c ++++ b/gcc/cprop.c +@@ -733,6 +733,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + int success = 0; + rtx set = single_set (insn); + ++#if 0 + bool check_rtx_costs = true; + bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); + int old_cost = set ? set_rtx_cost (set, speed) : 0; +@@ -744,6 +745,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + && (GET_CODE (XEXP (note, 0)) == CONST + || CONSTANT_P (XEXP (note, 0))))) + check_rtx_costs = false; ++#endif + + /* Usually we substitute easy stuff, so we won't copy everything. + We however need to take care to not duplicate non-trivial CONST +@@ -752,6 +754,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + + validate_replace_src_group (from, to, insn); + ++#if 0 + /* If TO is a constant, check the cost of the set after propagation + to the cost of the set before the propagation. If the cost is + higher, then do not replace FROM with TO. */ +@@ -764,6 +767,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + return false; + } + ++#endif + + if (num_changes_pending () && apply_change_group ()) + success = 1; +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch index 29bc752e..26b685a5 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch @@ -1,30 +1,25 @@ -From 646fe1dbaca06f2fe2df4c0da3fa20e0aff0a4ec Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:56 -0700 -Subject: [PATCH] MicroBlaze remove bitfield instructions macros +From 149cf4619622d27641a2886cd8bf38a49ad88f87 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 19 Feb 2018 18:06:16 +0530 +Subject: [PATCH 37/54] [Patch,Microblaze]: update in constraints for bitfield + insert and extract instructions. -Remove the conditions in the bit field expand macros to generate the -instructions in structure bit-field usecases - -ChangeLog: - -2018-08-16 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - - * gcc/config/microblaze/microblaze.md: - remove the expand constraints - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- - gcc/config/microblaze/microblaze.md | 40 +++++-------------------------------- - 1 file changed, 5 insertions(+), 35 deletions(-) + gcc/config/microblaze/microblaze.md | 43 ++++++------------------------------- + 1 file changed, 7 insertions(+), 36 deletions(-) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 68c3b22bd4..ef53c3069e 100644 +index 8072ffc..9bb87ec 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md -@@ -2482,25 +2482,8 @@ +@@ -2476,33 +2476,17 @@ + DONE; + }") + +-(define_expand "extvsi" ++(define_expand "extzvsi" + [(set (match_operand:SI 0 "register_operand" "r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "I") (match_operand:SI 3 "immediate_operand" "I")))] "TARGET_HAS_BITFIELD" @@ -50,13 +45,16 @@ index 68c3b22bd4..ef53c3069e 100644 +"" +) - (define_insn "extv_32" +-(define_insn "extv_32" ++ ++(define_insn "extzv_32" [(set (match_operand:SI 0 "register_operand" "=r") -@@ -2518,22 +2501,9 @@ - (match_operand:SI 1 "immediate_operand" "I") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "I") +@@ -2519,21 +2503,8 @@ (match_operand:SI 2 "immediate_operand" "I")) (match_operand:SI 3 "register_operand" "r"))] -- "TARGET_HAS_BITFIELD" + "TARGET_HAS_BITFIELD" - " -{ - unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); @@ -72,12 +70,11 @@ index 68c3b22bd4..ef53c3069e 100644 - operands[2], operands[3])); - DONE; -}") -+"TARGET_HAS_BITFIELD" +"" +) (define_insn "insv_32" [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch new file mode 100644 index 00000000..d8ae6c15 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch @@ -0,0 +1,38 @@ +From 5494699756f8e1dba6848fcf09780a031139c232 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 4 Jun 2018 10:10:18 +0530 +Subject: [PATCH 38/54] [Patch,Microblaze] : Removed fsqrt generation for + double values. + +--- + gcc/config/microblaze/microblaze.md | 14 -------------- + 1 file changed, 14 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 9bb87ec..a93ddd0 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -524,20 +524,6 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +-(define_insn "sqrtdf2" +- [(set (match_operand:DF 0 "register_operand" "=d") +- (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] +- "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" +- { +- if (REGNO (operands[0]) == REGNO (operands[1])) +- return "fsqrt\t%0,%1"; +- else +- return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; +- } +- [(set_attr "type" "fsqrt") +- (set_attr "mode" "SF") +- (set_attr "length" "4")]) +- + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch new file mode 100644 index 00000000..88497a8e --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch @@ -0,0 +1,810 @@ +From 6e8b37bf54646c38fb4071d542a60ea92715df9b Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 3 Apr 2018 16:48:39 +0530 +Subject: [PATCH 39/54] Intial commit of 64-bit Microblaze + +--- + gcc/config/microblaze/microblaze-protos.h | 1 + + gcc/config/microblaze/microblaze.c | 109 +++++++-- + gcc/config/microblaze/microblaze.h | 4 +- + gcc/config/microblaze/microblaze.md | 370 +++++++++++++++++++++++++++++- + gcc/config/microblaze/microblaze.opt | 9 +- + gcc/config/microblaze/t-microblaze | 7 +- + 6 files changed, 461 insertions(+), 39 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index c39e2e9..a5ed62e 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -35,6 +35,7 @@ extern void microblaze_expand_divide (rtx *); + extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_sf (rtx *); ++extern void microblaze_expand_conditional_branch_df (rtx *); + extern int microblaze_can_use_return_insn (void); + extern void print_operand (FILE *, rtx, int); + extern void print_operand_address (FILE *, rtx); +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 2e3b4c9..2079ae9 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3457,11 +3457,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) + op0 = operands[0]; + op1 = operands[1]; + +- if (!register_operand (op0, SImode) +- && !register_operand (op1, SImode) ++ if (!register_operand (op0, mode) ++ && !register_operand (op1, mode) + && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0)) + { +- rtx temp = force_reg (SImode, op1); ++ rtx temp = force_reg (mode, op1); + emit_move_insn (op0, temp); + return true; + } +@@ -3499,12 +3499,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) + && (flag_pic == 2 || microblaze_tls_symbol_p (p0) + || !SMALL_INT (p1))))) + { +- rtx temp = force_reg (SImode, p0); ++ rtx temp = force_reg (mode, p0); + rtx temp2 = p1; + + if (flag_pic && reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); +- emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2)); ++ emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2)); + return true; + } + } +@@ -3635,7 +3635,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + rtx cmp_op0 = operands[1]; + rtx cmp_op1 = operands[2]; + rtx label1 = operands[3]; +- rtx comp_reg = gen_reg_rtx (SImode); ++ rtx comp_reg = gen_reg_rtx (mode); + rtx condition; + + gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); +@@ -3644,23 +3644,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + if (cmp_op1 == const0_rtx) + { + comp_reg = cmp_op0; +- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); ++ + } + + else if (code == EQ || code == NE) + { + /* Use xor for equal/not-equal comparison. */ +- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); +- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); ++ else ++ emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); ++ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else + { + /* Generate compare and branch in single instruction. */ + cmp_op1 = force_reg (mode, cmp_op1); + condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); +- emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); ++ if (mode == SImode) ++ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); ++ else ++ emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1)); + } + } + +@@ -3671,7 +3684,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + rtx cmp_op0 = operands[1]; + rtx cmp_op1 = operands[2]; + rtx label1 = operands[3]; +- rtx comp_reg = gen_reg_rtx (SImode); ++ rtx comp_reg = gen_reg_rtx (mode); + rtx condition; + + gcc_assert ((GET_CODE (cmp_op0) == REG) +@@ -3682,30 +3695,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), +- SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else if (code == EQ) + { +- emit_insn (gen_seq_internal_pat (comp_reg, +- cmp_op0, cmp_op1)); +- condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ { ++ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ else ++ { ++ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); ++ + } + else if (code == NE) + { +- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, +- cmp_op1)); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ { ++ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ else ++ { ++ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ condition = gen_rtx_NE (mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else + { + /* Generate compare and branch in single instruction. */ + cmp_op1 = force_reg (mode, cmp_op1); + condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); +- emit_jump_insn (gen_branch_compare (condition, cmp_op0, +- cmp_op1, label1)); ++ if (mode == SImode) ++ emit_jump_insn (gen_branch_compare (condition, cmp_op0, ++ cmp_op1, label1)); ++ else ++ { ++ emit_jump_insn (gen_long_branch_compare (condition, cmp_op0, ++ cmp_op1, label1)); ++ } ++ + } + } + +@@ -3722,6 +3768,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) + emit_jump_insn (gen_condjump (condition, operands[3])); + } + ++void ++microblaze_expand_conditional_branch_df (rtx operands[]) ++{ ++ rtx condition; ++ rtx cmp_op0 = XEXP (operands[0], 0); ++ rtx cmp_op1 = XEXP (operands[0], 1); ++ rtx comp_reg = gen_reg_rtx (DImode); ++ ++ emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); ++ condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); ++ emit_jump_insn (gen_long_condjump (condition, operands[3])); ++} ++ + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ + + static bool +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 991d0f7..72fbee5 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe; + #define ASM_SPEC "\ + %(target_asm_spec) \ + %{mbig-endian:-EB} \ ++%{m64:-m64} \ + %{mlittle-endian:-EL}" + + /* Extra switches sometimes passed to the linker. */ +@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe; + #define LINK_SPEC "%{shared:-shared} -N -relax \ + %{mbig-endian:-EB --oformat=elf32-microblaze} \ + %{mlittle-endian:-EL --oformat=elf32-microblazeel} \ ++ %{m64:-EL --oformat=elf64-microblazeel} \ + %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \ +@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe; + #define MIN_UNITS_PER_WORD 4 + #define INT_TYPE_SIZE 32 + #define SHORT_TYPE_SIZE 16 +-#define LONG_TYPE_SIZE 32 ++#define LONG_TYPE_SIZE 64 + #define LONG_LONG_TYPE_SIZE 64 + #define FLOAT_TYPE_SIZE 32 + #define DOUBLE_TYPE_SIZE 64 +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index a93ddd0..6976b37 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -495,7 +495,6 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +- + (define_insn "divsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (div:SF (match_operand:SF 1 "register_operand" "d") +@@ -506,6 +505,7 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++ + (define_insn "sqrtsf2" + [(set (match_operand:SF 0 "register_operand" "=d") + (sqrt:SF (match_operand:SF 1 "register_operand" "d")))] +@@ -560,6 +560,18 @@ + + ;; Adding 2 DI operands in register or reg/imm + ++(define_insn "adddi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") ++ (match_operand:DI 2 "arith_plus_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ addlk\t%0,%z1,%2 ++ addlik\t%0,%z1,%2" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "adddi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") +@@ -604,6 +616,18 @@ + ;; Double Precision Subtraction + ;;---------------------------------------------------------------- + ++(define_insn "subdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "register_operand" "d,n")))] ++ "TARGET_MB_64" ++ "@ ++ rsubl\t%0,%2,%1 ++ addlik\t%0,%z1,-%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "subdi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") +@@ -793,6 +817,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "negdi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (neg:DI (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "rsubl\t%0,%1,r0" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "negdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -812,6 +845,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "one_cmpldi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (not:DI (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "xorli\t%0,%1,-1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "*one_cmpldi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -838,6 +880,20 @@ + ;; Logical + ;;---------------------------------------------------------------- + ++(define_insn "anddi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (and:DI (match_operand:DI 1 "arith_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ andl\t%0,%1,%2 ++ andli\t%0,%1,%2 #andl1" ++ ;; andli\t%0,%1,%2 #andl3 ++ ;; andli\t%0,%1,%2 #andl2 ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") +@@ -853,6 +909,18 @@ + (set_attr "length" "4,8,8,8")]) + + ++(define_insn "iordi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ior:DI (match_operand:DI 1 "arith_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ orl\t%0,%1,%2 ++ orli\t%0,%1,%2 #andl1" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "iorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") +@@ -867,6 +935,19 @@ + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + ++(define_insn "xordi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ xorl\t%0,%1,%2 ++ xorli\t%0,%1,%2 #andl1" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ ++ + (define_insn "xorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") +@@ -935,6 +1016,26 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++;;(define_expand "extendqidi2" ++;; [(set (match_operand:DI 0 "register_operand" "=d") ++;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] ++;; "TARGET_MB_64" ++;; { ++;; if (GET_CODE (operands[1]) != REG) ++;; FAIL; ++;; } ++;;) ++ ++ ++;;(define_insn "extendqidi2" ++;; [(set (match_operand:DI 0 "register_operand" "=d") ++;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] ++;; "TARGET_MB_64" ++;; "sextl8\t%0,%1" ++;; [(set_attr "type" "arith") ++;; (set_attr "mode" "DI") ++;; (set_attr "length" "4")]) ++ + (define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] +@@ -944,6 +1045,16 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "extendhidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "sextl16\t%0,%1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++ + ;; Those for integer source operand are ordered + ;; widest source type first. + +@@ -1009,7 +1120,6 @@ + ) + + +- + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") + (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] +@@ -1421,6 +1531,36 @@ + (set_attr "length" "4,4")] + ) + ++;; Barrel shift left ++(define_expand "ashldi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "ashldi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bsllli\t%0,%1,%2 ++ bslll\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++) + ;; The following patterns apply when there is no barrel shifter present + + (define_insn "*ashlsi3_with_mul_delay" +@@ -1546,6 +1686,36 @@ + ;;---------------------------------------------------------------- + ;; 32-bit right shifts + ;;---------------------------------------------------------------- ++;; Barrel shift left ++(define_expand "ashrdi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "ashrdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bslrai\t%0,%1,%2 ++ bslra\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++ ) + (define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -1655,6 +1825,36 @@ + ;;---------------------------------------------------------------- + ;; 32-bit right shifts (logical) + ;;---------------------------------------------------------------- ++;; Barrel shift left ++(define_expand "lshrdi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "lshrdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bslrli\t%0,%1,%2 ++ bslrl\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++ ) + + (define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") +@@ -1801,6 +2001,8 @@ + (set_attr "length" "4")] + ) + ++ ++ + ;;---------------------------------------------------------------- + ;; Setting a register from an floating point comparison. + ;;---------------------------------------------------------------- +@@ -1816,6 +2018,18 @@ + (set_attr "length" "4")] + ) + ++(define_insn "cstoredf4" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (match_operator:DI 1 "ordered_comparison_operator" ++ [(match_operand:DF 2 "register_operand" "r") ++ (match_operand:DF 3 "register_operand" "r")]))] ++ "TARGET_MB_64" ++ "dcmp.%C1\t%0,%3,%2" ++ [(set_attr "type" "fcmp") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")] ++) ++ + ;;---------------------------------------------------------------- + ;; Conditional branches + ;;---------------------------------------------------------------- +@@ -1928,6 +2142,115 @@ + (set_attr "length" "12")] + ) + ++ ++(define_expand "cbranchdi4" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "arith_operand" "I,i")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch (DImode, operands); ++ DONE; ++}) ++ ++(define_expand "cbranchdi4_reg" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "register_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch_reg (DImode, operands); ++ DONE; ++}) ++ ++(define_expand "cbranchdf4" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DF 1 "register_operand") ++ (match_operand:DF 2 "register_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch_df (operands); ++ DONE; ++ ++}) ++ ++;; Used to implement comparison instructions ++(define_expand "long_condjump" ++ [(set (pc) ++ (if_then_else (match_operand 0) ++ (label_ref (match_operand 1)) ++ (pc)))]) ++ ++(define_insn "long_branch_zero" ++ [(set (pc) ++ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand:DI 2 "pc_or_label_operand" "") ++ (match_operand:DI 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "beal%C0i%?\t%z1,%2"; ++ else ++ return "beal%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "long_branch_compare" ++ [(set (pc) ++ (if_then_else (match_operator:DI 0 "cmp_op" ++ [(match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:DI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); ++ return "beal%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- +@@ -2462,17 +2785,33 @@ + DONE; + }") + +-(define_expand "extzvsi" ++(define_expand "extvsi" + [(set (match_operand:SI 0 "register_operand" "r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "I") + (match_operand:SI 3 "immediate_operand" "I")))] + "TARGET_HAS_BITFIELD" +-"" +-) +- ++" ++{ ++ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); ++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); ++ ++ if ((len == 0) || (pos + len > 32) ) ++ FAIL; ++ ++ ;;if (!register_operand (operands[1], VOIDmode)) ++ ;; FAIL; ++ if (operands[0] == operands[1]) ++ FAIL; ++ if (GET_CODE (operands[1]) == ASHIFT) ++ FAIL; ++;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); ++ emit_insn (gen_extv_32 (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}") + +-(define_insn "extzv_32" ++(define_insn "extv_32" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "I") +@@ -2489,8 +2828,21 @@ + (match_operand:SI 2 "immediate_operand" "I")) + (match_operand:SI 3 "register_operand" "r"))] + "TARGET_HAS_BITFIELD" +-"" +-) ++ " ++{ ++ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); ++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); ++ ++ if (len <= 0 || pos + len > 32) ++ FAIL; ++ ++ ;;if (!register_operand (operands[0], VOIDmode)) ++ ;; FAIL; ++ ++ emit_insn (gen_insv_32 (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}") + + (define_insn "insv_32" + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") +diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt +index c8e6f00..cdcae00 100644 +--- a/gcc/config/microblaze/microblaze.opt ++++ b/gcc/config/microblaze/microblaze.opt +@@ -125,11 +125,16 @@ Description for mxl-mode-novectors. + + mxl-prefetch + Target Mask(PREFETCH) +-Use hardware prefetch instruction ++Use hardware prefetch instruction. + + mxl-mode-xilkernel + Target + + mxl-frequency + Target Mask(AREA_OPTIMIZED_2) +-Use 8 stage pipeline (frequency optimization) ++Use 8 stage pipeline (frequency optimization). ++ ++m64 ++Target Mask(MB_64) ++MicroBlaze 64-bit mode. ++ +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 41fa9a9..e9a1921 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,8 +1,11 @@ +-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian +-MULTILIB_DIRNAMES = bs m mh le ++MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 ++MULTILIB_DIRNAMES = bs m mh le m64 + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian ++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch new file mode 100644 index 00000000..1157a82f --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch @@ -0,0 +1,83 @@ +From 5526d87787d61990be3187b230fae4d0591d0651 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Wed, 4 Apr 2018 16:41:41 +0530 +Subject: [PATCH 40/54] Added load store pattern movdi and also adding missing + files + +--- + gcc/config/microblaze/constraints.md | 5 +++++ + gcc/config/microblaze/microblaze.md | 26 ++++++++++++++++++++++++++ + gcc/config/microblaze/t-microblaze | 4 ++-- + 3 files changed, 33 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index ae14944..a06b4d8 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -52,6 +52,11 @@ + (and (match_code "const_int") + (match_test "ival > 0 && ival < 0x10000"))) + ++(define_constraint "K" ++ "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." ++ (and (match_code "const_int") ++ (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) ++ + ;; Define floating point constraints + + (define_constraint "G" +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 6976b37..0cd0441 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1120,6 +1120,32 @@ + ) + + ++(define_insn "*movdi_internal_64" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") ++ (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] ++ "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1"; ++ case 1: ++ return "addlik\t%0,r0,%1"; ++ case 2: ++ return "addlk\t%0,r0,r0"; ++ case 3: ++ case 4: ++ return "lli\t%0,%1"; ++ case 5: ++ case 6: ++ return "sli\t%1,%0"; ++ } ++ return "unreachable"; ++ } ++ [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8,8,8,8,12,8,12")]) ++ + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") + (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index e9a1921..7671f63 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -4,8 +4,8 @@ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 +-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 ++#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 ++#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch new file mode 100644 index 00000000..411958e7 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch @@ -0,0 +1,2463 @@ +From eee9b7f7423823b133d6a5e5382863502433bdc6 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 27 Jul 2018 15:23:41 +0530 +Subject: [PATCH 41/54] Intial commit for 64bit-MB sources. Need to cleanup the + code later. + +--- + gcc/config/microblaze/constraints.md | 2 +- + gcc/config/microblaze/microblaze-c.c | 6 + + gcc/config/microblaze/microblaze.c | 218 ++++++++---- + gcc/config/microblaze/microblaze.h | 63 ++-- + gcc/config/microblaze/microblaze.md | 606 ++++++++++++++++++++++++-------- + gcc/config/microblaze/t-microblaze | 7 +- + libgcc/config/microblaze/crti.S | 4 +- + libgcc/config/microblaze/crtn.S | 4 +- + libgcc/config/microblaze/divdi3.S | 98 ++++++ + libgcc/config/microblaze/divdi3_table.c | 62 ++++ + libgcc/config/microblaze/moddi3.S | 97 +++++ + libgcc/config/microblaze/muldi3.S | 73 ++++ + libgcc/config/microblaze/t-microblaze | 11 +- + libgcc/config/microblaze/udivdi3.S | 107 ++++++ + libgcc/config/microblaze/umoddi3.S | 110 ++++++ + 15 files changed, 1232 insertions(+), 236 deletions(-) + create mode 100644 libgcc/config/microblaze/divdi3.S + create mode 100644 libgcc/config/microblaze/divdi3_table.c + create mode 100644 libgcc/config/microblaze/moddi3.S + create mode 100644 libgcc/config/microblaze/muldi3.S + create mode 100644 libgcc/config/microblaze/udivdi3.S + create mode 100644 libgcc/config/microblaze/umoddi3.S + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index a06b4d8..867a7b5 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -55,7 +55,7 @@ + (define_constraint "K" + "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." + (and (match_code "const_int") +- (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) ++ (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) + + ;; Define floating point constraints + +diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c +index 7b020b5..d8a1d13 100644 +--- a/gcc/config/microblaze/microblaze-c.c ++++ b/gcc/config/microblaze/microblaze-c.c +@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile) + builtin_define ("HAVE_HW_FPU_SQRT"); + builtin_define ("__HAVE_HW_FPU_SQRT__"); + } ++ if (TARGET_MB_64) ++ { ++ builtin_define ("__arch64__"); ++ builtin_define ("__microblaze64__"); ++ builtin_define ("__MICROBLAZE64__"); ++ } + } +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 2079ae9..ba7ade4 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -382,10 +382,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) + { + return 1; + } +- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) ++ /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) + { + return 1; +- } ++ }*/ + else + return 0; + +@@ -433,7 +433,7 @@ double_memory_operand (rtx op, machine_mode mode) + return 1; + + return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT +- ? E_SImode : E_SFmode), ++ ? Pmode : E_SFmode), + plus_constant (Pmode, addr, 4)); + } + +@@ -680,7 +680,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg) + /* Load the addend. */ + addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)), + UNSPEC_TLS); +- addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); ++ addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend)); + dest = gen_rtx_PLUS (Pmode, dest, addend); + break; + +@@ -698,7 +698,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x) + + if (XINT (x, 1) == UNSPEC_GOTOFF) + { +- info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM); ++ info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); + info->type = ADDRESS_GOTOFF; + } + else if (XINT (x, 1) == UNSPEC_PLT) +@@ -1230,8 +1230,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) + emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES)); + + /* Emit the test & branch. */ +- emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src), ++ ++ if (TARGET_MB_64) { ++ emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src), ++ src_reg, final_src, label)); ++ } ++ else { ++ emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src), + src_reg, final_src, label)); ++ ++ } + + /* Mop up any left-over bytes. */ + if (leftover) +@@ -1561,14 +1569,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v, + break; + + case E_DFmode: +- cum->arg_words += 2; ++ if (TARGET_MB_64) ++ cum->arg_words++; ++ else ++ cum->arg_words += 2; + if (!cum->gp_reg_found && cum->arg_number <= 2) + cum->fp_code += 2 << ((cum->arg_number - 1) * 2); + break; + + case E_DImode: + cum->gp_reg_found = 1; +- cum->arg_words += 2; ++ if (TARGET_MB_64) ++ cum->arg_words++; ++ else ++ cum->arg_words += 2; + break; + + case E_QImode: +@@ -2219,7 +2233,7 @@ compute_frame_size (HOST_WIDE_INT size) + + if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM) + /* Don't account for link register. It is accounted specially below. */ +- gp_reg_size += GET_MODE_SIZE (SImode); ++ gp_reg_size += GET_MODE_SIZE (Pmode); + + mask |= (1L << (regno - GP_REG_FIRST)); + } +@@ -2487,7 +2501,7 @@ print_operand (FILE * file, rtx op, int letter) + + if ((letter == 'M' && !WORDS_BIG_ENDIAN) + || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D') +- regnum++; ++ regnum++; + + fprintf (file, "%s", reg_names[regnum]); + } +@@ -2513,6 +2527,7 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; ++ int val1[2]; + long l[2]; + if (code == CONST_DOUBLE) + { +@@ -2525,12 +2540,12 @@ print_operand (FILE * file, rtx op, int letter) + val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } +- else if (code == CONST_INT) ++ else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) + { +- val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; +- val[1] = INTVAL (op) & 0x00000000ffffffffLL; ++ val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; ++ val1[1] = INTVAL (op) & 0x00000000ffffffffLL; + } +- fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); ++ fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); + } + else if (code == CONST_DOUBLE) + { +@@ -2713,7 +2728,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -2736,7 +2754,10 @@ microblaze_asm_destructor (rtx symbol, int priority) + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -2802,7 +2823,7 @@ save_restore_insns (int prologue) + /* For interrupt_handlers, need to save/restore the MSR. */ + if (microblaze_is_interrupt_variant ()) + { +- isr_mem_rtx = gen_rtx_MEM (SImode, ++ isr_mem_rtx = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, base_reg_rtx, + GEN_INT (current_frame_info. + gp_offset - +@@ -2810,8 +2831,8 @@ save_restore_insns (int prologue) + + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (isr_mem_rtx) = 1; +- isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG); +- isr_msr_rtx = gen_rtx_REG (SImode, ST_REG); ++ isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG); ++ isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG); + } + + if (microblaze_is_interrupt_variant () && !prologue) +@@ -2819,8 +2840,8 @@ save_restore_insns (int prologue) + emit_move_insn (isr_reg_rtx, isr_mem_rtx); + emit_move_insn (isr_msr_rtx, isr_reg_rtx); + /* Do not optimize in flow analysis. */ +- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); +- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); + } + + for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) +@@ -2831,9 +2852,9 @@ save_restore_insns (int prologue) + /* Don't handle here. Already handled as the first register. */ + continue; + +- reg_rtx = gen_rtx_REG (SImode, regno); ++ reg_rtx = gen_rtx_REG (Pmode, regno); + insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset)); +- mem_rtx = gen_rtx_MEM (SImode, insn); ++ mem_rtx = gen_rtx_MEM (Pmode, insn); + if (microblaze_is_interrupt_variant () || save_volatiles) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; +@@ -2848,7 +2869,7 @@ save_restore_insns (int prologue) + insn = emit_move_insn (reg_rtx, mem_rtx); + } + +- gp_offset += GET_MODE_SIZE (SImode); ++ gp_offset += GET_MODE_SIZE (Pmode); + } + } + +@@ -2858,8 +2879,8 @@ save_restore_insns (int prologue) + emit_move_insn (isr_mem_rtx, isr_reg_rtx); + + /* Do not optimize in flow analysis. */ +- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); +- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); + } + + /* Done saving and restoring */ +@@ -2949,7 +2970,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) + + switch_to_section (s); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -3095,10 +3119,10 @@ microblaze_expand_prologue (void) + { + if (offset != 0) + ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); +- emit_move_insn (gen_rtx_MEM (SImode, ptr), +- gen_rtx_REG (SImode, regno)); ++ emit_move_insn (gen_rtx_MEM (Pmode, ptr), ++ gen_rtx_REG (Pmode, regno)); + +- offset += GET_MODE_SIZE (SImode); ++ offset += GET_MODE_SIZE (Pmode); + } + + } +@@ -3108,15 +3132,23 @@ microblaze_expand_prologue (void) + rtx fsiz_rtx = GEN_INT (fsiz); + + rtx_insn *insn = NULL; +- insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ if (TARGET_MB_64) ++ { ++ ++ insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, + fsiz_rtx)); ++ } ++ else { ++ insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ fsiz_rtx)); ++ } + if (insn) + RTX_FRAME_RELATED_P (insn) = 1; + + /* Handle SUB_RETURN_ADDR_REGNUM specially at first. */ + if (!crtl->is_leaf || interrupt_handler) + { +- mem_rtx = gen_rtx_MEM (SImode, ++ mem_rtx = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, + const0_rtx)); + +@@ -3124,7 +3156,7 @@ microblaze_expand_prologue (void) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + +- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } +@@ -3224,12 +3256,12 @@ microblaze_expand_epilogue (void) + if (!crtl->is_leaf || interrupt_handler) + { + mem_rtx = +- gen_rtx_MEM (SImode, ++ gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); + if (interrupt_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; +- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + emit_move_insn (reg_rtx, mem_rtx); + } + +@@ -3245,15 +3277,25 @@ microblaze_expand_epilogue (void) + /* _restore_ registers for epilogue. */ + save_restore_insns (0); + emit_insn (gen_blockage ()); +- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); ++ else ++ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); + } + + if (crtl->calls_eh_return) +- emit_insn (gen_addsi3 (stack_pointer_rtx, ++ if (TARGET_MB_64) { ++ emit_insn (gen_adddi3 (stack_pointer_rtx, + stack_pointer_rtx, +- gen_raw_REG (SImode, ++ gen_raw_REG (Pmode, + MB_EH_STACKADJ_REGNUM))); +- ++ } ++ else { ++ emit_insn (gen_addsi3 (stack_pointer_rtx, ++ stack_pointer_rtx, ++ gen_raw_REG (Pmode, ++ MB_EH_STACKADJ_REGNUM))); ++ } + emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST + + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + } +@@ -3402,9 +3444,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + else + this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); + +- /* Apply the constant offset, if required. */ ++ /* Apply the constant offset, if required. */ + if (delta) +- emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ { ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ else ++ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ } + + /* Apply the offset from the vtable, if required. */ + if (vcall_offset) +@@ -3417,7 +3464,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); + emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); + +- emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1)); ++ else ++ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); + } + + /* Generate a tail call to the target function. */ +@@ -3564,7 +3614,7 @@ microblaze_eh_return (rtx op0) + /* Queue an .ident string in the queue of top-level asm statements. + If the string size is below the threshold, put it into .sdata2. + If the front-end is done, we must be being called from toplev.c. +- In that case, do nothing. */ ++ In that case, do nothing. */ + void + microblaze_asm_output_ident (const char *string) + { +@@ -3619,9 +3669,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + emit_block_move (m_tramp, assemble_trampoline_template (), + GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL); + +- mem = adjust_address (m_tramp, SImode, 16); ++ mem = adjust_address (m_tramp, Pmode, 16); + emit_move_insn (mem, chain_value); +- mem = adjust_address (m_tramp, SImode, 20); ++ mem = adjust_address (m_tramp, Pmode, 20); + emit_move_insn (mem, fnaddr); + } + +@@ -3645,7 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == SImode) ++ if (mode == Pmode) + emit_jump_insn (gen_condjump (condition, label1)); + else + emit_jump_insn (gen_long_condjump (condition, label1)); +@@ -3764,7 +3814,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) + rtx comp_reg = gen_reg_rtx (SImode); + + emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); ++ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); + emit_jump_insn (gen_condjump (condition, operands[3])); + } + +@@ -3774,10 +3824,10 @@ microblaze_expand_conditional_branch_df (rtx operands[]) + rtx condition; + rtx cmp_op0 = XEXP (operands[0], 0); + rtx cmp_op1 = XEXP (operands[0], 1); +- rtx comp_reg = gen_reg_rtx (DImode); ++ rtx comp_reg = gen_reg_rtx (Pmode); + + emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); +- condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); ++ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); + emit_jump_insn (gen_long_condjump (condition, operands[3])); + } + +@@ -3798,8 +3848,8 @@ microblaze_expand_divide (rtx operands[]) + { + /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ + +- rtx regt1 = gen_reg_rtx (SImode); +- rtx reg18 = gen_rtx_REG (SImode, R_TMP); ++ rtx regt1 = gen_reg_rtx (Pmode); ++ rtx reg18 = gen_rtx_REG (Pmode, R_TMP); + rtx regqi = gen_reg_rtx (QImode); + rtx_code_label *div_label = gen_label_rtx (); + rtx_code_label *div_end_label = gen_label_rtx (); +@@ -3807,17 +3857,31 @@ microblaze_expand_divide (rtx operands[]) + rtx mem_rtx; + rtx ret; + rtx_insn *jump, *cjump, *insn; +- +- insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); +- cjump = emit_jump_insn_after (gen_cbranchsi4 ( +- gen_rtx_GTU (SImode, regt1, GEN_INT (15)), ++ ++ if (TARGET_MB_64) { ++ insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2])); ++ cjump = emit_jump_insn_after (gen_cbranchdi4 ( ++ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), ++ regt1, GEN_INT (15), div_label), insn); ++ } ++ else { ++ insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); ++ cjump = emit_jump_insn_after (gen_cbranchsi4 ( ++ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), + regt1, GEN_INT (15), div_label), insn); ++ } + LABEL_NUSES (div_label) = 1; + JUMP_LABEL (cjump) = div_label; +- emit_insn (gen_rtx_CLOBBER (SImode, reg18)); ++ emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); + +- emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); +- emit_insn (gen_addsi3 (regt1, regt1, operands[2])); ++ if (TARGET_MB_64) { ++ emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_adddi3 (regt1, regt1, operands[2])); ++ } ++ else { ++ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_addsi3 (regt1, regt1, operands[2])); ++ } + mem_rtx = gen_rtx_MEM (QImode, + gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + +@@ -3964,7 +4028,7 @@ insert_wic_for_ilb_runout (rtx_insn *first) + { + insn = + emit_insn_before (gen_iprefetch +- (gen_int_mode (addr_offset, SImode)), ++ (gen_int_mode (addr_offset, Pmode)), + before_4); + recog_memoized (insn); + INSN_LOCATION (insn) = INSN_LOCATION (before_4); +@@ -3974,7 +4038,27 @@ insert_wic_for_ilb_runout (rtx_insn *first) + } + } + } +- ++ ++/* Set the names for various arithmetic operations according to the ++ * MICROBLAZE ABI. */ ++static void ++microblaze_init_libfuncs (void) ++{ ++ set_optab_libfunc (smod_optab, SImode, "__modsi3"); ++ set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); ++ set_optab_libfunc (smul_optab, SImode, "__mulsi3"); ++ set_optab_libfunc (umod_optab, SImode, "__umodsi3"); ++ set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); ++ ++ if (TARGET_MB_64) ++ { ++ set_optab_libfunc (smod_optab, DImode, "__moddi3"); ++ set_optab_libfunc (sdiv_optab, DImode, "__divdi3"); ++ set_optab_libfunc (smul_optab, DImode, "__muldi3"); ++ set_optab_libfunc (umod_optab, DImode, "__umoddi3"); ++ set_optab_libfunc (udiv_optab, DImode, "__udivdi3"); ++ } ++} + /* Insert instruction prefetch instruction at the fall + through path of the function call. */ + +@@ -4127,6 +4211,17 @@ microblaze_starting_frame_offset (void) + #undef TARGET_LRA_P + #define TARGET_LRA_P hook_bool_void_false + ++#ifdef TARGET_MB_64 ++#undef TARGET_ASM_ALIGNED_DI_OP ++#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" ++ ++#undef TARGET_ASM_ALIGNED_HI_OP ++#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" ++ ++#undef TARGET_ASM_ALIGNED_SI_OP ++#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" ++#endif ++ + #undef TARGET_FRAME_POINTER_REQUIRED + #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required + +@@ -4136,6 +4231,9 @@ microblaze_starting_frame_offset (void) + #undef TARGET_TRAMPOLINE_INIT + #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init + ++#undef TARGET_INIT_LIBFUNCS ++#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs ++ + #undef TARGET_PROMOTE_FUNCTION_MODE + #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 72fbee5..1e60513 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe; + + /* Generate DWARF exception handling info. */ + #define DWARF2_UNWIND_INFO 1 +- + /* Don't generate .loc operations. */ + #define DWARF2_ASM_LINE_DEBUG_INFO 0 + +@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe; + ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr) + + /* Use DWARF 2 debugging information by default. */ +-#define DWARF2_DEBUGGING_INFO ++#define DWARF2_DEBUGGING_INFO 1 + #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG ++#define DWARF2_ADDR_SIZE 4 + + /* Target machine storage layout */ + + #define BITS_BIG_ENDIAN 0 + #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) + #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) +-#define BITS_PER_WORD 32 +-#define UNITS_PER_WORD 4 ++//#define BITS_PER_WORD 64 ++//Revisit ++#define MAX_BITS_PER_WORD 64 ++#define UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) ++//#define MIN_UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) ++//#define UNITS_PER_WORD 4 + #define MIN_UNITS_PER_WORD 4 + #define INT_TYPE_SIZE 32 + #define SHORT_TYPE_SIZE 16 +-#define LONG_TYPE_SIZE 64 ++#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32) + #define LONG_LONG_TYPE_SIZE 64 + #define FLOAT_TYPE_SIZE 32 + #define DOUBLE_TYPE_SIZE 64 + #define LONG_DOUBLE_TYPE_SIZE 64 +-#define POINTER_SIZE 32 +-#define PARM_BOUNDARY 32 +-#define FUNCTION_BOUNDARY 32 +-#define EMPTY_FIELD_BOUNDARY 32 ++#define POINTER_SIZE (TARGET_MB_64 ? 64 : 32) ++//#define WIDEST_HARDWARE_FP_SIZE 64 ++//#define POINTERS_EXTEND_UNSIGNED 1 ++#define PARM_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++#define FUNCTION_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++#define EMPTY_FIELD_BOUNDARY (TARGET_MB_64 ? 64 : 32) + #define STRUCTURE_SIZE_BOUNDARY 8 +-#define BIGGEST_ALIGNMENT 32 ++#define BIGGEST_ALIGNMENT (TARGET_MB_64 ? 64 : 32) + #define STRICT_ALIGNMENT 1 + #define PCC_BITFIELD_TYPE_MATTERS 1 + ++//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode) + #undef SIZE_TYPE +-#define SIZE_TYPE "unsigned int" ++#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") + + #undef PTRDIFF_TYPE +-#define PTRDIFF_TYPE "int" ++#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int") ++ ++/*#undef INTPTR_TYPE ++#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/ ++#undef UINTPTR_TYPE ++#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") + + #define DATA_ALIGNMENT(TYPE, ALIGN) \ + ((((ALIGN) < BITS_PER_WORD) \ +@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe; + #define WORD_REGISTER_OPERATIONS 1 + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND +- ++/* + #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < 4) \ +- (MODE) = SImode; +- ++ && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ ++ (MODE) = TARGET_MB_64 ? DImode : SImode; ++*/ + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info; + #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD) + + #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 ++#define DWARF_CIE_DATA_ALIGNMENT -1 + + #define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL) + + #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 + +-#define STACK_BOUNDARY 32 ++#define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) + ++#define PREFERRED_STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++ + #define NUM_OF_ARGS 6 + + #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM) +@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info; + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + + #define LIBCALL_VALUE(MODE) \ ++ gen_rtx_REG (MODE,GP_RETURN) ++ ++/*#define LIBCALL_VALUE(MODE) \ + gen_rtx_REG ( \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), GP_RETURN) +- ++*/ + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +@@ -500,7 +518,7 @@ typedef struct microblaze_args + /* 4 insns + 2 words of data. */ + #define TRAMPOLINE_SIZE (6 * 4) + +-#define TRAMPOLINE_ALIGNMENT 32 ++#define TRAMPOLINE_ALIGNMENT 64 + + #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +@@ -533,13 +551,13 @@ typedef struct microblaze_args + addresses which require two reload registers. */ + #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X) + +-#define CASE_VECTOR_MODE (SImode) ++#define CASE_VECTOR_MODE (TARGET_MB_64? DImode:SImode) + + #ifndef DEFAULT_SIGNED_CHAR + #define DEFAULT_SIGNED_CHAR 1 + #endif + +-#define MOVE_MAX 4 ++#define MOVE_MAX (TARGET_MB_64 ? 8 : 4) + #define MAX_MOVE_MAX 8 + + #define SLOW_BYTE_ACCESS 1 +@@ -549,7 +567,7 @@ typedef struct microblaze_args + + #define SHIFT_COUNT_TRUNCATED 1 + +-#define Pmode SImode ++#define Pmode (TARGET_MB_64? DImode:SImode) + + #define FUNCTION_MODE SImode + +@@ -711,6 +729,7 @@ do { \ + + #undef TARGET_ASM_OUTPUT_IDENT + #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident ++//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive + + /* Default to -G 8 */ + #ifndef MICROBLAZE_DEFAULT_GVALUE +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 0cd0441..0f41ac6 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -26,6 +26,7 @@ + ;; Constants + ;;---------------------------------------------------- + (define_constants [ ++ (R_Z 0) ;; For reg r0 + (R_SP 1) ;; Stack pointer reg + (R_SR 15) ;; Sub-routine return addr reg + (R_IR 14) ;; Interrupt return addr reg +@@ -539,6 +540,7 @@ + + ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ] + ;; Leave carry as is ++ + (define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ") +@@ -560,23 +562,38 @@ + + ;; Adding 2 DI operands in register or reg/imm + +-(define_insn "adddi3_long" ++(define_expand "adddi3" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (plus:DI (match_operand:DI 1 "register_operand" "") ++ (match_operand:DI 2 "arith_plus_operand" "")))] ++"" ++{ ++ if (TARGET_MB_64) ++ { ++ if (GET_CODE (operands[2]) == CONST_INT && ++ INTVAL(operands[2]) < (long)-549755813888 && ++ INTVAL(operands[2]) > (long)549755813887) ++ FAIL; ++ } ++}) ++ ++(define_insn "*adddi3_long" + [(set (match_operand:DI 0 "register_operand" "=d,d") +- (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") ++ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") + (match_operand:DI 2 "arith_plus_operand" "d,K")))] + "TARGET_MB_64" + "@ +- addlk\t%0,%z1,%2 +- addlik\t%0,%z1,%2" +- [(set_attr "type" "arith,arith") +- (set_attr "mode" "DI,DI") ++ addlk\t%0,%1,%2 ++ addlik\t%0,%1,%2 #N10" ++ [(set_attr "type" "darith,no_delay_arith") ++ (set_attr "mode" "DI") + (set_attr "length" "4,4")]) + +-(define_insn "adddi3" ++(define_insn "*adddi3_all" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") + (match_operand:DI 2 "arith_operand" "d,i")))] +- "" ++ "!TARGET_MB_64" + "@ + add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 + addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" +@@ -603,7 +620,7 @@ + (define_insn "iprefetch" + [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH) + (clobber (mem:BLK (scratch)))] +- "TARGET_PREFETCH" ++ "TARGET_PREFETCH && !TARGET_MB_64" + { + operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + return "mfs\t%2,rpc\n\twic\t%2,r0"; +@@ -616,23 +633,33 @@ + ;; Double Precision Subtraction + ;;---------------------------------------------------------------- + +-(define_insn "subdi3_long" +- [(set (match_operand:DI 0 "register_operand" "=d,d") +- (minus:DI (match_operand:DI 1 "register_operand" "d,d") +- (match_operand:DI 2 "register_operand" "d,n")))] ++(define_expand "subdi3" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (minus:DI (match_operand:DI 1 "register_operand" "") ++ (match_operand:DI 2 "arith_operand" "")))] ++"" ++" ++{ ++}") ++ ++(define_insn "subsidi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") ++ (match_operand:DI 2 "arith_operand" "d,K,n")))] + "TARGET_MB_64" + "@ + rsubl\t%0,%2,%1 +- addlik\t%0,%z1,-%2" +- [(set_attr "type" "darith") +- (set_attr "mode" "DI,DI") +- (set_attr "length" "4,4")]) ++ addik\t%0,%z1,-%2 ++ addik\t%0,%z1,-%2" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,4,4")]) + +-(define_insn "subdi3" ++(define_insn "subdi3_small" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "" ++ "!TARGET_MB_64" + "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" + [(set_attr "type" "darith") + (set_attr "mode" "DI") +@@ -661,7 +688,7 @@ + (mult:DI + (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -672,7 +699,7 @@ + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -683,7 +710,7 @@ + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -787,7 +814,7 @@ + (match_operand:SI 4 "arith_operand")]) + (label_ref (match_operand 5)) + (pc)))] +- "TARGET_HARD_FLOAT" ++ "TARGET_HARD_FLOAT && !TARGET_MB_64" + [(set (match_dup 1) (match_dup 3))] + + { +@@ -817,6 +844,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "negsi_long" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (neg:SI (match_operand:DI 1 "register_operand" "d")))] ++ "" ++ "rsubk\t%0,%1,r0" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "4")]) ++ + (define_insn "negdi2_long" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -845,16 +881,24 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-(define_insn "one_cmpldi2_long" ++(define_expand "one_cmpldi2" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (not:DI (match_operand:DI 1 "register_operand" "")))] ++ "" ++ " ++{ ++}") ++ ++(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") +- (not:DI (match_operand:DI 1 "register_operand" "d")))] ++ (not:DI (match_operand:DI 1 "arith_operand" "d")))] + "TARGET_MB_64" + "xorli\t%0,%1,-1" +- [(set_attr "type" "arith") ++ [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + +-(define_insn "*one_cmpldi2" ++(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "register_operand" "d")))] + "" +@@ -869,7 +913,8 @@ + (not:DI (match_operand:DI 1 "register_operand" "")))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) +- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" ++ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) ++ && !TARGET_MB_64" + + [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) + (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] +@@ -881,18 +926,17 @@ + ;;---------------------------------------------------------------- + + (define_insn "anddi3" +- [(set (match_operand:DI 0 "register_operand" "=d,d") +- (and:DI (match_operand:DI 1 "arith_operand" "d,d") +- (match_operand:DI 2 "arith_operand" "d,K")))] ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") ++ (match_operand:DI 2 "arith_operand" "d,K,I")))] + "TARGET_MB_64" + "@ + andl\t%0,%1,%2 +- andli\t%0,%1,%2 #andl1" +- ;; andli\t%0,%1,%2 #andl3 +- ;; andli\t%0,%1,%2 #andl2 +- [(set_attr "type" "arith,arith") +- (set_attr "mode" "DI,DI") +- (set_attr "length" "4,4")]) ++ andli\t%0,%1,%2 #andl2 ++ andli\t%0,%1,%2 #andl3" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI,DI,DI") ++ (set_attr "length" "4,4,4")]) + + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") +@@ -917,7 +961,7 @@ + "@ + orl\t%0,%1,%2 + orli\t%0,%1,%2 #andl1" +- [(set_attr "type" "arith,arith") ++ [(set_attr "type" "arith,no_delay_arith") + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")]) + +@@ -943,7 +987,7 @@ + "@ + xorl\t%0,%1,%2 + xorli\t%0,%1,%2 #andl1" +- [(set_attr "type" "arith,arith") ++ [(set_attr "type" "arith,no_delay_arith") + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")]) + +@@ -1016,26 +1060,6 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-;;(define_expand "extendqidi2" +-;; [(set (match_operand:DI 0 "register_operand" "=d") +-;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] +-;; "TARGET_MB_64" +-;; { +-;; if (GET_CODE (operands[1]) != REG) +-;; FAIL; +-;; } +-;;) +- +- +-;;(define_insn "extendqidi2" +-;; [(set (match_operand:DI 0 "register_operand" "=d") +-;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] +-;; "TARGET_MB_64" +-;; "sextl8\t%0,%1" +-;; [(set_attr "type" "arith") +-;; (set_attr "mode" "DI") +-;; (set_attr "length" "4")]) +- + (define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] +@@ -1058,6 +1082,27 @@ + ;; Those for integer source operand are ordered + ;; widest source type first. + ++(define_insn "extendsidi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] ++ "TARGET_MB_64" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "sextl32\t%0,%1"; ++ case 1: ++ case 2: ++ { ++ output_asm_insn ("ll%i1\t%0,%1", operands); ++ return "sextl32\t%0,%0"; ++ } ++ } ++ } ++ [(set_attr "type" "multi,multi,multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,8,8")]) ++ + (define_insn "extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] +@@ -1088,68 +1133,117 @@ + ;; Unlike most other insns, the move insns can't be split with + ;; different predicates, because register spilling and other parts of + ;; the compiler, have memoized the insn number already. ++;; //} + + (define_expand "movdi" + [(set (match_operand:DI 0 "nonimmediate_operand" "") + (match_operand:DI 1 "general_operand" ""))] + "" + { +- /* If operands[1] is a constant address illegal for pic, then we need to +- handle it just like microblaze_legitimize_address does. */ +- if (flag_pic && pic_address_needs_scratch (operands[1])) ++ if (TARGET_MB_64) ++ { ++ if (microblaze_expand_move (DImode, operands)) DONE; ++ } ++ else + { ++ /* If operands[1] is a constant address illegal for pic, then we need to ++ handle it just like microblaze_legitimize_address does. */ ++ if (flag_pic && pic_address_needs_scratch (operands[1])) ++ { + rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0)); + rtx temp2 = XEXP (XEXP (operands[1], 0), 1); + emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2)); + DONE; +- } +- +- +- if ((reload_in_progress | reload_completed) == 0 +- && !register_operand (operands[0], DImode) +- && !register_operand (operands[1], DImode) +- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) +- && operands[1] != CONST0_RTX (DImode)))) +- { ++ } + +- rtx temp = force_reg (DImode, operands[1]); +- emit_move_insn (operands[0], temp); +- DONE; ++ if ((reload_in_progress | reload_completed) == 0 ++ && !register_operand (operands[0], DImode) ++ && !register_operand (operands[1], DImode) ++ && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) ++ && operands[1] != CONST0_RTX (DImode)))) ++ { ++ rtx temp = force_reg (DImode, operands[1]); ++ emit_move_insn (operands[0], temp); ++ DONE; ++ } + } + } + ) + ++;; Added for status registers ++(define_insn "movdi_status" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,z") ++ (match_operand:DI 1 "register_operand" "z,d,d"))] ++ "microblaze_is_interrupt_variant () && TARGET_MB_64" ++ "@ ++ mfs\t%0,%1 #mfs ++ addlk\t%0,%1,r0 #add movdi ++ mts\t%0,%1 #mts" ++ [(set_attr "type" "move") ++ (set_attr "mode" "DI") ++ (set_attr "length" "12")]) + +-(define_insn "*movdi_internal_64" +- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") +- (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] +- "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" ++;; This move will be not be moved to delay slot. ++(define_insn "*movdi_internal3" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") ++ (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] ++ "TARGET_MB_64 && (register_operand (operands[0], DImode) && ++ (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" ++ "@ ++ addlk\t%0,r0,r0\t ++ addlik\t%0,r0,%1\t #N1 %X1 ++ addlik\t%0,r0,%1\t #N2 %X1" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++;; This move may be used for PLT label operand ++(define_insn "*movdi_internal5_pltop" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (match_operand:DI 1 "call_insn_operand" ""))] ++ "TARGET_MB_64 && (register_operand (operands[0], Pmode) && ++ PLT_ADDR_P (operands[1]))" ++ { ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "load") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++(define_insn "*movdi_internal2" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") ++ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] ++ "TARGET_MB_64" + { + switch (which_alternative) + { + case 0: +- return "addlk\t%0,%1"; +- case 1: +- return "addlik\t%0,r0,%1"; +- case 2: +- return "addlk\t%0,r0,r0"; +- case 3: +- case 4: +- return "lli\t%0,%1"; +- case 5: +- case 6: +- return "sli\t%1,%0"; +- } +- return "unreachable"; +- } +- [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ case 2: ++ if (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) ++ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ else ++ return "addlik\t%0,r0,%1"; ++ case 3: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 5: ++ case 6: ++ return "sl%i0\t%z1,%0"; ++ } ++ } ++ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") + (set_attr "mode" "DI") +- (set_attr "length" "8,8,8,8,12,8,12")]) ++ (set_attr "length" "4,4,12,4,8,4,8")]) ++ + + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") + (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] +- "" ++ "!TARGET_MB_64" + { + switch (which_alternative) + { +@@ -1181,7 +1275,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))" ++ && (REGNO(operands[0]) == (REGNO(operands[1]) + 1)) ++ && !(TARGET_MB_64)" + + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] +@@ -1193,12 +1288,22 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) ++ && !(TARGET_MB_64)" + + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") + ++(define_insn "movdi_long_int" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") ++ (match_operand:DI 1 "general_operand" "i"))] ++ "" ++ "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "12")]) ++ + ;; Unlike most other insns, the move insns can't be split with + ;; different predicates, because register spilling and other parts of + ;; the compiler, have memoized the insn number already. +@@ -1270,6 +1375,8 @@ + (set_attr "length" "4,4,8,4,8,4,8")]) + + ++ ++ + ;; 16-bit Integer moves + + ;; Unlike most other insns, the move insns can't be split with +@@ -1302,8 +1409,8 @@ + "@ + addik\t%0,r0,%1\t# %X1 + addk\t%0,%1,r0 +- lhui\t%0,%1 +- lhui\t%0,%1 ++ lhu%i1\t%0,%1 ++ lhu%i1\t%0,%1 + sh%i0\t%z1,%0 + sh%i0\t%z1,%0" + [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store") +@@ -1346,7 +1453,7 @@ + lbu%i1\t%0,%1 + lbu%i1\t%0,%1 + sb%i0\t%z1,%0 +- sbi\t%z1,%0" ++ sb%i0\t%z1,%0" + [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store") + (set_attr "mode" "QI") + (set_attr "length" "4,4,8,4,8,4,8")]) +@@ -1419,7 +1526,7 @@ + addik\t%0,r0,%F1 + lw%i1\t%0,%1 + sw%i0\t%z1,%0 +- swi\t%z1,%0" ++ sw%i0\t%z1,%0" + [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store") + (set_attr "mode" "SF") + (set_attr "length" "4,4,4,4,4,4,4")]) +@@ -1458,6 +1565,33 @@ + ;; movdf_internal + ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT + ;; ++(define_insn "*movdf_internal_64" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") ++ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] ++ "TARGET_MB_64" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ return "addlk\t%0,r0,r0"; ++ case 2: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 3: ++ { ++ return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; ++ } ++ case 5: ++ return "sl%i0\t%1,%0"; ++ } ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4,4,4,16,4,4")]) ++ + (define_insn "*movdf_internal" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o") + (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))] +@@ -1492,7 +1626,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) == (REGNO (operands[1]) + 1)) ++ && !TARGET_MB_64" + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] + "") +@@ -1503,7 +1638,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) ++ && !TARGET_MB_64" + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") +@@ -2003,6 +2139,31 @@ else + " + ) + ++ ++(define_insn "seq_internal_pat_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (eq:DI ++ (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "pcmpleq\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "sne_internal_pat_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (ne:DI ++ (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "pcmplne\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ + (define_insn "seq_internal_pat" + [(set (match_operand:SI 0 "register_operand" "=d") + (eq:SI +@@ -2063,8 +2224,8 @@ else + (define_expand "cbranchsi4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:SI 1 "register_operand") +- (match_operand:SI 2 "arith_operand" "I,i")]) ++ [(match_operand 1 "register_operand") ++ (match_operand 2 "arith_operand" "I,i")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" +@@ -2076,13 +2237,13 @@ else + (define_expand "cbranchsi4_reg" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:SI 1 "register_operand") +- (match_operand:SI 2 "register_operand")]) ++ [(match_operand 1 "register_operand") ++ (match_operand 2 "register_operand")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" + { +- microblaze_expand_conditional_branch_reg (SImode, operands); ++ microblaze_expand_conditional_branch_reg (Pmode, operands); + DONE; + }) + +@@ -2107,6 +2268,26 @@ else + (label_ref (match_operand 1)) + (pc)))]) + ++(define_insn "branch_zero64" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand 2 "pc_or_label_operand" "") ++ (match_operand 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "bea%C0i%?\t%z1,%2"; ++ else ++ return "bea%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ + (define_insn "branch_zero" + [(set (pc) + (if_then_else (match_operator:SI 0 "ordered_comparison_operator" +@@ -2127,6 +2308,47 @@ else + (set_attr "length" "4")] + ) + ++(define_insn "branch_compare64" ++ [(set (pc) ++ (if_then_else (match_operator 0 "cmp_op" ++ [(match_operand 1 "register_operand" "d") ++ (match_operand 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:SI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmp\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmpu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmp\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmpu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx); ++ return "bea%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + (define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" +@@ -2310,7 +2532,7 @@ else + ;; Indirect jumps. Jump to register values. Assuming absolute jumps + + (define_insn "indirect_jump_internal1" +- [(set (pc) (match_operand:SI 0 "register_operand" "d"))] ++ [(set (pc) (match_operand 0 "register_operand" "d"))] + "" + "bra%?\t%0" + [(set_attr "type" "jump") +@@ -2323,7 +2545,7 @@ else + (use (label_ref (match_operand 1 "" "")))] + "" + { +- gcc_assert (GET_MODE (operands[0]) == Pmode); ++ //gcc_assert (GET_MODE (operands[0]) == Pmode); + + if (!flag_pic) + emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); +@@ -2335,7 +2557,7 @@ else + + (define_insn "tablejump_internal1" + [(set (pc) +- (match_operand:SI 0 "register_operand" "d")) ++ (match_operand 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bra%?\t%0 " +@@ -2345,9 +2567,9 @@ else + + (define_expand "tablejump_internal3" + [(parallel [(set (pc) +- (plus:SI (match_operand:SI 0 "register_operand" "d") +- (label_ref:SI (match_operand:SI 1 "" "")))) +- (use (label_ref:SI (match_dup 1)))])] ++ (plus (match_operand 0 "register_operand" "d") ++ (label_ref (match_operand:SI 1 "" "")))) ++ (use (label_ref (match_dup 1)))])] + "" + "" + ) +@@ -2408,7 +2630,7 @@ else + (minus (reg 1) (match_operand 1 "register_operand" ""))) + (set (reg 1) + (minus (reg 1) (match_dup 1)))] +- "" ++ "!TARGET_MB_64" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); + rtx reg = gen_reg_rtx (Pmode); +@@ -2433,7 +2655,7 @@ else + (define_expand "save_stack_block" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "")] +- "" ++ "!TARGET_MB_64" + { + emit_move_insn (operands[0], operands[1]); + DONE; +@@ -2443,7 +2665,7 @@ else + (define_expand "restore_stack_block" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "")] +- "" ++ "!TARGET_MB_64" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); + rtx rtmp = gen_rtx_REG (SImode, R_TMP); +@@ -2490,7 +2712,7 @@ else + + (define_insn "<optab>_internal" + [(any_return) +- (use (match_operand:SI 0 "register_operand" ""))] ++ (use (match_operand 0 "register_operand" ""))] + "" + { + if (microblaze_is_break_handler ()) +@@ -2523,7 +2745,7 @@ else + (define_expand "call" + [(parallel [(call (match_operand 0 "memory_operand" "m") + (match_operand 1 "" "i")) +- (clobber (reg:SI R_SR)) ++ (clobber (reg R_SR)) + (use (match_operand 2 "" "")) + (use (match_operand 3 "" ""))])] + "" +@@ -2543,12 +2765,12 @@ else + + if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC) + emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_internal0 (operands[0], operands[1], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; +@@ -2558,7 +2780,7 @@ else + (define_expand "call_internal0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) +- (clobber (match_operand:SI 2 "" ""))])] ++ (clobber (match_operand 2 "" ""))])] + "" + { + } +@@ -2567,18 +2789,34 @@ else + (define_expand "call_internal_plt0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) +- (clobber (match_operand:SI 2 "" "")) +- (use (match_operand:SI 3 "" ""))])] ++ (clobber (match_operand 2 "" "")) ++ (use (match_operand 3 "" ""))])] + "" + { + } + ) + ++(define_insn "call_internal_plt_64" ++ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR)) ++ (use (reg R_GOT))] ++ "flag_pic && TARGET_MB_64" ++ { ++ register rtx target2 = gen_rtx_REG (Pmode, ++ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "brealid\tr15,%0\;%#"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_internal_plt" +- [(call (mem (match_operand:SI 0 "call_insn_plt_operand" "")) +- (match_operand:SI 1 "" "i")) +- (clobber (reg:SI R_SR)) +- (use (reg:SI R_GOT))] ++ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR)) ++ (use (reg R_GOT))] + "flag_pic" + { + register rtx target2 = gen_rtx_REG (Pmode, +@@ -2590,10 +2828,41 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "call_internal1_64" ++ [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR))] ++ "TARGET_MB_64" ++ { ++ register rtx target = operands[0]; ++ register rtx target2 = gen_rtx_REG (Pmode, ++ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ if (GET_CODE (target) == SYMBOL_REF) { ++ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) { ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "breaki\tr16,%0\;%#"; ++ } ++ else { ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "brealid\tr15,%0\;%#"; ++ } ++ } else if (GET_CODE (target) == CONST_INT) ++ return "la\t%@,r0,%0\;brald\tr15,%@\;%#"; ++ else if (GET_CODE (target) == REG) ++ return "brald\tr15,%0\;%#"; ++ else { ++ fprintf (stderr,"Unsupported call insn\n"); ++ return NULL; ++ } ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_internal1" + [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) +- (match_operand:SI 1 "" "i")) +- (clobber (reg:SI R_SR))] ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR))] + "" + { + register rtx target = operands[0]; +@@ -2627,7 +2896,7 @@ else + [(parallel [(set (match_operand 0 "register_operand" "=d") + (call (match_operand 1 "memory_operand" "m") + (match_operand 2 "" "i"))) +- (clobber (reg:SI R_SR)) ++ (clobber (reg R_SR)) + (use (match_operand 3 "" ""))])] ;; next_arg_reg + "" + { +@@ -2647,13 +2916,13 @@ else + if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC) + emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], + operands[2], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_value_internal (operands[0], operands[1], + operands[2], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; +@@ -2665,7 +2934,7 @@ else + [(parallel [(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) +- (clobber (match_operand:SI 3 "" "")) ++ (clobber (match_operand 3 "" "")) + ])] + "" + {} +@@ -2675,18 +2944,35 @@ else + [(parallel[(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) +- (clobber (match_operand:SI 3 "" "")) +- (use (match_operand:SI 4 "" ""))])] ++ (clobber (match_operand 3 "" "")) ++ (use (match_operand 4 "" ""))])] + "flag_pic" + {} + ) + ++(define_insn "call_value_intern_plt_64" ++ [(set (match_operand:VOID 0 "register_operand" "=d") ++ (call (mem (match_operand 1 "call_insn_plt_operand" "")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d")) ++ (use (match_operand 4 "register_operand"))] ++ "flag_pic && TARGET_MB_64" ++ { ++ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ ++ gen_rtx_CLOBBER (VOIDmode,target2); ++ return "brealid\tr15,%1\;%#"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_value_intern_plt" + [(set (match_operand:VOID 0 "register_operand" "=d") +- (call (mem (match_operand:SI 1 "call_insn_plt_operand" "")) +- (match_operand:SI 2 "" "i"))) +- (clobber (match_operand:SI 3 "register_operand" "=d")) +- (use (match_operand:SI 4 "register_operand"))] ++ (call (mem (match_operand 1 "call_insn_plt_operand" "")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d")) ++ (use (match_operand 4 "register_operand"))] + "flag_pic" + { + register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); +@@ -2698,11 +2984,46 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "call_value_intern_64" ++ [(set (match_operand:VOID 0 "register_operand" "=d") ++ (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d"))] ++ "TARGET_MB_64" ++ { ++ register rtx target = operands[1]; ++ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ ++ if (GET_CODE (target) == SYMBOL_REF) ++ { ++ gen_rtx_CLOBBER (VOIDmode,target2); ++ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) ++ return "breaki\tr16,%1\;%#"; ++ else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION) ++ { ++ return "brealid\tr15,%1\;%#"; ++ } ++ else ++ { ++ return "bralid\tr15,%1\;%#"; ++ } ++ } ++ else if (GET_CODE (target) == CONST_INT) ++ return "la\t%@,r0,%1\;brald\tr15,%@\;%#"; ++ else if (GET_CODE (target) == REG) ++ return "brald\tr15,%1\;%#"; ++ else ++ return "Unsupported call insn\n"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_value_intern" + [(set (match_operand:VOID 0 "register_operand" "=d") + (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) +- (match_operand:SI 2 "" "i"))) +- (clobber (match_operand:SI 3 "register_operand" "=d"))] ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d"))] + "" + { + register rtx target = operands[1]; +@@ -2864,7 +3185,6 @@ else + + ;;if (!register_operand (operands[0], VOIDmode)) + ;; FAIL; +- + emit_insn (gen_insv_32 (operands[0], operands[1], + operands[2], operands[3])); + DONE; +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 7671f63..9fc80b1 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -2,10 +2,11 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en + MULTILIB_DIRNAMES = bs m mh le m64 + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian +-#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 +-#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S +index 2e15be4..3386520 100644 +--- a/libgcc/config/microblaze/crti.S ++++ b/libgcc/config/microblaze/crti.S +@@ -40,7 +40,7 @@ + + .align 2 + __init: +- addik r1, r1, -8 ++ addik r1, r1, -16 + sw r15, r0, r1 + la r11, r0, _stack + mts rshr, r11 +@@ -51,5 +51,5 @@ __init: + .global __fini + .align 2 + __fini: +- addik r1, r1, -8 ++ addik r1, r1, -16 + sw r15, r0, r1 +diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S +index cd5fd9e..04e73d7 100644 +--- a/libgcc/config/microblaze/crtn.S ++++ b/libgcc/config/microblaze/crtn.S +@@ -33,9 +33,9 @@ + .section .init, "ax" + lw r15, r0, r1 + rtsd r15, 8 +- addik r1, r1, 8 ++ addik r1, r1, 16 + + .section .fini, "ax" + lw r15, r0, r1 + rtsd r15, 8 +- addik r1, r1, 8 ++ addik r1, r1, 16 +diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S +new file mode 100644 +index 0000000..d37bf51 +--- /dev/null ++++ b/libgcc/config/microblaze/divdi3.S +@@ -0,0 +1,98 @@ ++###################################- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# divdi3.S ++# ++# Divide operation for 32 bit integers. ++# Input : Dividend in Reg r5 ++# Divisor in Reg r6 ++# Output: Result in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __divdi3 ++ .ent __divdi3 ++ .type __divdi3,@function ++__divdi3: ++ .frame r1,0,r15 ++ ++ ADDLIK r1,r1,-32 ++ SLI r28,r1,0 ++ SLI r29,r1,8 ++ SLI r30,r1,16 ++ SLI r31,r1,24 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ XORL r28,r5,r6 # Get the sign of the result ++ BEALGEI r5,$LaR5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$LaR5_Pos: ++ BEALGEI r6,$LaR6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$LaR6_Pos: ++ ADDLIK r30,r0,0 # Clear mod ++ ADDLIK r3,r0,0 # clear div ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++ # First part try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGTI r5,$LaDIV1 ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r30,r30,r30 # Move that bit into the Mod register ++ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) ++ BEALLTI r31,$LaMOD_TOO_SMALL ++ ORL r30,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r3,r3,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEALGEI r28,$LaRETURN_HERE ++ RSUBLI r3,r3,0 # Negate the result ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ ORL r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r28,r1,0 ++ LLI r29,r1,8 ++ LLI r30,r1,16 ++ LLI r31,r1,24 ++ ADDLIK r1,r1,32 ++ RTSD r15,8 ++ nop ++.end __divdi3 ++ .size __divdi3, . - __divdi3 ++#endif +diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c +new file mode 100644 +index 0000000..8096259 +--- /dev/null ++++ b/libgcc/config/microblaze/divdi3_table.c +@@ -0,0 +1,62 @@ ++/* Table for software lookup divide for Xilinx MicroBlaze. ++ ++ Copyright (C) 2009-2017 Free Software Foundation, Inc. ++ ++ Contributed by Michael Eager <eager@eagercon.com>. ++ ++ This file is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published by the ++ Free Software Foundation; either version 3, or (at your option) any ++ later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ <http://www.gnu.org/licenses/>. */ ++ ++ ++unsigned char _divdi3_table[] = ++{ ++ 0, 0/1, 0/2, 0/3, 0/4, 0/5, 0/6, 0/7, ++ 0/8, 0/9, 0/10, 0/11, 0/12, 0/13, 0/14, 0/15, ++ 0, 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ++ 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14, 1/15, ++ 0, 2/1, 2/2, 2/3, 2/4, 2/5, 2/6, 2/7, ++ 2/8, 2/9, 2/10, 2/11, 2/12, 2/13, 2/14, 2/15, ++ 0, 3/1, 3/2, 3/3, 3/4, 3/5, 3/6, 3/7, ++ 3/8, 3/9, 3/10, 3/11, 3/12, 3/13, 3/14, 3/15, ++ 0, 4/1, 4/2, 4/3, 4/4, 4/5, 4/6, 4/7, ++ 4/8, 4/9, 4/10, 4/11, 4/12, 4/13, 4/14, 4/15, ++ 0, 5/1, 5/2, 5/3, 5/4, 5/5, 5/6, 5/7, ++ 5/8, 5/9, 5/10, 5/11, 5/12, 5/13, 5/14, 5/15, ++ 0, 6/1, 6/2, 6/3, 6/4, 6/5, 6/6, 6/7, ++ 6/8, 6/9, 6/10, 6/11, 6/12, 6/13, 6/14, 6/15, ++ 0, 7/1, 7/2, 7/3, 7/4, 7/5, 7/6, 7/7, ++ 7/8, 7/9, 7/10, 7/11, 7/12, 7/13, 7/14, 7/15, ++ 0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, 8/7, ++ 8/8, 8/9, 8/10, 8/11, 8/12, 8/13, 8/14, 8/15, ++ 0, 9/1, 9/2, 9/3, 9/4, 9/5, 9/6, 9/7, ++ 9/8, 9/9, 9/10, 9/11, 9/12, 9/13, 9/14, 9/15, ++ 0, 10/1, 10/2, 10/3, 10/4, 10/5, 10/6, 10/7, ++ 10/8, 10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15, ++ 0, 11/1, 11/2, 11/3, 11/4, 11/5, 11/6, 11/7, ++ 11/8, 11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15, ++ 0, 12/1, 12/2, 12/3, 12/4, 12/5, 12/6, 12/7, ++ 12/8, 12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15, ++ 0, 13/1, 13/2, 13/3, 13/4, 13/5, 13/6, 13/7, ++ 13/8, 13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15, ++ 0, 14/1, 14/2, 14/3, 14/4, 14/5, 14/6, 14/7, ++ 14/8, 14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15, ++ 0, 15/1, 15/2, 15/3, 15/4, 15/5, 15/6, 15/7, ++ 15/8, 15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15, ++}; ++ +diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S +new file mode 100644 +index 0000000..5d3f7c0 +--- /dev/null ++++ b/libgcc/config/microblaze/moddi3.S +@@ -0,0 +1,97 @@ ++################################### ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# moddi3.S ++# ++# modulo operation for 32 bit integers. ++# Input : op1 in Reg r5 ++# op2 in Reg r6 ++# Output: op1 mod op2 in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __moddi3 ++ .ent __moddi3 ++ .type __moddi3,@function ++__moddi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-32 ++ sli r28,r1,0 ++ sli r29,r1,8 ++ sli r30,r1,16 ++ sli r31,r1,32 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDL r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] ++ BEALGEI r5,$LaR5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$LaR5_Pos: ++ BEALGEI r6,$LaR6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$LaR6_Pos: ++ ADDLIK r3,r0,0 # Clear mod ++ ADDLIK r30,r0,0 # clear div ++ ADDLIK r29,r0,64 # Initialize the loop count ++ BEALLTI r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++ # the first bit search. ++ # First part try to find the first '1' in the r5 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGEI r5,$LaDIV1 # ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r3,r3,r3 # Move that bit into the Mod register ++ rSUBL r31,r6,r3 # Try to subtract (r30 a r6) ++ BEALLTi r31,$LaMOD_TOO_SMALL ++ ORL r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEALGEI r28,$LaRETURN_HERE ++ rsubli r3,r3,0 # Negate the result ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ orl r3,r0,r0 # set result to 0 [Both mod as well as div are 0] ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r28,r1,0 ++ lli r29,r1,8 ++ lli r30,r1,16 ++ lli r31,r1,24 ++ addlik r1,r1,32 ++ rtsd r15,8 ++ nop ++ .end __moddi3 ++ .size __moddi3, . - __moddi3 ++#endif +diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S +new file mode 100644 +index 0000000..5677841 +--- /dev/null ++++ b/libgcc/config/microblaze/muldi3.S +@@ -0,0 +1,73 @@ ++/*###################################-*-asm*- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# muldi3.S ++# ++# Multiply operation for 32 bit integers. ++# Input : Operand1 in Reg r5 ++# Operand2 in Reg r6 ++# Output: Result [op1 * op2] in Reg r3 ++# ++#######################################*/ ++ ++#ifdef __arch64__ ++ .globl __muldi3 ++ .ent __muldi3 ++ .type __muldi3,@function ++__muldi3: ++ .frame r1,0,r15 ++ addl r3,r0,r0 ++ BEALEQI r5,$L_Result_Is_Zero # Multiply by Zero ++ BEALEQI r6,$L_Result_Is_Zero # Multiply by Zero ++ XORL r4,r5,r6 # Get the sign of the result ++ BEALGEI r5,$L_R5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$L_R5_Pos: ++ BEALGEI r6,$L_R6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$L_R6_Pos: ++ breai $L1 ++$L2: ++ addl r5,r5,r5 ++$L1: ++ srll r6,r6 ++ addlc r7,r0,r0 ++ bealeqi r7,$L2 ++ addl r3,r3,r5 ++ bealnei r6,$L2 ++ beallti r4,$L_NegateResult ++ rtsd r15,8 ++ nop ++$L_NegateResult: ++ rsubl r3,r3,r0 ++ rtsd r15,8 ++ nop ++$L_Result_Is_Zero: ++ addli r3,r0,0 ++ rtsd r15,8 ++ nop ++ .end __muldi3 ++ .size __muldi3, . - __muldi3 ++#endif +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 8d954a4..35021b2 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,11 +1,16 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ ++ _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ ++ $(srcdir)/config/microblaze/divdi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ +- $(srcdir)/config/microblaze/muldi3_hard.S \ ++ $(srcdir)/config/microblaze/moddi3.S \ + $(srcdir)/config/microblaze/mulsi3.S \ ++ $(srcdir)/config/microblaze/muldi3.S \ + $(srcdir)/config/microblaze/stack_overflow_exit.S \ + $(srcdir)/config/microblaze/udivsi3.S \ ++ $(srcdir)/config/microblaze/udivdi3.S \ + $(srcdir)/config/microblaze/umodsi3.S \ +- $(srcdir)/config/microblaze/divsi3_table.c ++ $(srcdir)/config/microblaze/umoddi3.S \ ++ $(srcdir)/config/microblaze/divsi3_table.c \ +diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S +new file mode 100644 +index 0000000..c210fbc +--- /dev/null ++++ b/libgcc/config/microblaze/udivdi3.S +@@ -0,0 +1,107 @@ ++###################################- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# udivdi3.S ++# ++# Unsigned divide operation. ++# Input : Divisor in Reg r5 ++# Dividend in Reg r6 ++# Output: Result in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __udivdi3 ++ .ent __udivdi3 ++ .type __udivdi3,@function ++__udivdi3: ++ .frame r1,0,r15 ++ ++ ADDlIK r1,r1,-24 ++ SLI r29,r1,0 ++ SLI r30,r1,8 ++ SLI r31,r1,16 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ ADDLIK r30,r0,0 # Clear mod ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++ # Check if r6 and r5 are equal # if yes, return 1 ++ RSUBL r18,r5,r6 ++ ADDLIK r3,r0,1 ++ BEALEQI r18,$LaRETURN_HERE ++ ++ # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 ++ XORL r18,r5,r6 ++ ADDL r3,r0,r0 # We would anyways clear r3 ++ BEALGEI r18,$LRSUBL ++ BEALLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater ++ BREAI $LCheckr6 ++$LRSUBL: ++ RSUBL r18,r6,r5 # MICROBLAZEcmp ++ BEALLTI r18,$LaRETURN_HERE ++ ++ # If r6 [bit 31] is set, then return result as 1 ++$LCheckr6: ++ BEALGTI r6,$LaDIV0 ++ ADDLIK r3,r0,1 ++ BREAI $LaRETURN_HERE ++ ++ # First part try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGTI r5,$LaDIV1 ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r30,r30,r30 # Move that bit into the Mod register ++ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) ++ BEALLTI r31,$LaMOD_TOO_SMALL ++ ORL r30,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r3,r3,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ ORL r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++ # Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r29,r1,0 ++ LLI r30,r1,8 ++ LLI r31,r1,16 ++ ADDLIK r1,r1,24 ++ RTSD r15,8 ++ NOP ++ .end __udivdi3 ++ .size __udivdi3, . - __udivdi3 ++#endif +diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S +new file mode 100644 +index 0000000..7f5cd23 +--- /dev/null ++++ b/libgcc/config/microblaze/umoddi3.S +@@ -0,0 +1,110 @@ ++################################### ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# umoddi3.S ++# ++# Unsigned modulo operation for 32 bit integers. ++# Input : op1 in Reg r5 ++# op2 in Reg r6 ++# Output: op1 mod op2 in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __umoddi3 ++ .ent __umoddi3 ++ .type __umoddi3,@function ++__umoddi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-24 ++ sli r29,r1,0 ++ sli r30,r1,8 ++ sli r31,r1,16 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ ADDLIK r3,r0,0 # Clear div ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDLIK r30,r0,0 # clear mod ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++# Check if r6 and r5 are equal # if yes, return 0 ++ rsubl r18,r5,r6 ++ bealeqi r18,$LaRETURN_HERE ++ ++# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 ++ xorl r18,r5,r6 ++ addlik r3,r5,0 ++ bealgei r18,$LRSUB ++ beallti r6,$LaRETURN_HERE ++ breai $LCheckr6 ++$LRSUB: ++ rsubl r18,r5,r6 # MICROBLAZEcmp ++ bealgti r18,$LaRETURN_HERE ++ ++# If r6 [bit 31] is set, then return result as r5-r6 ++$LCheckr6: ++ addlik r3,r0,0 ++ bealgti r6,$LaDIV0 ++ addlik r18,r0,0x7fffffff ++ andl r5,r5,r18 ++ andl r6,r6,r18 ++ breaid $LaRETURN_HERE ++ rsubl r3,r6,r5 ++# First part: try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGEI r5,$LaDIV1 # ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r3,r3,r3 # Move that bit into the Mod register ++ rSUBL r31,r6,r3 # Try to subtract (r3 a r6) ++ BEALLTi r31,$LaMOD_TOO_SMALL ++ ORL r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ orl r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r29,r1,0 ++ lli r30,r1,8 ++ lli r31,r1,16 ++ addlik r1,r1,24 ++ rtsd r15,8 ++ nop ++.end __umoddi3 ++ .size __umoddi3, . - __umoddi3 ++#endif +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch new file mode 100644 index 00000000..c33b247b --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch @@ -0,0 +1,268 @@ +From 9e45ca7bd65fe327e01e93d3c539c9d8cf049b79 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 3 Aug 2018 15:41:39 +0530 +Subject: [PATCH 42/54] re-arrangement of the compare branches + +--- + gcc/config/microblaze/microblaze.c | 28 ++----- + gcc/config/microblaze/microblaze.md | 141 +++++++++++++++++------------------- + 2 files changed, 73 insertions(+), 96 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index ba7ade4..fab79d9 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3695,11 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == Pmode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); +- ++ emit_jump_insn (gen_condjump (condition, label1)); + } + + else if (code == EQ || code == NE) +@@ -3710,10 +3706,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + else + emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else + { +@@ -3746,10 +3739,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), + mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else if (code == EQ) + { +@@ -3764,10 +3754,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + cmp_op1)); + } + condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + + } + else if (code == NE) +@@ -3783,10 +3770,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + cmp_op1)); + } + condition = gen_rtx_NE (mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else + { +@@ -3828,7 +3812,7 @@ microblaze_expand_conditional_branch_df (rtx operands[]) + + emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); + condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); +- emit_jump_insn (gen_long_condjump (condition, operands[3])); ++ emit_jump_insn (gen_condjump (condition, operands[3])); + } + + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 0f41ac6..2213d6e 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2268,7 +2268,27 @@ else + (label_ref (match_operand 1)) + (pc)))]) + +-(define_insn "branch_zero64" ++(define_insn "branch_zero_64" ++ [(set (pc) ++ (if_then_else (match_operator:SI 0 "ordered_comparison_operator" ++ [(match_operand:SI 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand:SI 2 "pc_or_label_operand" "") ++ (match_operand:SI 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "bea%C0i%?\t%z1,%2"; ++ else ++ return "bea%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "long_branch_zero" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand 1 "register_operand" "d") +@@ -2279,9 +2299,9 @@ else + "TARGET_MB_64" + { + if (operands[3] == pc_rtx) +- return "bea%C0i%?\t%z1,%2"; ++ return "beal%C0i%?\t%z1,%2"; + else +- return "bea%N0i%?\t%z1,%3"; ++ return "beal%N0i%?\t%z1,%3"; + } + [(set_attr "type" "branch") + (set_attr "mode" "none") +@@ -2310,9 +2330,9 @@ else + + (define_insn "branch_compare64" + [(set (pc) +- (if_then_else (match_operator 0 "cmp_op" +- [(match_operand 1 "register_operand" "d") +- (match_operand 2 "register_operand" "d") ++ (if_then_else (match_operator:SI 0 "cmp_op" ++ [(match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) +@@ -2349,6 +2369,47 @@ else + (set_attr "length" "12")] + ) + ++(define_insn "long_branch_compare" ++ [(set (pc) ++ (if_then_else (match_operator 0 "cmp_op" ++ [(match_operand 1 "register_operand" "d") ++ (match_operand 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:DI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); ++ return "beal%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + (define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" +@@ -2431,74 +2492,6 @@ else + + }) + +-;; Used to implement comparison instructions +-(define_expand "long_condjump" +- [(set (pc) +- (if_then_else (match_operand 0) +- (label_ref (match_operand 1)) +- (pc)))]) +- +-(define_insn "long_branch_zero" +- [(set (pc) +- (if_then_else (match_operator:DI 0 "ordered_comparison_operator" +- [(match_operand:DI 1 "register_operand" "d") +- (const_int 0)]) +- (match_operand:DI 2 "pc_or_label_operand" "") +- (match_operand:DI 3 "pc_or_label_operand" ""))) +- ] +- "TARGET_MB_64" +- { +- if (operands[3] == pc_rtx) +- return "beal%C0i%?\t%z1,%2"; +- else +- return "beal%N0i%?\t%z1,%3"; +- } +- [(set_attr "type" "branch") +- (set_attr "mode" "none") +- (set_attr "length" "4")] +-) +- +-(define_insn "long_branch_compare" +- [(set (pc) +- (if_then_else (match_operator:DI 0 "cmp_op" +- [(match_operand:DI 1 "register_operand" "d") +- (match_operand:DI 2 "register_operand" "d") +- ]) +- (label_ref (match_operand 3)) +- (pc))) +- (clobber(reg:DI R_TMP))] +- "TARGET_MB_64" +- { +- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); +- enum rtx_code code = GET_CODE (operands[0]); +- +- if (code == GT || code == LE) +- { +- output_asm_insn ("cmpl\tr18,%z1,%z2", operands); +- code = swap_condition (code); +- } +- else if (code == GTU || code == LEU) +- { +- output_asm_insn ("cmplu\tr18,%z1,%z2", operands); +- code = swap_condition (code); +- } +- else if (code == GE || code == LT) +- { +- output_asm_insn ("cmpl\tr18,%z2,%z1", operands); +- } +- else if (code == GEU || code == LTU) +- { +- output_asm_insn ("cmplu\tr18,%z2,%z1", operands); +- } +- +- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); +- return "beal%C0i%?\tr18,%3"; +- } +- [(set_attr "type" "branch") +- (set_attr "mode" "none") +- (set_attr "length" "12")] +-) +- + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch new file mode 100644 index 00000000..d1cf4579 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch @@ -0,0 +1,28 @@ +From 0c132e74714d217108d65fca630ab497a0d8821a Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 8 Aug 2018 17:37:26 +0530 +Subject: [PATCH 43/54] [Patch,Microblaze] : previous commit broke the + handling of SI Branch compare for Microblaze 32-bit.. + +--- + gcc/config/microblaze/microblaze.md | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 2213d6e..53ea401 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2224,8 +2224,8 @@ else + (define_expand "cbranchsi4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand 1 "register_operand") +- (match_operand 2 "arith_operand" "I,i")]) ++ [(match_operand:SI 1 "register_operand") ++ (match_operand:SI 2 "arith_operand" "I,i")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch new file mode 100644 index 00000000..68791cb2 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch @@ -0,0 +1,73 @@ +From 259ed1ee33625964f5bc394ae660103b6c35510f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 11 Sep 2018 13:43:48 +0530 +Subject: [PATCH 44/54] [Patch, Microblaze] : Support of multilibs with m64 ... + +--- + gcc/config/microblaze/microblaze-c.c | 1 + + gcc/config/microblaze/t-microblaze | 15 ++++++--------- + libgcc/config/microblaze/t-microblaze | 11 +++-------- + 3 files changed, 10 insertions(+), 17 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c +index d8a1d13..6586575 100644 +--- a/gcc/config/microblaze/microblaze-c.c ++++ b/gcc/config/microblaze/microblaze-c.c +@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile) + } + if (TARGET_MB_64) + { ++ builtin_define ("__microblaze64"); + builtin_define ("__arch64__"); + builtin_define ("__microblaze64__"); + builtin_define ("__MICROBLAZE64__"); +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 9fc80b1..35ab965 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,12 +1,9 @@ +-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 +-MULTILIB_DIRNAMES = bs m mh le m64 +-MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high +-MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 +-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high ++MULTILIB_DIRNAMES = m64 bs le m mh ++MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 35021b2..8d954a4 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,16 +1,11 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ +- _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ +- $(srcdir)/config/microblaze/divdi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ +- $(srcdir)/config/microblaze/moddi3.S \ ++ $(srcdir)/config/microblaze/muldi3_hard.S \ + $(srcdir)/config/microblaze/mulsi3.S \ +- $(srcdir)/config/microblaze/muldi3.S \ + $(srcdir)/config/microblaze/stack_overflow_exit.S \ + $(srcdir)/config/microblaze/udivsi3.S \ +- $(srcdir)/config/microblaze/udivdi3.S \ + $(srcdir)/config/microblaze/umodsi3.S \ +- $(srcdir)/config/microblaze/umoddi3.S \ +- $(srcdir)/config/microblaze/divsi3_table.c \ ++ $(srcdir)/config/microblaze/divsi3_table.c +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch new file mode 100644 index 00000000..8c0bde71 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch @@ -0,0 +1,70 @@ +From 654582846ebf847b52e769eb6e015c8e486461d6 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 11 Sep 2018 14:58:00 +0530 +Subject: [PATCH 45/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign + extension issue + +--- + gcc/config/microblaze/microblaze.c | 16 ++++++++++------ + gcc/config/microblaze/microblaze.md | 2 +- + 2 files changed, 11 insertions(+), 7 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index fab79d9..6b6ca61 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2241,9 +2241,14 @@ compute_frame_size (HOST_WIDE_INT size) + + total_size += gp_reg_size; + +- /* Add 4 bytes for MSR. */ ++ /* Add 4/8 bytes for MSR. */ + if (microblaze_is_interrupt_variant ()) +- total_size += 4; ++ { ++ if (TARGET_MB_64) ++ total_size += 8; ++ else ++ total_size += 4; ++ } + + /* No space to be allocated for link register in leaf functions with no other + stack requirements. */ +@@ -2527,7 +2532,6 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; +- int val1[2]; + long l[2]; + if (code == CONST_DOUBLE) + { +@@ -2542,10 +2546,10 @@ print_operand (FILE * file, rtx op, int letter) + } + else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) + { +- val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; +- val1[1] = INTVAL (op) & 0x00000000ffffffffLL; ++ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; ++ val[1] = INTVAL (op) & 0x00000000ffffffffLL; + } +- fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); ++ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); + } + else if (code == CONST_DOUBLE) + { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 53ea401..3a6943b 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1094,7 +1094,7 @@ + case 1: + case 2: + { +- output_asm_insn ("ll%i1\t%0,%1", operands); ++ output_asm_insn ("lw%i1\t%0,%1", operands); + return "sextl32\t%0,%0"; + } + } +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch new file mode 100644 index 00000000..22bb5b2f --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch @@ -0,0 +1,306 @@ +From 48f9f9a1c6809b14e7cfdd2343df92c0de18d730 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 28 Sep 2018 11:59:12 +0530 +Subject: [PATCH 46/54] Fixed below issues: - Floating point print issues in + 64bit mode - Dejagnu Jump related issues - Added dbl instruction + +--- + gcc/config/microblaze/microblaze.c | 12 ++++- + gcc/config/microblaze/microblaze.h | 7 +++ + gcc/config/microblaze/microblaze.md | 89 ++++++++++++++++++++++++++++++------- + libgcc/config/microblaze/crti.S | 24 +++++++++- + libgcc/config/microblaze/crtn.S | 13 ++++++ + 5 files changed, 127 insertions(+), 18 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 6b6ca61..33d183e 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2536,7 +2536,12 @@ print_operand (FILE * file, rtx op, int letter) + if (code == CONST_DOUBLE) + { + if (GET_MODE (op) == DFmode) +- REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ { ++ if (TARGET_MB_64) ++ REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ else ++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ } + else + { + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); +@@ -3874,7 +3879,10 @@ microblaze_expand_divide (rtx operands[]) + gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + + insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); +- jump = emit_jump_insn_after (gen_jump (div_end_label), insn); ++ if (TARGET_MB_64) ++ jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn); ++ else ++ jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + JUMP_LABEL (jump) = div_end_label; + LABEL_NUSES (div_end_label) = 1; + emit_barrier (); +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 1e60513..e34f549 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -892,10 +892,17 @@ do { \ + /* We do this to save a few 10s of code space that would be taken up + by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION + definition in crtstuff.c. */ ++#ifdef __arch64__ ++#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ ++ asm ( SECTION_OP "\n" \ ++ "\tbrealid r15, " #FUNC "\n\t nop\n" \ ++ TEXT_SECTION_ASM_OP); ++#else + #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ + asm ( SECTION_OP "\n" \ + "\tbrlid r15, " #FUNC "\n\t nop\n" \ + TEXT_SECTION_ASM_OP); ++#endif + + /* We need to group -lm as well, since some Newlib math functions + reference __errno! */ +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 3a6943b..2669a28 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -525,6 +525,15 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "floatdidf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (float:DF (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dbl\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +@@ -1298,7 +1307,7 @@ + (define_insn "movdi_long_int" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d") + (match_operand:DI 1 "general_operand" "i"))] +- "" ++ "TARGET_MB_64" + "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -1581,7 +1590,7 @@ + return "ll%i1\t%0,%1"; + case 3: + { +- return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; ++ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; + } + case 5: + return "sl%i0\t%1,%0"; +@@ -2371,9 +2380,9 @@ else + + (define_insn "long_branch_compare" + [(set (pc) +- (if_then_else (match_operator 0 "cmp_op" +- [(match_operand 1 "register_operand" "d") +- (match_operand 2 "register_operand" "d") ++ (if_then_else (match_operator:DI 0 "cmp_op" ++ [(match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) +@@ -2495,6 +2504,20 @@ else + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- ++(define_insn "jump_64" ++ [(set (pc) ++ (label_ref (match_operand 0 "" "")))] ++ "TARGET_MB_64" ++ { ++ if (GET_CODE (operands[0]) == REG) ++ return "brea%?\t%0"; ++ else ++ return "breai%?\t%l0"; ++ } ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] +@@ -2538,19 +2561,28 @@ else + (use (label_ref (match_operand 1 "" "")))] + "" + { +- //gcc_assert (GET_MODE (operands[0]) == Pmode); +- ++ gcc_assert (GET_MODE (operands[0]) == Pmode); ++ + if (!flag_pic) +- emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); +- else +- emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); ++ { ++ if (!TARGET_MB_64) ++ emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); ++ else ++ emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); ++ } ++ else { ++ if (!TARGET_MB_64) ++ emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); ++ else ++ emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); ++ } + DONE; + } + ) + + (define_insn "tablejump_internal1" + [(set (pc) +- (match_operand 0 "register_operand" "d")) ++ (match_operand:SI 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bra%?\t%0 " +@@ -2558,11 +2590,21 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "tablejump_internal2" ++ [(set (pc) ++ (match_operand:DI 0 "register_operand" "d")) ++ (use (label_ref (match_operand 1 "" "")))] ++ "TARGET_MB_64" ++ "bra%?\t%0 " ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_expand "tablejump_internal3" + [(parallel [(set (pc) +- (plus (match_operand 0 "register_operand" "d") +- (label_ref (match_operand:SI 1 "" "")))) +- (use (label_ref (match_dup 1)))])] ++ (plus:SI (match_operand:SI 0 "register_operand" "d") ++ (label_ref:SI (match_operand:SI 1 "" "")))) ++ (use (label_ref:SI (match_dup 1)))])] + "" + "" + ) +@@ -2593,6 +2635,23 @@ else + "" + ) + ++(define_insn "" ++ [(set (pc) ++ (plus:DI (match_operand:DI 0 "register_operand" "d") ++ (label_ref:DI (match_operand 1 "" "")))) ++ (use (label_ref:DI (match_dup 1)))] ++ "TARGET_MB_64 && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0 ++ && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC ++ && flag_pic" ++ { ++ output_asm_insn ("addlk\t%0,%0,r20",operands); ++ return "bra%?\t%0"; ++} ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ ++ + ;;---------------------------------------------------------------- + ;; Function prologue/epilogue and stack allocation + ;;---------------------------------------------------------------- +@@ -3097,7 +3156,7 @@ else + ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference + ;; between "mfs" and "addik" instructions. + (define_insn "set_got" +- [(set (match_operand:SI 0 "register_operand" "=r") ++ [(set (match_operand 0 "register_operand" "=r") + (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))] + "" + "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8" +diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S +index 3386520..3d4cde2 100644 +--- a/libgcc/config/microblaze/crti.S ++++ b/libgcc/config/microblaze/crti.S +@@ -33,11 +33,32 @@ + .section .init, "ax" + .global __init + ++#ifdef __arch64__ + .weak _stack +- .set _stack, 0xffffffff ++ .set _stack, 0xffffffffffffffff + .weak _stack_end + .set _stack_end, 0 + ++ .align 3 ++__init: ++ addlik r1, r1, -32 ++ sl r15, r0, r1 ++ addlik r11, r0, _stack ++ mts rshr, r11 ++ addlik r11, r0, _stack_end ++ mts rslr, r11 ++ ++ .section .fini, "ax" ++ .global __fini ++ .align 3 ++__fini: ++ addlik r1, r1, -32 ++ sl r15, r0, r1 ++#else ++ .weak _stack ++ .set _stack, 0xffffffff ++ .weak _stack_end ++ .set _stack_end, 0 + .align 2 + __init: + addik r1, r1, -16 +@@ -53,3 +74,4 @@ __init: + __fini: + addik r1, r1, -16 + sw r15, r0, r1 ++#endif +diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S +index 04e73d7..c262ce0 100644 +--- a/libgcc/config/microblaze/crtn.S ++++ b/libgcc/config/microblaze/crtn.S +@@ -29,7 +29,19 @@ + .section .note.GNU-stack,"",%progbits + .previous + #endif ++#ifdef __arch64__ ++ .section .init, "ax" ++ ll r15, r0, r1 ++ addlik r1, r1, 32 ++ rtsd r15, 8 ++ nop + ++ .section .fini, "ax" ++ ll r15, r0, r1 ++ addlik r1, r1, 32 ++ rtsd r15, 8 ++ nop ++#else + .section .init, "ax" + lw r15, r0, r1 + rtsd r15, 8 +@@ -39,3 +51,4 @@ + lw r15, r0, r1 + rtsd r15, 8 + addik r1, r1, 16 ++#endif +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch new file mode 100644 index 00000000..f28d9f51 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch @@ -0,0 +1,135 @@ +From b09721c830dd0831f50084e2e64920f83618e3f4 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 9 Oct 2018 10:07:08 +0530 +Subject: [PATCH 47/54] -Added double arith instructions -Fixed prologue stack + pointer decrement issue + +--- + gcc/config/microblaze/microblaze.md | 78 ++++++++++++++++++++++++++++++++----- + gcc/config/microblaze/t-microblaze | 7 ++++ + 2 files changed, 76 insertions(+), 9 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 2669a28..dca61d6 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -525,6 +525,66 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "fix_truncsfsi2" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (fix:SI (match_operand:SF 1 "register_operand" "d")))] ++ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" ++ "fint\t%0,%1" ++ [(set_attr "type" "fint") ++ (set_attr "mode" "SF") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "adddf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (plus:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dadd\t%0,%1,%2" ++ [(set_attr "type" "fadd") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "subdf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (minus:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "drsub\t%0,%2,%1" ++ [(set_attr "type" "frsub") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "muldf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (mult:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dmul\t%0,%1,%2" ++ [(set_attr "type" "fmul") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "divdf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (div:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "ddiv\t%0,%2,%1" ++ [(set_attr "type" "fdiv") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "sqrtdf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dsqrt\t%0,%1" ++ [(set_attr "type" "fsqrt") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (float:DF (match_operand:DI 1 "register_operand" "d")))] +@@ -534,13 +594,13 @@ + (set_attr "mode" "DF") + (set_attr "length" "4")]) + +-(define_insn "fix_truncsfsi2" +- [(set (match_operand:SI 0 "register_operand" "=d") +- (fix:SI (match_operand:SF 1 "register_operand" "d")))] +- "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" +- "fint\t%0,%1" +- [(set_attr "type" "fint") +- (set_attr "mode" "SF") ++(define_insn "floatdfdi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (float:DI (match_operand:DF 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dlong\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "DI") + (set_attr "length" "4")]) + + ;;---------------------------------------------------------------- +@@ -658,8 +718,8 @@ + "TARGET_MB_64" + "@ + rsubl\t%0,%2,%1 +- addik\t%0,%z1,-%2 +- addik\t%0,%z1,-%2" ++ addlik\t%0,%z1,-%2 ++ addlik\t%0,%z1,-%2" + [(set_attr "type" "arith,no_delay_arith,no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "4,4,4")]) +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 35ab965..dfef45c 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,6 +1,13 @@ + MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high + MULTILIB_DIRNAMES = m64 bs le m mh + MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64 ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch new file mode 100644 index 00000000..9a214d55 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch @@ -0,0 +1,37 @@ +From 1ed548dd5993b8c3e58ef393467bdeea49c437be Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 12 Oct 2018 16:07:36 +0530 +Subject: [PATCH 48/54] Fixed the issue in the delay slot with swap + instructions + +--- + gcc/config/microblaze/microblaze.md | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index dca61d6..d037843 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -441,6 +441,9 @@ + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] + "TARGET_REORDER" + "swapb %0, %1" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "4")] + ) + + (define_insn "bswaphi2" +@@ -449,6 +452,9 @@ + "TARGET_REORDER" + "swapb %0, %1 + swaph %0, %0" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "8")] + ) + + ;;---------------------------------------------------------------- +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch new file mode 100644 index 00000000..a682bc19 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch @@ -0,0 +1,256 @@ +From 1c889b64454f63f164f34d79d891d91b0bb4731f Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sat, 13 Oct 2018 21:12:43 +0530 +Subject: [PATCH 49/54] Fixed the load store issue with the 32bit arith + libraries + +--- + libgcc/config/microblaze/divsi3.S | 25 ++++++++++++++++++++++++- + libgcc/config/microblaze/modsi3.S | 26 +++++++++++++++++++++++++- + libgcc/config/microblaze/mulsi3.S | 3 +++ + libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++- + libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++- + 5 files changed, 98 insertions(+), 4 deletions(-) + +diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S +index 663d398..7e7d875 100644 +--- a/libgcc/config/microblaze/divsi3.S ++++ b/libgcc/config/microblaze/divsi3.S +@@ -41,6 +41,17 @@ + .globl __divsi3 + .ent __divsi3 + .type __divsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__divsi3: ++ .frame r1,0,r15 ++ ++ ADDIK r1,r1,-32 ++ SLI r28,r1,0 ++ SLI r29,r1,8 ++ SLI r30,r1,16 ++ SLI r31,r1,24 ++#else + __divsi3: + .frame r1,0,r15 + +@@ -49,7 +60,7 @@ __divsi3: + SWI r29,r1,4 + SWI r30,r1,8 + SWI r31,r1,12 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero + BGEID r5,$LaR5_Pos +@@ -89,6 +100,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r28,r1,0 ++ LLI r29,r1,8 ++ LLI r30,r1,16 ++ LLI r31,r1,24 ++ ADDLIK r1,r1,32 ++ RTSD r15,8 ++ NOP ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + LWI r28,r1,0 +@@ -97,6 +119,7 @@ $LaRETURN_HERE: + LWI r31,r1,12 + RTSD r15,8 + ADDIK r1,r1,16 ++#endif + .end __divsi3 + .size __divsi3, . - __divsi3 + +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index 71b56e30..7e85064 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -41,6 +41,17 @@ + .globl __modsi3 + .ent __modsi3 + .type __modsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__modsi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-32 ++ sli r28,r1,0 ++ sli r29,r1,8 ++ sli r30,r1,16 ++ sli r31,r1,24 ++#else + __modsi3: + .frame r1,0,r15 + +@@ -49,6 +60,7 @@ __modsi3: + swi r29,r1,4 + swi r30,r1,8 + swi r31,r1,12 ++#endif + + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero +@@ -88,6 +100,18 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 [Both mod as well as div are 0] ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r28,r1,0 ++ lli r29,r1,8 ++ lli r30,r1,16 ++ lli r31,r1,24 ++ addik r1,r1,32 ++ rtsd r15,8 ++ nop ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + lwi r28,r1,0 +@@ -95,7 +119,7 @@ $LaRETURN_HERE: + lwi r30,r1,8 + lwi r31,r1,12 + rtsd r15,8 +- addik r1,r1,16 ++#endif + .end __modsi3 + .size __modsi3, . - __modsi3 + +diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S +index 40b0b15..31a73c2 100644 +--- a/libgcc/config/microblaze/mulsi3.S ++++ b/libgcc/config/microblaze/mulsi3.S +@@ -41,6 +41,9 @@ + .globl __mulsi3 + .ent __mulsi3 + .type __mulsi3,@function ++#ifdef __arch64__ ++ .align 3 ++#endif + __mulsi3: + .frame r1,0,r15 + add r3,r0,r0 +diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S +index 2aef8ed..94adb6a 100644 +--- a/libgcc/config/microblaze/udivsi3.S ++++ b/libgcc/config/microblaze/udivsi3.S +@@ -41,6 +41,16 @@ + .globl __udivsi3 + .ent __udivsi3 + .type __udivsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__udivsi3: ++ .frame r1,0,r15 ++ ++ ADDLIK r1,r1,-24 ++ SLI r29,r1,0 ++ SLI r30,r1,8 ++ SLI r31,r1,16 ++#else + __udivsi3: + .frame r1,0,r15 + +@@ -48,7 +58,7 @@ __udivsi3: + SWI r29,r1,0 + SWI r30,r1,4 + SWI r31,r1,8 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQID r5,$LaResult_Is_Zero # Result is Zero + ADDIK r30,r0,0 # Clear mod +@@ -98,6 +108,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++ # Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r29,r1,0 ++ LLI r30,r1,8 ++ LLI r31,r1,16 ++ ADDIK r1,r1,24 ++ RTSD r15,8 ++ NOP ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + LWI r29,r1,0 +@@ -105,5 +126,6 @@ $LaRETURN_HERE: + LWI r31,r1,8 + RTSD r15,8 + ADDIK r1,r1,12 ++#endif + .end __udivsi3 + .size __udivsi3, . - __udivsi3 +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index a2582d0..00b3bdf 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -41,6 +41,16 @@ + .globl __umodsi3 + .ent __umodsi3 + .type __umodsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__umodsi3: ++ .frame r1,0,r15 ++ ++ addik r1,r1,-24 ++ swi r29,r1,0 ++ swi r30,r1,8 ++ swi r31,r1,16 ++#else + __umodsi3: + .frame r1,0,r15 + +@@ -48,7 +58,7 @@ __umodsi3: + swi r29,r1,0 + swi r30,r1,4 + swi r31,r1,8 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQId r5,$LaResult_Is_Zero # Result is Zero + ADDIK r3,r0,0 # Clear div +@@ -101,6 +111,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r29,r1,0 ++ lli r30,r1,8 ++ lli r31,r1,16 ++ addlik r1,r1,24 ++ rtsd r15,8 ++ nop ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + lwi r29,r1,0 +@@ -108,5 +129,6 @@ $LaRETURN_HERE: + lwi r31,r1,8 + rtsd r15,8 + addik r1,r1,12 ++#endif + .end __umodsi3 + .size __umodsi3, . - __umodsi3 +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch new file mode 100644 index 00000000..95a26db2 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch @@ -0,0 +1,25 @@ +From 751a01ce1eeaffcd41c504b9bf44868345b45da0 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 15 Oct 2018 12:00:10 +0530 +Subject: [PATCH 50/54] extending the Dwarf support to 64bit Microblaze + +--- + gcc/config/microblaze/microblaze.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index e34f549..0a5ff0a 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe; + /* Use DWARF 2 debugging information by default. */ + #define DWARF2_DEBUGGING_INFO 1 + #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG +-#define DWARF2_ADDR_SIZE 4 ++#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4) + + /* Target machine storage layout */ + +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch new file mode 100644 index 00000000..574037ec --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch @@ -0,0 +1,29 @@ +From 295046d0a63148fb5a685ae2bd7a06489274c72a Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 16 Oct 2018 07:55:46 +0530 +Subject: [PATCH 51/54] fixing the typo errors in umodsi3 file + +--- + libgcc/config/microblaze/umodsi3.S | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index 00b3bdf..9bf65c3 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -47,9 +47,9 @@ __umodsi3: + .frame r1,0,r15 + + addik r1,r1,-24 +- swi r29,r1,0 +- swi r30,r1,8 +- swi r31,r1,16 ++ sli r29,r1,0 ++ sli r30,r1,8 ++ sli r31,r1,16 + #else + __umodsi3: + .frame r1,0,r15 +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch new file mode 100644 index 00000000..95d39bb2 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch @@ -0,0 +1,68 @@ +From d55eff09f175ddbc66e4e800fa5650ce9e2f599e Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Wed, 17 Oct 2018 16:56:14 +0530 +Subject: [PATCH 52/54] fixing the 32bit LTO related issue9(1014024) + +--- + gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- + 1 file changed, 14 insertions(+), 10 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 0a5ff0a..740b8d9 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe; + #define WORD_REGISTER_OPERATIONS 1 + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND +-/* +-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ +- if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ +- (MODE) = TARGET_MB_64 ? DImode : SImode; +-*/ ++ ++#ifndef __arch64__ ++#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ ++ if (GET_MODE_CLASS (MODE) == MODE_INT \ ++ && GET_MODE_SIZE (MODE) < 4) \ ++ (MODE) = SImode; ++#endif ++ + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info; + + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + ++#ifdef __aarch64__ + #define LIBCALL_VALUE(MODE) \ + gen_rtx_REG (MODE,GP_RETURN) +- +-/*#define LIBCALL_VALUE(MODE) \ ++#else ++#define LIBCALL_VALUE(MODE) \ + gen_rtx_REG ( \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), GP_RETURN) +-*/ ++#endif ++ + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +@@ -518,7 +522,7 @@ typedef struct microblaze_args + /* 4 insns + 2 words of data. */ + #define TRAMPOLINE_SIZE (6 * 4) + +-#define TRAMPOLINE_ALIGNMENT 64 ++#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32) + + #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch new file mode 100644 index 00000000..e992075b --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch @@ -0,0 +1,25 @@ +From 3e7161218dc8b4dd84ad8d31f6dbaa7c256e7a82 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 19 Oct 2018 14:26:25 +0530 +Subject: [PATCH 53/54] Fixed the missing stack adjustment in prologue of + modsi3 function + +--- + libgcc/config/microblaze/modsi3.S | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index 7e85064..46ff34a 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -119,6 +119,7 @@ $LaRETURN_HERE: + lwi r30,r1,8 + lwi r31,r1,12 + rtsd r15,8 ++ addik r1,r1,16 + #endif + .end __modsi3 + .size __modsi3, . - __modsi3 +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch new file mode 100644 index 00000000..afb88d35 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch @@ -0,0 +1,29 @@ +From a89b3e6902d7835129ad178f6af896eba15c5d5e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 24 Oct 2018 18:31:04 +0530 +Subject: [PATCH 54/54] [Patch,Microblaze] : corrected SPN for dlong + instruction mapping. + +--- + gcc/config/microblaze/microblaze.md | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index d037843..cbd7e77 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -600,9 +600,9 @@ + (set_attr "mode" "DF") + (set_attr "length" "4")]) + +-(define_insn "floatdfdi2" ++(define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") +- (float:DI (match_operand:DF 1 "register_operand" "d")))] ++ (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] + "TARGET_MB_64" + "dlong\t%0,%1" + [(set_attr "type" "fcvt") +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend deleted file mode 100644 index 9770af61..00000000 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend +++ /dev/null @@ -1,38 +0,0 @@ -# Add MicroBlaze Patches (only when using MicroBlaze) -FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-7:" -SRC_URI_append_microblaze = " \ - file://0001-Revert.patch \ - file://0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch \ - file://0003-PR-target-83013.patch \ - file://0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch \ - file://0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch \ - file://0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch \ - file://0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch \ - file://0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch \ - file://0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch \ - file://0010-Fix-atomic-side-effects.patch \ - file://0011-Fix-atomic-boolean-return-value.patch \ - file://0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch \ - file://0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch \ - file://0014-Removed-MicroBlaze-moddi3-routinue.patch \ - file://0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch \ - file://0016-MicroBlaze-use-bralid-for-profiler-calls.patch \ - file://0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch \ - file://0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch \ - file://0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch \ - file://0020-Modified-MicroBlaze-trap-instruction.patch \ - file://0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch \ - file://0022-Inline-Expansion-of-fsqrt-builtin.patch \ - file://0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch \ - file://0024-8-stage-pipeline-for-microblaze.patch \ - file://0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch \ - file://0026-Fix-internal-compiler-error-with-msmall-divides.patch \ - file://0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch \ - file://0028-Add-new-bit-field-instructions.patch \ - file://0029-Fix-bug-in-MB-version-calculation.patch \ - file://0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch \ - file://0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch \ - file://0032-MicroBlaze-remove-bitfield-instructions-macros.patch \ - file://0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch \ - " - diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend new file mode 100644 index 00000000..a1148a8f --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend @@ -0,0 +1,58 @@ +# Add MicroBlaze Patches (only when using MicroBlaze) +FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-8:" +SRC_URI_append_microblaze = " \ +file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \ + file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \ + file://0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch \ + file://0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \ + file://0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \ + file://0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch \ + file://0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \ + file://0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \ + file://0009-Patch-microblaze-Fix-atomic-side-effects.patch \ + file://0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch \ + file://0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \ + file://0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \ + file://0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch \ + file://0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch \ + file://0015-Patch-microblaze-Disable-fivopts-by-default.patch \ + file://0016-Patch-microblaze-Removed-moddi3-routinue.patch \ + file://0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch \ + file://0018-Patch-microblaze-Add-optimized-lshrsi3.patch \ + file://0019-Patch-microblaze-Modified-trap-instruction.patch \ + file://0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \ + file://0021-Patch-microblaze-Add-cbranchsi4_reg.patch \ + file://0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \ + file://0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch \ + file://0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \ + file://0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \ + file://0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \ + file://0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch \ + file://0028-Patch-microblaze-Correct-the-const-high-double-immed.patch \ + file://0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \ + file://0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \ + file://0031-Patch-microblaze-Add-new-bit-field-instructions.patch \ + file://0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch \ + file://0033-Fixing-the-bug-in-the-bit-field-instruction.patch \ + file://0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch \ + file://0035-Fixing-the-issue-with-the-builtin_alloc.patch \ + file://0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch \ + file://0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch \ + file://0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \ + file://0039-Intial-commit-of-64-bit-Microblaze.patch \ + file://0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch \ + file://0041-Intial-commit-for-64bit-MB-sources.patch \ + file://0042-re-arrangement-of-the-compare-branches.patch \ + file://0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch \ + file://0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch \ + file://0045-Fixed-issues-like.patch \ + file://0046-Fixed-below-issues.patch \ + file://0047-Added-double-arith-instructions.patch \ + file://0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \ + file://0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \ + file://0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch \ + file://0051-fixing-the-typo-errors-in-umodsi3-file.patch \ + file://0052-fixing-the-32bit-LTO-related-issue9-1014024.patch \ + file://0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \ + file://0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \ +" |