diff options
| -rw-r--r-- | recipes-kernel/linux/linux-imx/arm-mach-mx6-fix-pll4-set_rate-callback.patch | 44 | ||||
| -rw-r--r-- | recipes-kernel/linux/linux-imx_3.0.35.bb | 1 |
2 files changed, 45 insertions, 0 deletions
diff --git a/recipes-kernel/linux/linux-imx/arm-mach-mx6-fix-pll4-set_rate-callback.patch b/recipes-kernel/linux/linux-imx/arm-mach-mx6-fix-pll4-set_rate-callback.patch new file mode 100644 index 0000000..a3197fb --- /dev/null +++ b/recipes-kernel/linux/linux-imx/arm-mach-mx6-fix-pll4-set_rate-callback.patch @@ -0,0 +1,44 @@ +From patchwork Wed May 29 12:23:55 2013 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: arm/mach-mx6: fix pll4 set_rate callback +Date: Wed, 29 May 2013 12:23:55 -0000 +From: Alexander Smirnov <alex.bluesman.smirnov@gmail.com> +X-Patchwork-Id: 50693 +Message-Id: <1369830235-8476-2-git-send-email-alex.bluesman.smirnov@gmail.com> +To: meta-freescale@yoctoproject.org +Cc: Alexander Smirnov <alex.bluesman.smirnov@gmail.com> + +There is single method to set clock-rate for both audio and video pll-s +in i.MX6q clock system implementation. That's possible due to they have +similar set of registers with a different bases. But there is also one +common register: CCM_ANALOG_MISC2, which contains post-dividers. + +In current implementation, independently of whether audio or video clock +is going to be set, the mask 0xc0000000 is applied to MISC2 register. +This means, that if the audio clock rate is changed, the video clock +post-dividers possibly will be corrupted. + +This patch fixes the issue described above. + +Signed-off-by: Alexander Smirnov <alex.bluesman.smirnov@gmail.com> + +--- +arch/arm/mach-mx6/clock.c | 3 ++- + 1 files changed, 2 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c +index 8c590b7..8706c32 100644 +--- a/arch/arm/mach-mx6/clock.c ++++ b/arch/arm/mach-mx6/clock.c +@@ -1023,7 +1023,8 @@ static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate) + __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET); + __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET); + +- if (rev >= IMX_CHIP_REVISION_1_1) { ++ if ((rev >= IMX_CHIP_REVISION_1_1) && ++ (pllbase == PLL5_VIDEO_BASE_ADDR)) { + reg = __raw_readl(ANA_MISC2_BASE_ADDR) + & ~ANADIG_ANA_MISC2_CONTROL3_MASK; + reg |= control3 << ANADIG_ANA_MISC2_CONTROL3_OFFSET; diff --git a/recipes-kernel/linux/linux-imx_3.0.35.bb b/recipes-kernel/linux/linux-imx_3.0.35.bb index ce4bac3..6ee2247 100644 --- a/recipes-kernel/linux/linux-imx_3.0.35.bb +++ b/recipes-kernel/linux/linux-imx_3.0.35.bb @@ -10,3 +10,4 @@ COMPATIBLE_MACHINE = "(mx6)" # Revision of 4.0.0 branch SRCREV = "572fd62b7e2d70ef83e2ca8fe9895fe6f1531f8a" LOCALVERSION = "-4.0.0+yocto" +SRC_URI += "file://arm-mach-mx6-fix-pll4-set_rate-callback.patch" |