From dae2ee6b39e11dbf47f644c4c8cca66373485f6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 22 Aug 2018 16:44:56 +0200 Subject: [PATCH 5226/5725] drm/amdgpu: enable GTT PD/PT for raven v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Should work on Vega10 as well, but with an obvious performance hit. Older APUs can be enabled as well, but will probably be more work. v2: fix error checking v3: use more general check Change-Id: I5194cf3cb267032198d5f16c0be95e39838515b7 Signed-off-by: Christian König Acked-by: Andrey Grodzovsky Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 4b6d0cc..c5c2d6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -308,6 +308,9 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, list_move(&bo_base->vm_status, &vm->moved); spin_unlock(&vm->moved_lock); } else { + r = amdgpu_ttm_alloc_gart(&bo->tbo); + if (r) + break; list_move(&bo_base->vm_status, &vm->relocated); } } @@ -384,6 +387,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, if (r) goto error; + r = amdgpu_ttm_alloc_gart(&bo->tbo); + if (r) + return r; + r = amdgpu_job_alloc_with_ib(adev, 64, &job); if (r) goto error; @@ -434,6 +441,37 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, } /** + * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation + * + * @adev: amdgpu_device pointer + * @vm: requesting vm + * @bp: resulting BO allocation parameters + */ +static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, + int level, struct amdgpu_bo_param *bp) +{ + memset(bp, 0, sizeof(*bp)); + + bp->size = amdgpu_vm_bo_size(adev, level); + bp->byte_align = AMDGPU_GPU_PAGE_SIZE; + bp->domain = AMDGPU_GEM_DOMAIN_VRAM; + if (bp->size <= PAGE_SIZE && adev->asic_type >= CHIP_VEGA10 && + adev->flags & AMD_IS_APU) + bp->domain |= AMDGPU_GEM_DOMAIN_GTT; + bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain); + bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_CPU_GTT_USWC; + if (vm->use_cpu_for_update) + bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + else + bp->flags |= AMDGPU_GEM_CREATE_SHADOW | + AMDGPU_GEM_CREATE_NO_CPU_ACCESS; + bp->type = ttm_bo_type_kernel; + if (vm->root.base.bo) + bp->resv = vm->root.base.bo->tbo.resv; +} + +/** * amdgpu_vm_alloc_levels - allocate the PD/PT levels * * @adev: amdgpu_device pointer -- 2.7.4