From eee2e2622ae43d135a1a9d1243ddf3416242bb66 Mon Sep 17 00:00:00 2001
From: Ken Wang <Ken.Wang@amd.com>
Date: Fri, 29 Sep 2017 15:41:43 +0800
Subject: [PATCH 1066/4131] drm/amdgpu: correct reference clock value on vega10

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f0c9904..29d8b82 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -279,6 +279,9 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 }
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
+        if (adev->asic_type == CHIP_VEGA10)
+                return 27000;
+        else
 	return adev->clock.spll.reference_freq;
 }
 
-- 
2.7.4