From 227cdc285348863b9b06246a3e03d52cefb75f31 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Tue, 13 Mar 2018 15:27:06 +0800 Subject: [PATCH 3803/4131] drm/amd/pp: Delete dead code on cz_clockpowergating.c Change-Id: I3f64b811f304223b9a80628b1c09a643256f6cd9 Reviewed-by: Alex Deucher Reviewed-by: Evan Quan Signed-off-by: Rex Zhu --- .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 78 ---------------------- .../drm/amd/powerplay/hwmgr/cz_clockpowergating.h | 3 - 2 files changed, 81 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c index 416abeb..01e5612 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c @@ -25,84 +25,6 @@ #include "cz_clockpowergating.h" #include "cz_ppsmc.h" -/* PhyID -> Status Mapping in DDI_PHY_GEN_STATUS - 0 GFX0L (3:0), (27:24), - 1 GFX0H (7:4), (31:28), - 2 GFX1L (3:0), (19:16), - 3 GFX1H (7:4), (23:20), - 4 DDIL (3:0), (11: 8), - 5 DDIH (7:4), (15:12), - 6 DDI2L (3:0), ( 3: 0), - 7 DDI2H (7:4), ( 7: 4), -*/ -#define DDI_PHY_GEN_STATUS_VAL(phyID) (1 << ((3 - ((phyID & 0x07)/2))*8 + (phyID & 0x01)*4)) -#define IS_PHY_ID_USED_BY_PLL(PhyID) (((0xF3 & (1 << PhyID)) & 0xFF) ? true : false) - - -int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating) -{ - int ret = 0; - - switch (block) { - case PHM_AsicBlock_UVD_MVC: - case PHM_AsicBlock_UVD: - case PHM_AsicBlock_UVD_HD: - case PHM_AsicBlock_UVD_SD: - if (gating == PHM_ClockGateSetting_StaticOff) - ret = cz_dpm_powerdown_uvd(hwmgr); - else - ret = cz_dpm_powerup_uvd(hwmgr); - break; - case PHM_AsicBlock_GFX: - default: - break; - } - - return ret; -} - - -bool cz_phm_is_safe_for_asic_block(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, enum PHM_AsicBlock block) -{ - return true; -} - - -int cz_phm_enable_disable_gfx_power_gating(struct pp_hwmgr *hwmgr, bool enable) -{ - return 0; -} - -int cz_phm_smu_power_up_down_pcie(struct pp_hwmgr *hwmgr, uint32_t target, bool up, uint32_t args) -{ - /* TODO */ - return 0; -} - -int cz_phm_initialize_display_phy_access(struct pp_hwmgr *hwmgr, bool initialize, bool accesshw) -{ - /* TODO */ - return 0; -} - -int cz_phm_get_display_phy_access_info(struct pp_hwmgr *hwmgr) -{ - /* TODO */ - return 0; -} - -int cz_phm_gate_unused_display_phys(struct pp_hwmgr *hwmgr) -{ - /* TODO */ - return 0; -} - -int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr) -{ - /* TODO */ - return 0; -} - int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h index 92f707b..08d393f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h @@ -25,10 +25,7 @@ #define _CZ_CLOCK_POWER_GATING_H_ #include "cz_hwmgr.h" -#include "pp_asicblocks.h" -extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating); -extern const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master; extern void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); extern void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); extern int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); -- 2.7.4