From c66d5f9b8236a782c7810ada7245e9857def1ed8 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Tue, 24 Nov 2015 10:53:27 -0500 Subject: [PATCH 0112/1110] drm/amd/amdgpu: enable uvd&vce clock gating for Fiji. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Alex Deucher Reviewed-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Eric Huang --- drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 89f5a1f..d94c625 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1443,7 +1443,8 @@ static int vi_common_early_init(void *handle) break; case CHIP_FIJI: adev->has_uvd = true; - adev->cg_flags = 0; + adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG | + AMDGPU_CG_SUPPORT_VCE_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x3c; break; -- 2.7.4