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-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch51
1 files changed, 51 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch
new file mode 100644
index 00000000..4aed01d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch
@@ -0,0 +1,51 @@
+From d691a52f1ffe68a039c5f235860fef167ba339b8 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 18 Nov 2019 13:31:04 -0500
+Subject: [PATCH 4715/4736] drm/amd/display: Extend DMCUB offload testing into
+ dcn20/21
+
+[Why]
+To quickly validate whether DMCUB is running and accepting commands for
+offload testing we want to intercept a common sequence as part of
+modeset programming.
+
+[How]
+OTG enable will cause the most impact in terms of golden register
+changes and it's a single register write.
+
+This approach was previously done in dcn10 code when it was shared with
+dcn20 but it wasn't ported over to the dcn20 code.
+
+Port over start, execute and wait sequence into dcn20_optc.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index f5854a5d2b76..673c83e2afd4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -59,11 +59,16 @@ bool optc2_enable_crtc(struct timing_generator *optc)
+ REG_UPDATE(CONTROL,
+ VTG0_ENABLE, 1);
+
++ REG_SEQ_START();
++
+ /* Enable CRTC */
+ REG_UPDATE_2(OTG_CONTROL,
+ OTG_DISABLE_POINT_CNTL, 3,
+ OTG_MASTER_EN, 1);
+
++ REG_SEQ_SUBMIT();
++ REG_SEQ_WAIT_DONE();
++
+ return true;
+ }
+
+--
+2.17.1
+