diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch new file mode 100644 index 00000000..6f15b44f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch @@ -0,0 +1,68 @@ +From ef14a8387788a849b24a54f954dbc14a807f10d4 Mon Sep 17 00:00:00 2001 +From: Joseph Gravenor <joseph.gravenor@amd.com> +Date: Tue, 12 Nov 2019 17:48:36 -0500 +Subject: [PATCH 4697/4736] drm/amd/display: update sr latency for renoir when + using lpddr4 + +[Why] +DF team has produced more optimized sr latency numbers, for lpddr4 + +[How] +change the sr laency in the lpddr4 wm table to the new latency +number + +Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +index 901e7035bf8e..37230d3d94a0 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +@@ -563,32 +563,32 @@ struct wm_table lpddr4_wm_table = { + .wm_inst = WM_A, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, +- .sr_exit_time_us = 12.5, +- .sr_enter_plus_exit_time_us = 17.0, ++ .sr_exit_time_us = 5.32, ++ .sr_enter_plus_exit_time_us = 6.38, + .valid = true, + }, + { + .wm_inst = WM_B, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, +- .sr_exit_time_us = 12.5, +- .sr_enter_plus_exit_time_us = 17.0, ++ .sr_exit_time_us = 9.82, ++ .sr_enter_plus_exit_time_us = 11.196, + .valid = true, + }, + { + .wm_inst = WM_C, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, +- .sr_exit_time_us = 12.5, +- .sr_enter_plus_exit_time_us = 17.0, ++ .sr_exit_time_us = 9.89, ++ .sr_enter_plus_exit_time_us = 11.24, + .valid = true, + }, + { + .wm_inst = WM_D, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, +- .sr_exit_time_us = 12.5, +- .sr_enter_plus_exit_time_us = 17.0, ++ .sr_exit_time_us = 9.748, ++ .sr_enter_plus_exit_time_us = 11.102, + .valid = true, + }, + } +-- +2.17.1 + |