diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch new file mode 100644 index 00000000..2f211973 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch @@ -0,0 +1,47 @@ +From 9dfa55f00ad9fc538d374cfc59d35b63b51f653a Mon Sep 17 00:00:00 2001 +From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com> +Date: Thu, 7 Nov 2019 16:30:04 -0500 +Subject: [PATCH 4684/4736] drm/amd/display: Change the delay time before + enabling FEC + +[why] +DP spec requires 1000 symbols delay between the end of link training +and enabling FEC in the stream. Currently we are using 1 miliseconds +delay which is not accurate. + +[how] +One lane RBR should have the maximum time for transmitting 1000 LL +codes which is 6.173 us. So using 7 microseconds delay instead of +1 miliseconds. + +Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> +Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> +Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +index 537b4dee8f22..b10019106030 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +@@ -3951,7 +3951,14 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) + if (link_enc->funcs->fec_set_enable && + link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { + if (link->fec_state == dc_link_fec_ready && enable) { +- msleep(1); ++ /* Accord to DP spec, FEC enable sequence can first ++ * be transmitted anytime after 1000 LL codes have ++ * been transmitted on the link after link training ++ * completion. Using 1 lane RBR should have the maximum ++ * time for transmitting 1000 LL codes which is 6.173 us. ++ * So use 7 microseconds delay instead. ++ */ ++ udelay(7); + link_enc->funcs->fec_set_enable(link_enc, true); + link->fec_state = dc_link_fec_enabled; + } else if (link->fec_state == dc_link_fec_enabled && !enable) { +-- +2.17.1 + |