diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch | 103 |
1 files changed, 103 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch new file mode 100644 index 00000000..f6319283 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch @@ -0,0 +1,103 @@ +From 05da4bf83601928e4f9292175592c4cbf74ef0cd Mon Sep 17 00:00:00 2001 +From: Eric Yang <Eric.Yang2@amd.com> +Date: Sun, 10 Nov 2019 12:08:02 -0500 +Subject: [PATCH 4682/4736] drm/amd/display: fix dprefclk and ss percentage + reading on RN + +[Why] +Before was using HW counter value to determine the dprefclk. Which +take into account ss, but has large variation, not good enough for +generating audio dto. Also, the bios parser code to get the ss +percentage was not working. + +[How] +After this change, dprefclk is hard coded, same as on RV. We don't +expect this to change on Renoir. Modified bios parser code to get +the right ss percentage. + +Change-Id: Ifed07a5d523b213769b6f7ed4f207cf2dc0108cd +Signed-off-by: Eric Yang <Eric.Yang2@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com> +--- + .../gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 + + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 16 +++------------- + drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 + + 3 files changed, 5 insertions(+), 13 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +index 8b2426f14519..42babd82ce6b 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +@@ -832,6 +832,7 @@ static enum bp_result bios_parser_get_spread_spectrum_info( + case 1: + return get_ss_info_v4_1(bp, signal, index, ss_info); + case 2: ++ case 3: + return get_ss_info_v4_2(bp, signal, index, ss_info); + default: + break; +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +index 89ed230cdb26..307c8540e36f 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +@@ -675,7 +675,6 @@ void rn_clk_mgr_construct( + { + struct dc_debug_options *debug = &ctx->dc->debug; + struct dpm_clocks clock_table = { 0 }; +- struct clk_state_registers_and_bypass s = { 0 }; + + clk_mgr->base.ctx = ctx; + clk_mgr->base.funcs = &dcn21_funcs; +@@ -695,7 +694,6 @@ void rn_clk_mgr_construct( + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { + dcn21_funcs.update_clocks = dcn2_update_clocks_fpga; + clk_mgr->base.dentist_vco_freq_khz = 3600000; +- clk_mgr->base.dprefclk_khz = 600000; + } else { + struct clk_log_info log_info = {0}; + +@@ -706,24 +704,16 @@ void rn_clk_mgr_construct( + if (clk_mgr->base.dentist_vco_freq_khz == 0) + clk_mgr->base.dentist_vco_freq_khz = 3600000; + +- rn_dump_clk_registers(&s, &clk_mgr->base, &log_info); +- /* Convert dprefclk units from MHz to KHz */ +- /* Value already divided by 10, some resolution lost */ +- clk_mgr->base.dprefclk_khz = s.dprefclk * 1000; +- +- /* in case we don't get a value from the register, use default */ +- if (clk_mgr->base.dprefclk_khz == 0) { +- ASSERT(clk_mgr->base.dprefclk_khz == 600000); +- clk_mgr->base.dprefclk_khz = 600000; +- } +- + if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { + rn_bw_params.wm_table = lpddr4_wm_table; + } else { + rn_bw_params.wm_table = ddr4_wm_table; + } ++ /* Saved clocks configured at boot for debug purposes */ ++ rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info); + } + ++ clk_mgr->base.dprefclk_khz = 600000; + dce_clock_read_ss_info(clk_mgr); + + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +index 026e6a2a2c44..c10cb4b54fae 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +@@ -196,6 +196,7 @@ struct clk_mgr { + int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes + int dentist_vco_freq_khz; + #ifdef CONFIG_DRM_AMD_DC_DCN2_1 ++ struct clk_state_registers_and_bypass boot_snapshot; + struct clk_bw_params *bw_params; + #endif + }; +-- +2.17.1 + |