diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch | 2772 |
1 files changed, 2772 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch new file mode 100644 index 00000000..9fc92880 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch @@ -0,0 +1,2772 @@ +From ff94007b6f9295e74823b8083017abfe9c10e5a5 Mon Sep 17 00:00:00 2001 +From: Anthony Koo <Anthony.Koo@amd.com> +Date: Tue, 5 Nov 2019 13:17:30 -0500 +Subject: [PATCH 4668/4736] drm/amd/display: add separate of private hwss + functions + +[Why] +Some function pointers in the hwss function pointer table are +meant to be hw sequencer entry points to be called from dc. + +However some of those function pointers are not meant to +be entry points, but instead used as a code reuse/inheritance +tool called directly by other hwss functions, not by dc. + +Therefore, we want a more clear separation of which functions +we determine to be interface functions vs the functions we +use within hwss. + +[How] +DC interface functions will be stored in: + struct hw_sequencer_funcs +Functions used within HWSS will be stored in: + struct hwseq_private_funcs + +Also compilation fix for CONFIG_DRM_AMD_DC_DCN2_0 and CONFIG_DRM_AMD_DC_DCN2_0 +are done +Change-Id: Ia8d8be52879c996de697011d0d57feee11267a19 +Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com> +--- + drivers/gpu/drm/amd/display/dc/Makefile | 11 +- + drivers/gpu/drm/amd/display/dc/core/dc.c | 56 ++- + .../gpu/drm/amd/display/dc/core/dc_debug.c | 1 - + .../gpu/drm/amd/display/dc/core/dc_resource.c | 3 +- + .../gpu/drm/amd/display/dc/core/dc_stream.c | 9 +- + .../gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +- + .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 6 +- + .../display/dc/dce100/dce100_hw_sequencer.c | 3 +- + .../display/dc/dce100/dce100_hw_sequencer.h | 1 + + .../display/dc/dce110/dce110_hw_sequencer.c | 81 ++-- + .../display/dc/dce110/dce110_hw_sequencer.h | 1 + + .../amd/display/dc/dce110/dce110_resource.c | 3 +- + .../display/dc/dce112/dce112_hw_sequencer.c | 2 +- + .../display/dc/dce112/dce112_hw_sequencer.h | 1 + + .../display/dc/dce120/dce120_hw_sequencer.c | 2 +- + .../display/dc/dce120/dce120_hw_sequencer.h | 1 + + .../amd/display/dc/dce80/dce80_hw_sequencer.c | 2 +- + .../amd/display/dc/dce80/dce80_hw_sequencer.h | 1 + + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 128 +++--- + .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 1 + + .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 38 +- + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 71 ++-- + .../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 3 + + .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 54 +-- + .../drm/amd/display/dc/dcn21/dcn21_hwseq.c | 1 + + .../drm/amd/display/dc/dcn21/dcn21_hwseq.h | 2 + + .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 63 +-- + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 385 +++++------------- + .../amd/display/dc/inc/hw_sequencer_private.h | 156 +++++++ + 29 files changed, 613 insertions(+), 475 deletions(-) + create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h + +diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile +index 38ef29719400..57e12b6c48fa 100644 +--- a/drivers/gpu/drm/amd/display/dc/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/Makefile +@@ -25,9 +25,16 @@ + + DC_LIBS = basics bios calcs clk_mgr dce gpio irq virtual + +-ifdef CONFIG_DRM_AMD_DC_DCN1_0 ++ifdef CONFIG_DRM_AMD_DC_DCN2_0 + DC_LIBS += dcn20 ++endif ++ ++ ++ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + DC_LIBS += dsc ++endif ++ ++ifdef CONFIG_DRM_AMD_DC_DCN1_0 + DC_LIBS += dcn10 dml + endif + +@@ -53,7 +60,7 @@ include $(AMD_DC) + DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ + dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o + +-ifdef CONFIG_DRM_AMD_DC_DCN1_0 ++ifdef CONFIG_DRM_AMD_DC_DCN2_0 + DISPLAY_CORE += dc_vm_helper.o + endif + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 09184adfccc8..e5cbc5bf3290 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -57,9 +57,13 @@ + #include "dc_link_dp.h" + #include "dc_dmub_srv.h" + ++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #include "dsc.h" ++#endif + ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + #include "vm_helper.h" ++#endif + + #include "dce/dce_i2c.h" + +@@ -571,8 +575,10 @@ static void dc_destruct(struct dc *dc) + dc->dcn_ip = NULL; + + #endif ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + kfree(dc->vm_helper); + dc->vm_helper = NULL; ++#endif + + } + +@@ -590,8 +596,10 @@ static bool dc_construct(struct dc *dc, + enum dce_version dc_version = DCE_VERSION_UNKNOWN; + dc->config = init_params->flags; + ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + // Allocate memory for the vm_helper + dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL); ++#endif + + memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides)); + +@@ -626,7 +634,9 @@ static bool dc_construct(struct dc *dc, + } + + dc->dcn_ip = dcn_ip; ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + dc->soc_bounding_box = init_params->soc_bounding_box; ++#endif + #endif + + dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL); +@@ -728,6 +738,7 @@ static bool dc_construct(struct dc *dc, + return false; + } + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + static bool disable_all_writeback_pipes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, +@@ -740,6 +751,7 @@ static bool disable_all_writeback_pipes_for_stream( + + return true; + } ++#endif + + static void disable_dangling_plane(struct dc *dc, struct dc_state *context) + { +@@ -765,12 +777,16 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) + } + if (should_disable && old_stream) { + dc_rem_all_planes_for_stream(dc, old_stream, dangling_context); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context); ++#endif + if (dc->hwss.apply_ctx_for_surface) + dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context); + } ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx) + dc->hwss.program_front_end_for_ctx(dc, dangling_context); ++#endif + } + + current_ctx = dc->current_state; +@@ -1160,8 +1176,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + context->stream_status[i].plane_count, + context); /* use new pipe config in new context */ + } ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx) + dc->hwss.program_front_end_for_ctx(dc, context); ++#endif + + /* Program hardware */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { +@@ -1180,8 +1198,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + } + + /* Program all planes within new context*/ ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx) + dc->hwss.program_front_end_for_ctx(dc, context); ++#endif + for (i = 0; i < context->stream_count; i++) { + const struct dc_link *link = context->streams[i]->link; + +@@ -1665,8 +1685,10 @@ static enum surface_update_type check_update_surfaces_for_stream( + if (stream_update->gamut_remap) + su_flags->bits.gamut_remap = 1; + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (stream_update->wb_update) + su_flags->bits.wb_update = 1; ++#endif + if (su_flags->raw != 0) + overall_type = UPDATE_TYPE_FULL; + +@@ -1834,6 +1856,7 @@ static void copy_surface_update_to_plane( + sizeof(struct dc_transfer_func_distributed_points)); + } + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (srf_update->func_shaper && + (surface->in_shaper_func != + srf_update->func_shaper)) +@@ -1855,6 +1878,7 @@ static void copy_surface_update_to_plane( + srf_update->blend_tf)) + memcpy(surface->blend_tf, srf_update->blend_tf, + sizeof(*surface->blend_tf)); ++#endif + + if (srf_update->input_csc_color_matrix) + surface->input_csc_color_matrix = +@@ -1932,6 +1956,7 @@ static void copy_stream_update_to_stream(struct dc *dc, + + if (update->dither_option) + stream->dither_option = *update->dither_option; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* update current stream with writeback info */ + if (update->wb_update) { + int i; +@@ -1942,6 +1967,8 @@ static void copy_stream_update_to_stream(struct dc *dc, + stream->writeback_info[i] = + update->wb_update->writeback_info[i]; + } ++#endif ++#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) + if (update->dsc_config) { + struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; + uint32_t old_dsc_enabled = stream->timing.flags.DSC; +@@ -1968,6 +1995,7 @@ static void copy_stream_update_to_stream(struct dc *dc, + update->dsc_config = NULL; + } + } ++#endif + } + + static void commit_planes_do_stream_update(struct dc *dc, +@@ -2001,6 +2029,12 @@ static void commit_planes_do_stream_update(struct dc *dc, + dc->hwss.update_info_frame(pipe_ctx); + } + ++ if (stream_update->hdr_static_metadata && ++ stream->use_dynamic_meta && ++ dc->hwss.set_dmdata_attributes && ++ pipe_ctx->stream->dmdata_address.quad_part != 0) ++ dc->hwss.set_dmdata_attributes(pipe_ctx); ++ + if (stream_update->gamut_remap) + dc_stream_set_gamut_remap(dc, stream); + +@@ -2008,25 +2042,30 @@ static void commit_planes_do_stream_update(struct dc *dc, + dc_stream_program_csc_matrix(dc, stream); + + if (stream_update->dither_option) { ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; ++#endif + resource_build_bit_depth_reduction_params(pipe_ctx->stream, + &pipe_ctx->stream->bit_depth_params); + pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + while (odm_pipe) { + odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); + odm_pipe = odm_pipe->next_odm_pipe; + } ++#endif + } +- ++#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) + if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) { + dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true); + dp_update_dsc_config(pipe_ctx); + dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false); + } ++#endif + /* Full fe update*/ + if (update_type == UPDATE_TYPE_FAST) + continue; +@@ -2113,12 +2152,14 @@ static void commit_planes_for_stream(struct dc *dc, + */ + if (dc->hwss.apply_ctx_for_surface) + dc->hwss.apply_ctx_for_surface(dc, stream, 0, context); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx) + dc->hwss.program_front_end_for_ctx(dc, context); +- ++#endif + return; + } + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { + for (i = 0; i < surface_count; i++) { + struct dc_plane_state *plane_state = srf_updates[i].surface; +@@ -2140,6 +2181,7 @@ static void commit_planes_for_stream(struct dc *dc, + } + } + } ++#endif + + // Update Type FULL, Surface updates + for (j = 0; j < dc->res_pool->pipe_count; j++) { +@@ -2160,6 +2202,7 @@ static void commit_planes_for_stream(struct dc *dc, + if (update_type == UPDATE_TYPE_FAST) + continue; + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); + + if (dc->hwss.program_triplebuffer != NULL && +@@ -2168,6 +2211,7 @@ static void commit_planes_for_stream(struct dc *dc, + dc->hwss.program_triplebuffer( + dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); + } ++#endif + stream_status = + stream_get_status(context, pipe_ctx->stream); + +@@ -2176,6 +2220,7 @@ static void commit_planes_for_stream(struct dc *dc, + dc, pipe_ctx->stream, stream_status->plane_count, context); + } + } ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) { + dc->hwss.program_front_end_for_ctx(dc, context); + #ifdef CONFIG_DRM_AMD_DC_DCN1_0 +@@ -2194,6 +2239,7 @@ static void commit_planes_for_stream(struct dc *dc, + } + #endif + } ++#endif + + // Update Type FAST, Surface updates + if (update_type == UPDATE_TYPE_FAST) { +@@ -2203,6 +2249,7 @@ static void commit_planes_for_stream(struct dc *dc, + */ + dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true); + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.set_flip_control_gsl) + for (i = 0; i < surface_count; i++) { + struct dc_plane_state *plane_state = srf_updates[i].surface; +@@ -2221,6 +2268,7 @@ static void commit_planes_for_stream(struct dc *dc, + plane_state->flip_immediate); + } + } ++#endif + /* Perform requested Updates */ + for (i = 0; i < surface_count; i++) { + struct dc_plane_state *plane_state = srf_updates[i].surface; +@@ -2233,6 +2281,7 @@ static void commit_planes_for_stream(struct dc *dc, + + if (pipe_ctx->plane_state != plane_state) + continue; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /*program triple buffer after lock based on flip type*/ + if (dc->hwss.program_triplebuffer != NULL && + !dc->debug.disable_tri_buf) { +@@ -2240,6 +2289,7 @@ static void commit_planes_for_stream(struct dc *dc, + dc->hwss.program_triplebuffer( + dc, pipe_ctx, plane_state->triplebuffer_flips); + } ++#endif + if (srf_updates[i].flip_addr) + dc->hwss.update_plane_addr(dc, pipe_ctx); + } +@@ -2405,10 +2455,12 @@ void dc_set_power_state( + + dc->hwss.init_hw(dc); + ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + if (dc->hwss.init_sys_ctx != NULL && + dc->vm_pa_config.valid) { + dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config); + } ++#endif + + break; + default: +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +index 5203159ad519..c371e553a476 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +@@ -33,7 +33,6 @@ + + #include "core_status.h" + #include "core_types.h" +-#include "hw_sequencer.h" + + #include "resource.h" + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index 67d1c8cc583b..fd9358c11222 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -161,10 +161,11 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, + res_pool = dcn10_create_resource_pool(init_data, dc); + break; + +- ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case DCN_VERSION_2_0: + res_pool = dcn20_create_resource_pool(init_data, dc); + break; ++#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + case DCN_VERSION_2_1: + res_pool = dcn21_create_resource_pool(init_data, dc); +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +index a43b4d7d5a50..8eb441388335 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +@@ -30,9 +30,6 @@ + #include "resource.h" + #include "ipp.h" + #include "timing_generator.h" +-#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +-#include "dcn10/dcn10_hw_sequencer.h" +-#endif + + #define DC_LOGGER dc->ctx->logger + +@@ -106,6 +103,7 @@ static void dc_stream_construct(struct dc_stream_state *stream, + /* EDID CAP translation for HDMI 2.0 */ + stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; + ++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); + stream->timing.dsc_cfg.num_slices_h = 0; + stream->timing.dsc_cfg.num_slices_v = 0; +@@ -114,6 +112,7 @@ static void dc_stream_construct(struct dc_stream_state *stream, + stream->timing.dsc_cfg.linebuf_depth = 9; + stream->timing.dsc_cfg.version_minor = 2; + stream->timing.dsc_cfg.ycbcr422_simple = 0; ++#endif + + update_stream_signal(stream, dc_sink_data); + +@@ -363,6 +362,7 @@ bool dc_stream_set_cursor_position( + return true; + } + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool dc_stream_add_writeback(struct dc *dc, + struct dc_stream_state *stream, + struct dc_writeback_info *wb_info) +@@ -475,6 +475,7 @@ bool dc_stream_remove_writeback(struct dc *dc, + + return true; + } ++#endif + + uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) + { +@@ -561,6 +562,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, + return ret; + } + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) + { + struct pipe_ctx *pipe = NULL; +@@ -621,6 +623,7 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, + + return true; + } ++#endif + + void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) + { +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +index 0275d6d60da4..e1c5839a80dc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +@@ -25,7 +25,7 @@ + + #include "dce_hwseq.h" + #include "reg_helper.h" +-#include "hw_sequencer.h" ++#include "hw_sequencer_private.h" + #include "core_types.h" + + #define CTX \ +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index 7e3dde764111..a3491fab05f6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -25,7 +25,7 @@ + #ifndef __DCE_HWSEQ_H__ + #define __DCE_HWSEQ_H__ + +-#include "hw_sequencer.h" ++#include "dc_types.h" + + #define BL_REG_LIST()\ + SR(LVTMA_PWRSEQ_CNTL), \ +@@ -815,6 +815,10 @@ enum blnd_mode { + BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ + }; + ++struct dce_hwseq; ++struct pipe_ctx; ++struct clock_source; ++ + void dce_enable_fe_clock(struct dce_hwseq *hwss, + unsigned int inst, bool enable); + +diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +index 799d36299c9b..753cb8edd996 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +@@ -26,7 +26,6 @@ + #include "dc.h" + #include "core_types.h" + #include "clk_mgr.h" +-#include "hw_sequencer.h" + #include "dce100_hw_sequencer.h" + #include "resource.h" + +@@ -136,7 +135,7 @@ void dce100_hw_sequencer_construct(struct dc *dc) + { + dce110_hw_sequencer_construct(dc); + +- dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; ++ dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating; + dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; + dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +index a6b80fdaa666..34518da20009 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +@@ -27,6 +27,7 @@ + #define __DC_HWSS_DCE100_H__ + + #include "core_types.h" ++#include "hw_sequencer_private.h" + + struct dc; + struct dc_state; +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index ad53e6727df2..f95c122c197b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -650,10 +650,9 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) + { + enum dc_lane_count lane_count = + pipe_ctx->stream->link->cur_link_settings.lane_count; +- + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; + struct dc_link *link = pipe_ctx->stream->link; +- ++ const struct dc *dc = link->dc; + + uint32_t active_total_with_borders; + uint32_t early_control = 0; +@@ -666,7 +665,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) + link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, + pipe_ctx->stream_res.stream_enc->id, true); + +- link->dc->hwss.update_info_frame(pipe_ctx); ++ dc->hwss.update_info_frame(pipe_ctx); + + /* enable early control to avoid corruption on DP monitor*/ + active_total_with_borders = +@@ -1046,6 +1045,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + struct encoder_unblank_param params = { { 0 } }; + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; ++ struct dce_hwseq *hws = link->dc->hwseq; + + /* only 3 items below are used by unblank */ + params.timing = pipe_ctx->stream->timing; +@@ -1055,7 +1055,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); + + if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { +- link->dc->hwss.edp_backlight_control(link, true); ++ hws->funcs.edp_backlight_control(link, true); + } + } + +@@ -1063,9 +1063,10 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx) + { + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; ++ struct dce_hwseq *hws = link->dc->hwseq; + + if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { +- link->dc->hwss.edp_backlight_control(link, false); ++ hws->funcs.edp_backlight_control(link, false); + dc_link_set_abm_disable(link); + } + +@@ -1321,10 +1322,13 @@ static enum dc_status apply_single_controller_ctx_to_hw( + struct dc_stream_state *stream = pipe_ctx->stream; + struct drr_params params = {0}; + unsigned int event_triggers = 0; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; ++#endif ++ struct dce_hwseq *hws = dc->hwseq; + +- if (dc->hwss.disable_stream_gating) { +- dc->hwss.disable_stream_gating(dc, pipe_ctx); ++ if (hws->funcs.disable_stream_gating) { ++ hws->funcs.disable_stream_gating(dc, pipe_ctx); + } + + if (pipe_ctx->stream_res.audio != NULL) { +@@ -1354,10 +1358,10 @@ static enum dc_status apply_single_controller_ctx_to_hw( + /* */ + /* Do not touch stream timing on seamless boot optimization. */ + if (!pipe_ctx->stream->apply_seamless_boot_optimization) +- dc->hwss.enable_stream_timing(pipe_ctx, context, dc); ++ hws->funcs.enable_stream_timing(pipe_ctx, context, dc); + +- if (dc->hwss.setup_vupdate_interrupt) +- dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx); ++ if (hws->funcs.setup_vupdate_interrupt) ++ hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); + + params.vertical_total_min = stream->adjust.v_total_min; + params.vertical_total_max = stream->adjust.v_total_max; +@@ -1387,6 +1391,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( + pipe_ctx->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + while (odm_pipe) { + odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( + odm_pipe->stream_res.opp, +@@ -1400,6 +1405,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( + &stream->clamping); + odm_pipe = odm_pipe->next_odm_pipe; + } ++#endif + + if (!stream->dpms_off) + core_link_enable_stream(context, pipe_ctx); +@@ -1550,9 +1556,10 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) + bool can_apply_edp_fast_boot = false; + bool can_apply_seamless_boot = false; + bool keep_edp_vdd_on = false; ++ struct dce_hwseq *hws = dc->hwseq; + +- if (dc->hwss.init_pipes) +- dc->hwss.init_pipes(dc, context); ++ if (hws->funcs.init_pipes) ++ hws->funcs.init_pipes(dc, context); + + edp_stream = get_edp_stream(context); + +@@ -1589,7 +1596,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) + if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { + if (edp_link_with_sink && !keep_edp_vdd_on) { + /*turn off backlight before DP_blank and encoder powered down*/ +- dc->hwss.edp_backlight_control(edp_link_with_sink, false); ++ hws->funcs.edp_backlight_control(edp_link_with_sink, false); + } + /*resume from S3, no vbios posting, no need to power down again*/ + power_down_all_hw_blocks(dc); +@@ -2004,13 +2011,14 @@ enum dc_status dce110_apply_ctx_to_hw( + struct dc *dc, + struct dc_state *context) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct dc_bios *dcb = dc->ctx->dc_bios; + enum dc_status status; + int i; + + /* Reset old context */ + /* look up the targets that have been removed since last commit */ +- dc->hwss.reset_hw_ctx_wrap(dc, context); ++ hws->funcs.reset_hw_ctx_wrap(dc, context); + + /* Skip applying if no targets */ + if (context->stream_count <= 0) +@@ -2035,7 +2043,7 @@ enum dc_status dce110_apply_ctx_to_hw( + continue; + } + +- dc->hwss.enable_display_power_gating( ++ hws->funcs.enable_display_power_gating( + dc, i, dc->ctx->dc_bios, + PIPE_GATING_CONTROL_DISABLE); + } +@@ -2344,19 +2352,20 @@ static void init_hw(struct dc *dc) + struct transform *xfm; + struct abm *abm; + struct dmcu *dmcu; ++ struct dce_hwseq *hws = dc->hwseq; + + bp = dc->ctx->dc_bios; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + xfm = dc->res_pool->transforms[i]; + xfm->funcs->transform_reset(xfm); + +- dc->hwss.enable_display_power_gating( ++ hws->funcs.enable_display_power_gating( + dc, i, bp, + PIPE_GATING_CONTROL_INIT); +- dc->hwss.enable_display_power_gating( ++ hws->funcs.enable_display_power_gating( + dc, i, bp, + PIPE_GATING_CONTROL_DISABLE); +- dc->hwss.enable_display_pipe_clock_gating( ++ hws->funcs.enable_display_pipe_clock_gating( + dc->ctx, + true); + } +@@ -2442,6 +2451,8 @@ static void dce110_program_front_end_for_pipe( + struct xfm_grph_csc_adjustment adjust; + struct out_csc_color_matrix tbl_entry; + unsigned int i; ++ struct dce_hwseq *hws = dc->hwseq; ++ + DC_LOGGER_INIT(); + memset(&tbl_entry, 0, sizeof(tbl_entry)); + +@@ -2500,10 +2511,10 @@ static void dce110_program_front_end_for_pipe( + if (pipe_ctx->plane_state->update_flags.bits.full_update || + pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || + pipe_ctx->plane_state->update_flags.bits.gamma_change) +- dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); ++ hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); + + if (pipe_ctx->plane_state->update_flags.bits.full_update) +- dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); ++ hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); + + DC_LOG_SURFACE( + "Pipe:%d %p: addr hi:0x%x, " +@@ -2606,6 +2617,7 @@ static void dce110_apply_ctx_for_surface( + + static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) + { ++ struct dce_hwseq *hws = dc->hwseq; + int fe_idx = pipe_ctx->plane_res.mi ? + pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; + +@@ -2613,7 +2625,7 @@ static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) + if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) + return; + +- dc->hwss.enable_display_power_gating( ++ hws->funcs.enable_display_power_gating( + dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); + + dc->res_pool->transforms[fe_idx]->funcs->transform_reset( +@@ -2702,14 +2714,10 @@ static const struct hw_sequencer_funcs dce110_funcs = { + .program_gamut_remap = program_gamut_remap, + .program_output_csc = program_output_csc, + .init_hw = init_hw, +- .init_pipes = init_pipes, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .apply_ctx_for_surface = dce110_apply_ctx_for_surface, + .update_plane_addr = update_plane_addr, + .update_pending_status = dce110_update_pending_status, +- .set_input_transfer_func = dce110_set_input_transfer_func, +- .set_output_transfer_func = dce110_set_output_transfer_func, +- .power_down = dce110_power_down, + .enable_accelerated_mode = dce110_enable_accelerated_mode, + .enable_timing_synchronization = dce110_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, +@@ -2720,8 +2728,6 @@ static const struct hw_sequencer_funcs dce110_funcs = { + .blank_stream = dce110_blank_stream, + .enable_audio_stream = dce110_enable_audio_stream, + .disable_audio_stream = dce110_disable_audio_stream, +- .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, +- .enable_display_power_gating = dce110_enable_display_power_gating, + .disable_plane = dce110_power_down_fe, + .pipe_control_lock = dce_pipe_control_lock, + .prepare_bandwidth = dce110_prepare_bandwidth, +@@ -2729,22 +2735,33 @@ static const struct hw_sequencer_funcs dce110_funcs = { + .set_drr = set_drr, + .get_position = get_position, + .set_static_screen_control = set_static_screen_control, +- .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, +- .enable_stream_timing = dce110_enable_stream_timing, +- .disable_stream_gating = NULL, +- .enable_stream_gating = NULL, + .setup_stereo = NULL, + .set_avmute = dce110_set_avmute, + .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, +- .edp_backlight_control = dce110_edp_backlight_control, + .edp_power_control = dce110_edp_power_control, + .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, + .set_cursor_position = dce110_set_cursor_position, + .set_cursor_attribute = dce110_set_cursor_attribute + }; + ++static const struct hwseq_private_funcs dce110_private_funcs = { ++ .init_pipes = init_pipes, ++ .update_plane_addr = update_plane_addr, ++ .set_input_transfer_func = dce110_set_input_transfer_func, ++ .set_output_transfer_func = dce110_set_output_transfer_func, ++ .power_down = dce110_power_down, ++ .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, ++ .enable_display_power_gating = dce110_enable_display_power_gating, ++ .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, ++ .enable_stream_timing = dce110_enable_stream_timing, ++ .disable_stream_gating = NULL, ++ .enable_stream_gating = NULL, ++ .edp_backlight_control = dce110_edp_backlight_control, ++}; ++ + void dce110_hw_sequencer_construct(struct dc *dc) + { + dc->hwss = dce110_funcs; ++ dc->hwseq->funcs = dce110_private_funcs; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +index c639e1680b7b..26a9c14a58b1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +@@ -27,6 +27,7 @@ + #define __DC_HWSS_DCE110_H__ + + #include "core_types.h" ++#include "hw_sequencer_private.h" + + struct dc; + struct dc_state; +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +index 762f97b48f0f..75ffea78c6cc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +@@ -1095,6 +1095,7 @@ static struct pipe_ctx *dce110_acquire_underlay( + struct dc_stream_state *stream) + { + struct dc *dc = stream->ctx->dc; ++ struct dce_hwseq *hws = dc->hwseq; + struct resource_context *res_ctx = &context->res_ctx; + unsigned int underlay_idx = pool->underlay_pipe_index; + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; +@@ -1115,7 +1116,7 @@ static struct pipe_ctx *dce110_acquire_underlay( + struct tg_color black_color = {0}; + struct dc_bios *dcb = dc->ctx->dc_bios; + +- dc->hwss.enable_display_power_gating( ++ hws->funcs.enable_display_power_gating( + dc, + pipe_ctx->stream_res.tg->inst, + dcb, PIPE_GATING_CONTROL_DISABLE); +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c +index 1e4a7c13f0ed..19873ee1f78d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c +@@ -158,6 +158,6 @@ void dce112_hw_sequencer_construct(struct dc *dc) + * structure + */ + dce110_hw_sequencer_construct(dc); +- dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating; ++ dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h +index e646f4a37fa2..943f1b2c5b2f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h +@@ -27,6 +27,7 @@ + #define __DC_HWSS_DCE112_H__ + + #include "core_types.h" ++#include "hw_sequencer_private.h" + + struct dc; + +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +index 1ca30928025e..66a13aa39c95 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +@@ -265,7 +265,7 @@ void dce120_hw_sequencer_construct(struct dc *dc) + * structure + */ + dce110_hw_sequencer_construct(dc); +- dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating; ++ dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating; + dc->hwss.update_dchub = dce120_update_dchub; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h +index c51afbd0b012..bc024534732f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h +@@ -27,6 +27,7 @@ + #define __DC_HWSS_DCE120_H__ + + #include "core_types.h" ++#include "hw_sequencer_private.h" + + struct dc; + +diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +index c4543178ba20..893261c81854 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +@@ -74,7 +74,7 @@ void dce80_hw_sequencer_construct(struct dc *dc) + { + dce110_hw_sequencer_construct(dc); + +- dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; ++ dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating; + dc->hwss.pipe_control_lock = dce_pipe_control_lock; + dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; + dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; +diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h +index 7a1b31def66f..e43af832d00c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h +@@ -27,6 +27,7 @@ + #define __DC_HWSS_DCE80_H__ + + #include "core_types.h" ++#include "hw_sequencer_private.h" + + struct dc; + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 1ed26ac33551..528a6a953be4 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -641,8 +641,8 @@ static void power_on_plane( + if (REG(DC_IP_REQUEST_CNTL)) { + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); +- hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true); +- hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true); ++ hws->funcs.dpp_pg_control(hws, plane_id, true); ++ hws->funcs.hubp_pg_control(hws, plane_id, true); + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); + DC_LOG_DEBUG( +@@ -663,7 +663,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); + +- dc->hwss.hubp_pg_control(hws, 0, false); ++ hws->funcs.hubp_pg_control(hws, 0, false); + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); + +@@ -692,7 +692,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); + +- dc->hwss.hubp_pg_control(hws, 0, true); ++ hws->funcs.hubp_pg_control(hws, 0, true); + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); + +@@ -702,14 +702,16 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) + + void dcn10_bios_golden_init(struct dc *dc) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct dc_bios *bp = dc->ctx->dc_bios; + int i; + bool allow_self_fresh_force_enable = true; + + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) +- if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc)) ++ if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc)) + return; + #endif ++ + if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) + allow_self_fresh_force_enable = + dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub); +@@ -1016,6 +1018,7 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc) + /* trigger HW to start disconnect plane from stream on the next vsync */ + void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + int dpp_id = pipe_ctx->plane_res.dpp->inst; + struct mpc *mpc = dc->res_pool->mpc; +@@ -1040,7 +1043,7 @@ void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) + hubp->funcs->hubp_disconnect(hubp); + + if (dc->debug.sanity_checks) +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + } + + void dcn10_plane_atomic_power_down(struct dc *dc, +@@ -1053,8 +1056,8 @@ void dcn10_plane_atomic_power_down(struct dc *dc, + if (REG(DC_IP_REQUEST_CNTL)) { + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); +- dc->hwss.dpp_pg_control(hws, dpp->inst, false); +- dc->hwss.hubp_pg_control(hws, hubp->inst, false); ++ hws->funcs.dpp_pg_control(hws, dpp->inst, false); ++ hws->funcs.hubp_pg_control(hws, hubp->inst, false); + dpp->funcs->dpp_reset(dpp); + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); +@@ -1068,6 +1071,7 @@ void dcn10_plane_atomic_power_down(struct dc *dc, + */ + void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + int opp_id = hubp->opp_id; +@@ -1086,7 +1090,7 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) + hubp->power_gated = true; + dc->optimized_required = false; /* We're powering off, no need to optimize */ + +- dc->hwss.plane_atomic_power_down(dc, ++ hws->funcs.plane_atomic_power_down(dc, + pipe_ctx->plane_res.dpp, + pipe_ctx->plane_res.hubp); + +@@ -1100,12 +1104,13 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) + + void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) + { ++ struct dce_hwseq *hws = dc->hwseq; + DC_LOGGER_INIT(dc->ctx->logger); + + if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) + return; + +- dc->hwss.plane_atomic_disable(dc, pipe_ctx); ++ hws->funcs.plane_atomic_disable(dc, pipe_ctx); + + apply_DEGVIDCN10_253_wa(dc); + +@@ -1116,6 +1121,7 @@ void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) + void dcn10_init_pipes(struct dc *dc, struct dc_state *context) + { + int i; ++ struct dce_hwseq *hws = dc->hwseq; + bool can_apply_seamless_boot = false; + + for (i = 0; i < context->stream_count; i++) { +@@ -1140,8 +1146,8 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context) + * command table. + */ + if (tg->funcs->is_tg_enabled(tg)) { +- if (dc->hwss.init_blank != NULL) { +- dc->hwss.init_blank(dc, tg); ++ if (hws->funcs.init_blank != NULL) { ++ hws->funcs.init_blank(dc, tg); + tg->funcs->lock(tg); + } else { + tg->funcs->lock(tg); +@@ -1198,7 +1204,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context) + dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; + pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; + +- dc->hwss.plane_atomic_disconnect(dc, pipe_ctx); ++ hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); + + if (tg->funcs->is_tg_enabled(tg)) + tg->funcs->unlock(tg); +@@ -1244,15 +1250,15 @@ void dcn10_init_hw(struct dc *dc) + } + + //Enable ability to power gate / don't force power on permanently +- dc->hwss.enable_power_gating_plane(hws, true); ++ hws->funcs.enable_power_gating_plane(hws, true); + + return; + } + + if (!dcb->funcs->is_accelerated_mode(dcb)) +- dc->hwss.disable_vga(dc->hwseq); ++ hws->funcs.disable_vga(dc->hwseq); + +- dc->hwss.bios_golden_init(dc); ++ hws->funcs.bios_golden_init(dc); + if (dc->ctx->dc_bios->fw_info_valid) { + res_pool->ref_clocks.xtalin_clock_inKhz = + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; +@@ -1293,10 +1299,12 @@ void dcn10_init_hw(struct dc *dc) + link->link_status.link_active = true; + } + ++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* Power gate DSCs */ + for (i = 0; i < res_pool->res_cap->num_dsc; i++) +- if (dc->hwss.dsc_pg_control != NULL) +- dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); ++ if (hws->funcs.dsc_pg_control != NULL) ++ hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); ++#endif + + /* If taking control over from VBIOS, we may want to optimize our first + * mode set, so we need to skip powering down pipes until we know which +@@ -1305,7 +1313,7 @@ void dcn10_init_hw(struct dc *dc) + * everything down. + */ + if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { +- dc->hwss.init_pipes(dc, dc->current_state); ++ hws->funcs.init_pipes(dc, dc->current_state); + } + + for (i = 0; i < res_pool->audio_count; i++) { +@@ -1337,7 +1345,7 @@ void dcn10_init_hw(struct dc *dc) + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + } + +- dc->hwss.enable_power_gating_plane(dc->hwseq, true); ++ hws->funcs.enable_power_gating_plane(dc->hwseq, true); + + if (dc->clk_mgr->funcs->notify_wm_ranges) + dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); +@@ -1349,6 +1357,7 @@ void dcn10_reset_hw_ctx_wrap( + struct dc_state *context) + { + int i; ++ struct dce_hwseq *hws = dc->hwseq; + + /* Reset Back End*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { +@@ -1367,8 +1376,8 @@ void dcn10_reset_hw_ctx_wrap( + struct clock_source *old_clk = pipe_ctx_old->clock_source; + + dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); +- if (dc->hwss.enable_stream_gating) +- dc->hwss.enable_stream_gating(dc, pipe_ctx); ++ if (hws->funcs.enable_stream_gating) ++ hws->funcs.enable_stream_gating(dc, pipe_ctx); + if (old_clk) + old_clk->funcs->cs_power_down(old_clk); + } +@@ -1545,6 +1554,8 @@ void dcn10_pipe_control_lock( + struct pipe_ctx *pipe, + bool lock) + { ++ struct dce_hwseq *hws = dc->hwseq; ++ + /* use TG master update lock to lock everything on the TG + * therefore only top pipe need to lock + */ +@@ -1552,7 +1563,7 @@ void dcn10_pipe_control_lock( + return; + + if (dc->debug.sanity_checks) +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + + if (lock) + pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); +@@ -1560,7 +1571,7 @@ void dcn10_pipe_control_lock( + pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); + + if (dc->debug.sanity_checks) +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + } + + static bool wait_for_reset_trigger_to_occur( +@@ -1868,7 +1879,7 @@ static void dcn10_enable_plane( + struct dce_hwseq *hws = dc->hwseq; + + if (dc->debug.sanity_checks) { +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + } + + undo_DEGVIDCN10_253_wa(dc); +@@ -1925,7 +1936,7 @@ static void dcn10_enable_plane( + dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp); + + if (dc->debug.sanity_checks) { +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + } + } + +@@ -2102,6 +2113,7 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state + + void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct mpcc_blnd_cfg blnd_cfg = {{0}}; + bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; +@@ -2111,10 +2123,10 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) + struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); + + if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { +- dc->hwss.get_hdr_visual_confirm_color( ++ hws->funcs.get_hdr_visual_confirm_color( + pipe_ctx, &blnd_cfg.black_color); + } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { +- dc->hwss.get_surface_visual_confirm_color( ++ hws->funcs.get_surface_visual_confirm_color( + pipe_ctx, &blnd_cfg.black_color); + } else { + color_space_to_black_color( +@@ -2201,6 +2213,7 @@ static void dcn10_update_dchubp_dpp( + struct pipe_ctx *pipe_ctx, + struct dc_state *context) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; +@@ -2259,7 +2272,7 @@ static void dcn10_update_dchubp_dpp( + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.per_pixel_alpha_change || + plane_state->update_flags.bits.global_alpha_change) +- dc->hwss.update_mpcc(dc, pipe_ctx); ++ hws->funcs.update_mpcc(dc, pipe_ctx); + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.per_pixel_alpha_change || +@@ -2319,7 +2332,7 @@ static void dcn10_update_dchubp_dpp( + + hubp->power_gated = false; + +- dc->hwss.update_plane_addr(dc, pipe_ctx); ++ hws->funcs.update_plane_addr(dc, pipe_ctx); + + if (is_pipe_tree_visible(pipe_ctx)) + hubp->funcs->set_blank(hubp, false); +@@ -2395,17 +2408,19 @@ void dcn10_program_pipe( + struct pipe_ctx *pipe_ctx, + struct dc_state *context) + { ++ struct dce_hwseq *hws = dc->hwseq; ++ + if (pipe_ctx->plane_state->update_flags.bits.full_update) + dcn10_enable_plane(dc, pipe_ctx, context); + + dcn10_update_dchubp_dpp(dc, pipe_ctx, context); + +- dc->hwss.set_hdr_multiplier(pipe_ctx); ++ hws->funcs.set_hdr_multiplier(pipe_ctx); + + if (pipe_ctx->plane_state->update_flags.bits.full_update || + pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || + pipe_ctx->plane_state->update_flags.bits.gamma_change) +- dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); ++ hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); + + /* dcn10_translate_regamma_to_hw_format takes 750us to finish + * only do gamma programming for full update. +@@ -2414,7 +2429,7 @@ void dcn10_program_pipe( + * doing heavy calculation and programming + */ + if (pipe_ctx->plane_state->update_flags.bits.full_update) +- dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); ++ hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); + } + + static void dcn10_program_all_pipe_in_tree( +@@ -2422,6 +2437,8 @@ static void dcn10_program_all_pipe_in_tree( + struct pipe_ctx *pipe_ctx, + struct dc_state *context) + { ++ struct dce_hwseq *hws = dc->hwseq; ++ + if (pipe_ctx->top_pipe == NULL) { + bool blank = !is_pipe_tree_visible(pipe_ctx); + +@@ -2435,14 +2452,14 @@ static void dcn10_program_all_pipe_in_tree( + pipe_ctx->stream_res.tg->funcs->set_vtg_params( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + +- if (dc->hwss.setup_vupdate_interrupt) +- dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx); ++ if (hws->funcs.setup_vupdate_interrupt) ++ hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); + +- dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); ++ hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); + } + + if (pipe_ctx->plane_state != NULL) +- dc->hwss.program_pipe(dc, pipe_ctx, context); ++ hws->funcs.program_pipe(dc, pipe_ctx, context); + + if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) + dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); +@@ -2478,6 +2495,7 @@ void dcn10_apply_ctx_for_surface( + int num_planes, + struct dc_state *context) + { ++ struct dce_hwseq *hws = dc->hwseq; + int i; + struct timing_generator *tg; + uint32_t underflow_check_delay_us; +@@ -2497,8 +2515,8 @@ void dcn10_apply_ctx_for_surface( + + underflow_check_delay_us = dc->debug.underflow_assert_delay_us; + +- if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur) +- ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program)); ++ if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur) ++ ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program)); + + if (interdependent_update) + dcn10_lock_all_pipes(dc, context, true); +@@ -2508,12 +2526,12 @@ void dcn10_apply_ctx_for_surface( + if (underflow_check_delay_us != 0xFFFFFFFF) + udelay(underflow_check_delay_us); + +- if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur) +- ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program)); ++ if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur) ++ ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program)); + + if (num_planes == 0) { + /* OTG blank before remove all front end */ +- dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true); ++ hws->funcs.blank_pixel_data(dc, top_pipe_to_program, true); + } + + /* Disconnect unused mpcc */ +@@ -2539,7 +2557,7 @@ void dcn10_apply_ctx_for_surface( + old_pipe_ctx->plane_state && + old_pipe_ctx->stream_res.tg == tg) { + +- dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx); ++ hws->funcs.plane_atomic_disconnect(dc, old_pipe_ctx); + removed_pipe[i] = true; + + DC_LOG_DC("Reset mpcc for pipe %d\n", +@@ -2550,9 +2568,11 @@ void dcn10_apply_ctx_for_surface( + if (num_planes > 0) + dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context); + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* Program secondary blending tree and writeback pipes */ +- if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree)) +- dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context); ++ if ((stream->num_wb_info > 0) && (hws->funcs.program_all_writeback_pipes_in_tree)) ++ hws->funcs.program_all_writeback_pipes_in_tree(dc, stream, context); ++#endif + if (interdependent_update) + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; +@@ -2609,10 +2629,11 @@ void dcn10_prepare_bandwidth( + struct dc *dc, + struct dc_state *context) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct hubbub *hubbub = dc->res_pool->hubbub; + + if (dc->debug.sanity_checks) +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + if (context->stream_count == 0) +@@ -2634,17 +2655,18 @@ void dcn10_prepare_bandwidth( + dcn_bw_notify_pplib_of_wm_ranges(dc); + + if (dc->debug.sanity_checks) +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + } + + void dcn10_optimize_bandwidth( + struct dc *dc, + struct dc_state *context) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct hubbub *hubbub = dc->res_pool->hubbub; + + if (dc->debug.sanity_checks) +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + if (context->stream_count == 0) +@@ -2666,7 +2688,7 @@ void dcn10_optimize_bandwidth( + dcn_bw_notify_pplib_of_wm_ranges(dc); + + if (dc->debug.sanity_checks) +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + } + + void dcn10_set_drr(struct pipe_ctx **pipe_ctx, +@@ -2808,10 +2830,11 @@ void dcn10_wait_for_mpcc_disconnect( + struct resource_pool *res_pool, + struct pipe_ctx *pipe_ctx) + { ++ struct dce_hwseq *hws = dc->hwseq; + int mpcc_inst; + + if (dc->debug.sanity_checks) { +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + } + + if (!pipe_ctx->stream_res.opp) +@@ -2828,7 +2851,7 @@ void dcn10_wait_for_mpcc_disconnect( + } + + if (dc->debug.sanity_checks) { +- dc->hwss.verify_allow_pstate_change_high(dc); ++ hws->funcs.verify_allow_pstate_change_high(dc); + } + + } +@@ -3127,6 +3150,7 @@ void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx, + struct encoder_unblank_param params = { { 0 } }; + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; ++ struct dce_hwseq *hws = link->dc->hwseq; + + /* only 3 items below are used by unblank */ + params.timing = pipe_ctx->stream->timing; +@@ -3140,7 +3164,7 @@ void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx, + } + + if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { +- link->dc->hwss.edp_backlight_control(link, true); ++ hws->funcs.edp_backlight_control(link, true); + } + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +index 5aad3922be6c..55b8f3b2fc4e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +@@ -27,6 +27,7 @@ + #define __DC_HWSS_DCN10_H__ + + #include "core_types.h" ++#include "hw_sequencer_private.h" + + struct dc; + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c +index 38923f3120ee..e7e5352ec424 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c +@@ -23,25 +23,19 @@ + * + */ + ++#include "hw_sequencer_private.h" + #include "dce110/dce110_hw_sequencer.h" + #include "dcn10_hw_sequencer.h" + + static const struct hw_sequencer_funcs dcn10_funcs = { + .program_gamut_remap = dcn10_program_gamut_remap, + .init_hw = dcn10_init_hw, +- .init_pipes = dcn10_init_pipes, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .apply_ctx_for_surface = dcn10_apply_ctx_for_surface, + .update_plane_addr = dcn10_update_plane_addr, +- .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, +- .program_pipe = dcn10_program_pipe, + .update_dchub = dcn10_update_dchub, +- .update_mpcc = dcn10_update_mpcc, + .update_pending_status = dcn10_update_pending_status, +- .set_input_transfer_func = dcn10_set_input_transfer_func, +- .set_output_transfer_func = dcn10_set_output_transfer_func, + .program_output_csc = dcn10_program_output_csc, +- .power_down = dce110_power_down, + .enable_accelerated_mode = dce110_enable_accelerated_mode, + .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, +@@ -53,14 +47,10 @@ static const struct hw_sequencer_funcs dcn10_funcs = { + .blank_stream = dce110_blank_stream, + .enable_audio_stream = dce110_enable_audio_stream, + .disable_audio_stream = dce110_disable_audio_stream, +- .enable_display_power_gating = dcn10_dummy_display_power_gating, + .disable_plane = dcn10_disable_plane, +- .blank_pixel_data = dcn10_blank_pixel_data, + .pipe_control_lock = dcn10_pipe_control_lock, + .prepare_bandwidth = dcn10_prepare_bandwidth, + .optimize_bandwidth = dcn10_optimize_bandwidth, +- .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap, +- .enable_stream_timing = dcn10_enable_stream_timing, + .set_drr = dcn10_set_drr, + .get_position = dcn10_get_position, + .set_static_screen_control = dcn10_set_static_screen_control, +@@ -70,18 +60,34 @@ static const struct hw_sequencer_funcs dcn10_funcs = { + .get_hw_state = dcn10_get_hw_state, + .clear_status_bits = dcn10_clear_status_bits, + .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, +- .edp_backlight_control = dce110_edp_backlight_control, + .edp_power_control = dce110_edp_power_control, + .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, + .set_cursor_position = dcn10_set_cursor_position, + .set_cursor_attribute = dcn10_set_cursor_attribute, + .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, +- .disable_stream_gating = NULL, +- .enable_stream_gating = NULL, + .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, +- .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt, + .set_clock = dcn10_set_clock, + .get_clock = dcn10_get_clock, ++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, ++}; ++ ++static const struct hwseq_private_funcs dcn10_private_funcs = { ++ .init_pipes = dcn10_init_pipes, ++ .update_plane_addr = dcn10_update_plane_addr, ++ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, ++ .program_pipe = dcn10_program_pipe, ++ .update_mpcc = dcn10_update_mpcc, ++ .set_input_transfer_func = dcn10_set_input_transfer_func, ++ .set_output_transfer_func = dcn10_set_output_transfer_func, ++ .power_down = dce110_power_down, ++ .enable_display_power_gating = dcn10_dummy_display_power_gating, ++ .blank_pixel_data = dcn10_blank_pixel_data, ++ .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap, ++ .enable_stream_timing = dcn10_enable_stream_timing, ++ .edp_backlight_control = dce110_edp_backlight_control, ++ .disable_stream_gating = NULL, ++ .enable_stream_gating = NULL, ++ .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt, + .did_underflow_occur = dcn10_did_underflow_occur, + .init_blank = NULL, + .disable_vga = dcn10_disable_vga, +@@ -96,10 +102,10 @@ static const struct hw_sequencer_funcs dcn10_funcs = { + .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color, + .set_hdr_multiplier = dcn10_set_hdr_multiplier, + .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, +- .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, + }; + + void dcn10_hw_sequencer_construct(struct dc *dc) + { + dc->hwss = dcn10_funcs; ++ dc->hwseq->funcs = dcn10_private_funcs; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index 937ecb28948d..d99e882bd555 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -276,6 +276,7 @@ void dcn20_init_blank( + struct dc *dc, + struct timing_generator *tg) + { ++ struct dce_hwseq *hws = dc->hwseq; + enum dc_color_space color_space; + struct tg_color black_color = {0}; + struct output_pixel_processor *opp = NULL; +@@ -323,7 +324,7 @@ void dcn20_init_blank( + otg_active_height); + } + +- dc->hwss.wait_for_blank_complete(opp); ++ hws->funcs.wait_for_blank_complete(opp); + } + + void dcn20_dsc_pg_control( +@@ -556,6 +557,7 @@ void dcn20_hubp_pg_control( + */ + void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + +@@ -576,7 +578,7 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) + hubp->power_gated = true; + dc->optimized_required = false; /* We're powering off, no need to optimize */ + +- dc->hwss.plane_atomic_power_down(dc, ++ hws->funcs.plane_atomic_power_down(dc, + pipe_ctx->plane_res.dpp, + pipe_ctx->plane_res.hubp); + +@@ -607,6 +609,7 @@ enum dc_status dcn20_enable_stream_timing( + struct dc_state *context, + struct dc *dc) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct dc_stream_state *stream = pipe_ctx->stream; + struct drr_params params = {0}; + unsigned int event_triggers = 0; +@@ -666,7 +669,7 @@ enum dc_status dcn20_enable_stream_timing( + pipe_ctx->stream_res.opp, + true); + +- dc->hwss.blank_pixel_data(dc, pipe_ctx, true); ++ hws->funcs.blank_pixel_data(dc, pipe_ctx, true); + + /* VTG is within DCHUB command block. DCFCLK is always on */ + if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { +@@ -674,7 +677,7 @@ enum dc_status dcn20_enable_stream_timing( + return DC_ERROR_UNEXPECTED; + } + +- dc->hwss.wait_for_blank_complete(pipe_ctx->stream_res.opp); ++ hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); + + params.vertical_total_min = stream->adjust.v_total_min; + params.vertical_total_max = stream->adjust.v_total_max; +@@ -824,6 +827,7 @@ bool dcn20_set_input_transfer_func(struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + const struct dc_transfer_func *tf = NULL; + bool result = true; +@@ -832,8 +836,8 @@ bool dcn20_set_input_transfer_func(struct dc *dc, + if (dpp_base == NULL || plane_state == NULL) + return false; + +- dc->hwss.set_shaper_3dlut(pipe_ctx, plane_state); +- dc->hwss.set_blend_lut(pipe_ctx, plane_state); ++ hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); ++ hws->funcs.set_blend_lut(pipe_ctx, plane_state); + + if (plane_state->in_transfer_func) + tf = plane_state->in_transfer_func; +@@ -1296,6 +1300,7 @@ static void dcn20_update_dchubp_dpp( + struct pipe_ctx *pipe_ctx, + struct dc_state *context) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; +@@ -1360,7 +1365,7 @@ static void dcn20_update_dchubp_dpp( + old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; + } + } +- dc->hwss.update_mpcc(dc, pipe_ctx); ++ hws->funcs.update_mpcc(dc, pipe_ctx); + } + + if (pipe_ctx->update_flags.bits.scaler || +@@ -1435,7 +1440,7 @@ static void dcn20_update_dchubp_dpp( + } + + if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update) +- dc->hwss.update_plane_addr(dc, pipe_ctx); ++ hws->funcs.update_plane_addr(dc, pipe_ctx); + + if (pipe_ctx->update_flags.bits.enable) + hubp->funcs->set_blank(hubp, false); +@@ -1447,10 +1452,11 @@ static void dcn20_program_pipe( + struct pipe_ctx *pipe_ctx, + struct dc_state *context) + { ++ struct dce_hwseq *hws = dc->hwseq; + /* Only need to unblank on top pipe */ + if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) + && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) +- dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); ++ hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); + + if (pipe_ctx->update_flags.bits.global_sync) { + pipe_ctx->stream_res.tg->funcs->program_global_sync( +@@ -1463,12 +1469,12 @@ static void dcn20_program_pipe( + pipe_ctx->stream_res.tg->funcs->set_vtg_params( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + +- if (dc->hwss.setup_vupdate_interrupt) +- dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx); ++ if (hws->funcs.setup_vupdate_interrupt) ++ hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); + } + + if (pipe_ctx->update_flags.bits.odm) +- dc->hwss.update_odm(dc, context, pipe_ctx); ++ hws->funcs.update_odm(dc, context, pipe_ctx); + + if (pipe_ctx->update_flags.bits.enable) + dcn20_enable_plane(dc, pipe_ctx, context); +@@ -1478,19 +1484,19 @@ static void dcn20_program_pipe( + + if (pipe_ctx->update_flags.bits.enable + || pipe_ctx->plane_state->update_flags.bits.hdr_mult) +- dc->hwss.set_hdr_multiplier(pipe_ctx); ++ hws->funcs.set_hdr_multiplier(pipe_ctx); + + if (pipe_ctx->update_flags.bits.enable || + pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || + pipe_ctx->plane_state->update_flags.bits.gamma_change) +- dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); ++ hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); + + /* dcn10_translate_regamma_to_hw_format takes 750us to finish + * only do gamma programming for powering on, internal memcmp to avoid + * updating on slave planes + */ + if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) +- dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); ++ hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); + + /* If the pipe has been enabled or has a different opp, we + * should reprogram the fmt. This deals with cases where +@@ -1530,6 +1536,7 @@ void dcn20_program_front_end_for_ctx( + { + const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; + int i; ++ struct dce_hwseq *hws = dc->hwseq; + bool pipe_locked[MAX_PIPES] = {false}; + DC_LOGGER_INIT(dc->ctx->logger); + +@@ -1561,13 +1568,13 @@ void dcn20_program_front_end_for_ctx( + && !context->res_ctx.pipe_ctx[i].top_pipe + && !context->res_ctx.pipe_ctx[i].prev_odm_pipe + && context->res_ctx.pipe_ctx[i].stream) +- dc->hwss.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); ++ hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); + + /* Disconnect mpcc */ + for (i = 0; i < dc->res_pool->pipe_count; i++) + if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable + || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { +- dc->hwss.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); ++ hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); + DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); + } + +@@ -1587,8 +1594,8 @@ void dcn20_program_front_end_for_ctx( + pipe = &context->res_ctx.pipe_ctx[i]; + if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0 + && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw) +- && dc->hwss.program_all_writeback_pipes_in_tree) +- dc->hwss.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); ++ && hws->funcs.program_all_writeback_pipes_in_tree) ++ hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); + } + } + +@@ -1673,6 +1680,7 @@ bool dcn20_update_bandwidth( + struct dc_state *context) + { + int i; ++ struct dce_hwseq *hws = dc->hwseq; + + /* recalculate DML parameters */ + if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) +@@ -1702,10 +1710,10 @@ bool dcn20_update_bandwidth( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + + if (pipe_ctx->prev_odm_pipe == NULL) +- dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); ++ hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); + +- if (dc->hwss.setup_vupdate_interrupt) +- dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx); ++ if (hws->funcs.setup_vupdate_interrupt) ++ hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); + } + + pipe_ctx->plane_res.hubp->funcs->hubp_setup( +@@ -1942,6 +1950,7 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, + struct encoder_unblank_param params = { { 0 } }; + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; ++ struct dce_hwseq *hws = link->dc->hwseq; + struct pipe_ctx *odm_pipe; + + params.opp_cnt = 1; +@@ -1962,7 +1971,7 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, + } + + if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { +- link->dc->hwss.edp_backlight_control(link, true); ++ hws->funcs.edp_backlight_control(link, true); + } + } + +@@ -2050,6 +2059,7 @@ void dcn20_reset_hw_ctx_wrap( + struct dc_state *context) + { + int i; ++ struct dce_hwseq *hws = dc->hwseq; + + /* Reset Back End*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { +@@ -2068,8 +2078,8 @@ void dcn20_reset_hw_ctx_wrap( + struct clock_source *old_clk = pipe_ctx_old->clock_source; + + dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); +- if (dc->hwss.enable_stream_gating) +- dc->hwss.enable_stream_gating(dc, pipe_ctx); ++ if (hws->funcs.enable_stream_gating) ++ hws->funcs.enable_stream_gating(dc, pipe_ctx); + if (old_clk) + old_clk->funcs->cs_power_down(old_clk); + } +@@ -2100,6 +2110,7 @@ void dcn20_get_mpctree_visual_confirm_color( + + void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) + { ++ struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct mpcc_blnd_cfg blnd_cfg = { {0} }; + bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; +@@ -2110,10 +2121,10 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) + + // input to MPCC is always RGB, by default leave black_color at 0 + if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { +- dc->hwss.get_hdr_visual_confirm_color( ++ hws->funcs.get_hdr_visual_confirm_color( + pipe_ctx, &blnd_cfg.black_color); + } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { +- dc->hwss.get_surface_visual_confirm_color( ++ hws->funcs.get_surface_visual_confirm_color( + pipe_ctx, &blnd_cfg.black_color); + } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) { + dcn20_get_mpctree_visual_confirm_color( +@@ -2269,13 +2280,13 @@ void dcn20_fpga_init_hw(struct dc *dc) + res_pool->dccg->funcs->dccg_init(res_pool->dccg); + + //Enable ability to power gate / don't force power on permanently +- dc->hwss.enable_power_gating_plane(hws, true); ++ hws->funcs.enable_power_gating_plane(hws, true); + + // Specific to FPGA dccg and registers + REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); + REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); + +- dc->hwss.dccg_init(hws); ++ hws->funcs.dccg_init(hws); + + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); +@@ -2339,7 +2350,7 @@ void dcn20_fpga_init_hw(struct dc *dc) + dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; + pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; + /*to do*/ +- dc->hwss.plane_atomic_disconnect(dc, pipe_ctx); ++ hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); + } + + /* initialize DWB pointer to MCIF_WB */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +index f58b69c1b321..fe23a24c3325 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +@@ -26,6 +26,8 @@ + #ifndef __DC_HWSS_DCN20_H__ + #define __DC_HWSS_DCN20_H__ + ++#include "hw_sequencer_private.h" ++ + bool dcn20_set_blend_lut( + struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); + bool dcn20_set_shaper_3dlut( +@@ -111,6 +113,7 @@ void dcn20_disable_writeback( + void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); + bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx); + void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx); ++void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx); + void dcn20_init_vm_ctx( + struct dce_hwseq *hws, + struct dc *dc, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c +index 10493777d192..7ac145ef165f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c +@@ -30,19 +30,13 @@ + static const struct hw_sequencer_funcs dcn20_funcs = { + .program_gamut_remap = dcn10_program_gamut_remap, + .init_hw = dcn10_init_hw, +- .init_pipes = dcn10_init_pipes, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .apply_ctx_for_surface = NULL, + .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, + .update_plane_addr = dcn20_update_plane_addr, +- .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, + .update_dchub = dcn10_update_dchub, +- .update_mpcc = dcn20_update_mpcc, + .update_pending_status = dcn10_update_pending_status, +- .set_input_transfer_func = dcn20_set_input_transfer_func, +- .set_output_transfer_func = dcn20_set_output_transfer_func, + .program_output_csc = dcn20_program_output_csc, +- .power_down = dce110_power_down, + .enable_accelerated_mode = dce110_enable_accelerated_mode, + .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, +@@ -54,16 +48,12 @@ static const struct hw_sequencer_funcs dcn20_funcs = { + .blank_stream = dce110_blank_stream, + .enable_audio_stream = dce110_enable_audio_stream, + .disable_audio_stream = dce110_disable_audio_stream, +- .enable_display_power_gating = dcn10_dummy_display_power_gating, + .disable_plane = dcn20_disable_plane, +- .blank_pixel_data = dcn20_blank_pixel_data, + .pipe_control_lock = dcn20_pipe_control_lock, + .pipe_control_lock_global = dcn20_pipe_control_lock_global, + .prepare_bandwidth = dcn20_prepare_bandwidth, + .optimize_bandwidth = dcn20_optimize_bandwidth, + .update_bandwidth = dcn20_update_bandwidth, +- .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap, +- .enable_stream_timing = dcn20_enable_stream_timing, + .set_drr = dcn10_set_drr, + .get_position = dcn10_get_position, + .set_static_screen_control = dcn10_set_static_screen_control, +@@ -73,18 +63,42 @@ static const struct hw_sequencer_funcs dcn20_funcs = { + .get_hw_state = dcn10_get_hw_state, + .clear_status_bits = dcn10_clear_status_bits, + .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, +- .edp_backlight_control = dce110_edp_backlight_control, + .edp_power_control = dce110_edp_power_control, + .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, + .set_cursor_position = dcn10_set_cursor_position, + .set_cursor_attribute = dcn10_set_cursor_attribute, + .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, +- .disable_stream_gating = dcn20_disable_stream_gating, +- .enable_stream_gating = dcn20_enable_stream_gating, + .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, +- .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, + .set_clock = dcn10_set_clock, + .get_clock = dcn10_get_clock, ++ .program_triplebuffer = dcn20_program_triple_buffer, ++ .enable_writeback = dcn20_enable_writeback, ++ .disable_writeback = dcn20_disable_writeback, ++ .dmdata_status_done = dcn20_dmdata_status_done, ++ .program_dmdata_engine = dcn20_program_dmdata_engine, ++ .set_dmdata_attributes = dcn20_set_dmdata_attributes, ++ .init_sys_ctx = dcn20_init_sys_ctx, ++ .init_vm_ctx = dcn20_init_vm_ctx, ++ .set_flip_control_gsl = dcn20_set_flip_control_gsl, ++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, ++}; ++ ++static const struct hwseq_private_funcs dcn20_private_funcs = { ++ .init_pipes = dcn10_init_pipes, ++ .update_plane_addr = dcn20_update_plane_addr, ++ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, ++ .update_mpcc = dcn20_update_mpcc, ++ .set_input_transfer_func = dcn20_set_input_transfer_func, ++ .set_output_transfer_func = dcn20_set_output_transfer_func, ++ .power_down = dce110_power_down, ++ .enable_display_power_gating = dcn10_dummy_display_power_gating, ++ .blank_pixel_data = dcn20_blank_pixel_data, ++ .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap, ++ .enable_stream_timing = dcn20_enable_stream_timing, ++ .edp_backlight_control = dce110_edp_backlight_control, ++ .disable_stream_gating = dcn20_disable_stream_gating, ++ .enable_stream_gating = dcn20_enable_stream_gating, ++ .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, + .did_underflow_occur = dcn10_did_underflow_occur, + .init_blank = dcn20_init_blank, + .disable_vga = dcn20_disable_vga, +@@ -95,15 +109,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = { + .dpp_pg_control = dcn20_dpp_pg_control, + .hubp_pg_control = dcn20_hubp_pg_control, + .dsc_pg_control = NULL, +- .program_triplebuffer = dcn20_program_triple_buffer, +- .enable_writeback = dcn20_enable_writeback, +- .disable_writeback = dcn20_disable_writeback, + .update_odm = dcn20_update_odm, +- .dmdata_status_done = dcn20_dmdata_status_done, +- .program_dmdata_engine = dcn20_program_dmdata_engine, +- .init_sys_ctx = dcn20_init_sys_ctx, +- .init_vm_ctx = dcn20_init_vm_ctx, +- .set_flip_control_gsl = dcn20_set_flip_control_gsl, + #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .dsc_pg_control = dcn20_dsc_pg_control, + #else +@@ -117,15 +123,15 @@ static const struct hw_sequencer_funcs dcn20_funcs = { + .dccg_init = dcn20_dccg_init, + .set_blend_lut = dcn20_set_blend_lut, + .set_shaper_3dlut = dcn20_set_shaper_3dlut, +- .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, + }; + + void dcn20_hw_sequencer_construct(struct dc *dc) + { + dc->hwss = dcn20_funcs; ++ dc->hwseq->funcs = dcn20_private_funcs; + + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + dc->hwss.init_hw = dcn20_fpga_init_hw; +- dc->hwss.init_pipes = NULL; ++ dc->hwseq->funcs.init_pipes = NULL; + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c +index 005894dcabc9..081ad8e43d58 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c +@@ -28,6 +28,7 @@ + #include "core_types.h" + #include "resource.h" + #include "dce/dce_hwseq.h" ++#include "dcn21_hwseq.h" + #include "vmid.h" + #include "reg_helper.h" + #include "hw/clk_mgr.h" +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h +index 2f7b8a220eb9..182736096123 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h +@@ -26,6 +26,8 @@ + #ifndef __DC_HWSS_DCN21_H__ + #define __DC_HWSS_DCN21_H__ + ++#include "hw_sequencer_private.h" ++ + struct dc; + + int dcn21_init_sys_ctx(struct dce_hwseq *hws, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c +index cbd55037a04a..45e79a8b7070 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c +@@ -31,19 +31,13 @@ + static const struct hw_sequencer_funcs dcn21_funcs = { + .program_gamut_remap = dcn10_program_gamut_remap, + .init_hw = dcn10_init_hw, +- .init_pipes = dcn10_init_pipes, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .apply_ctx_for_surface = NULL, + .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, + .update_plane_addr = dcn20_update_plane_addr, +- .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, + .update_dchub = dcn10_update_dchub, +- .update_mpcc = dcn20_update_mpcc, + .update_pending_status = dcn10_update_pending_status, +- .set_input_transfer_func = dcn20_set_input_transfer_func, +- .set_output_transfer_func = dcn20_set_output_transfer_func, + .program_output_csc = dcn20_program_output_csc, +- .power_down = dce110_power_down, + .enable_accelerated_mode = dce110_enable_accelerated_mode, + .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, +@@ -55,16 +49,12 @@ static const struct hw_sequencer_funcs dcn21_funcs = { + .blank_stream = dce110_blank_stream, + .enable_audio_stream = dce110_enable_audio_stream, + .disable_audio_stream = dce110_disable_audio_stream, +- .enable_display_power_gating = dcn10_dummy_display_power_gating, + .disable_plane = dcn20_disable_plane, +- .blank_pixel_data = dcn20_blank_pixel_data, + .pipe_control_lock = dcn20_pipe_control_lock, + .pipe_control_lock_global = dcn20_pipe_control_lock_global, + .prepare_bandwidth = dcn20_prepare_bandwidth, + .optimize_bandwidth = dcn20_optimize_bandwidth, + .update_bandwidth = dcn20_update_bandwidth, +- .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap, +- .enable_stream_timing = dcn20_enable_stream_timing, + .set_drr = dcn10_set_drr, + .get_position = dcn10_get_position, + .set_static_screen_control = dcn10_set_static_screen_control, +@@ -74,18 +64,49 @@ static const struct hw_sequencer_funcs dcn21_funcs = { + .get_hw_state = dcn10_get_hw_state, + .clear_status_bits = dcn10_clear_status_bits, + .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, +- .edp_backlight_control = dce110_edp_backlight_control, + .edp_power_control = dce110_edp_power_control, + .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, + .set_cursor_position = dcn10_set_cursor_position, + .set_cursor_attribute = dcn10_set_cursor_attribute, + .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, +- .disable_stream_gating = dcn20_disable_stream_gating, +- .enable_stream_gating = dcn20_enable_stream_gating, + .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, +- .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, + .set_clock = dcn10_set_clock, + .get_clock = dcn10_get_clock, ++ .program_triplebuffer = dcn20_program_triple_buffer, ++ .enable_writeback = dcn20_enable_writeback, ++ .disable_writeback = dcn20_disable_writeback, ++ .dmdata_status_done = dcn20_dmdata_status_done, ++ .program_dmdata_engine = dcn20_program_dmdata_engine, ++ .set_dmdata_attributes = dcn20_set_dmdata_attributes, ++ .init_sys_ctx = dcn21_init_sys_ctx, ++ .init_vm_ctx = dcn20_init_vm_ctx, ++ .set_flip_control_gsl = dcn20_set_flip_control_gsl, ++ .optimize_pwr_state = dcn21_optimize_pwr_state, ++ .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, ++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, ++ .set_cursor_position = dcn10_set_cursor_position, ++ .set_cursor_attribute = dcn10_set_cursor_attribute, ++ .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, ++ .optimize_pwr_state = dcn21_optimize_pwr_state, ++ .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, ++}; ++ ++static const struct hwseq_private_funcs dcn21_private_funcs = { ++ .init_pipes = dcn10_init_pipes, ++ .update_plane_addr = dcn20_update_plane_addr, ++ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, ++ .update_mpcc = dcn20_update_mpcc, ++ .set_input_transfer_func = dcn20_set_input_transfer_func, ++ .set_output_transfer_func = dcn20_set_output_transfer_func, ++ .power_down = dce110_power_down, ++ .enable_display_power_gating = dcn10_dummy_display_power_gating, ++ .blank_pixel_data = dcn20_blank_pixel_data, ++ .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap, ++ .enable_stream_timing = dcn20_enable_stream_timing, ++ .edp_backlight_control = dce110_edp_backlight_control, ++ .disable_stream_gating = dcn20_disable_stream_gating, ++ .enable_stream_gating = dcn20_enable_stream_gating, ++ .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, + .did_underflow_occur = dcn10_did_underflow_occur, + .init_blank = dcn20_init_blank, + .disable_vga = dcn20_disable_vga, +@@ -96,15 +117,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = { + .dpp_pg_control = dcn20_dpp_pg_control, + .hubp_pg_control = dcn20_hubp_pg_control, + .dsc_pg_control = NULL, +- .program_triplebuffer = dcn20_program_triple_buffer, +- .enable_writeback = dcn20_enable_writeback, +- .disable_writeback = dcn20_disable_writeback, + .update_odm = dcn20_update_odm, +- .dmdata_status_done = dcn20_dmdata_status_done, +- .program_dmdata_engine = dcn20_program_dmdata_engine, +- .init_sys_ctx = dcn21_init_sys_ctx, +- .init_vm_ctx = dcn20_init_vm_ctx, +- .set_flip_control_gsl = dcn20_set_flip_control_gsl, + #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .dsc_pg_control = dcn20_dsc_pg_control, + #else +@@ -115,21 +128,19 @@ static const struct hw_sequencer_funcs dcn21_funcs = { + .set_hdr_multiplier = dcn10_set_hdr_multiplier, + .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, + .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa, +- .optimize_pwr_state = dcn21_optimize_pwr_state, +- .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, + .wait_for_blank_complete = dcn20_wait_for_blank_complete, + .dccg_init = dcn20_dccg_init, + .set_blend_lut = dcn20_set_blend_lut, + .set_shaper_3dlut = dcn20_set_shaper_3dlut, +- .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, + }; + + void dcn21_hw_sequencer_construct(struct dc *dc) + { + dc->hwss = dcn21_funcs; ++ dc->hwseq->funcs = dcn21_private_funcs; + + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + dc->hwss.init_hw = dcn20_fpga_init_hw; +- dc->hwss.init_pipes = NULL; ++ dc->hwseq->funcs.init_pipes = NULL; + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +index 937a02d02f18..54b3e88bf0d3 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +@@ -32,294 +32,137 @@ + #include "inc/hw/link_encoder.h" + #include "core_status.h" + +-enum pipe_gating_control { +- PIPE_GATING_CONTROL_DISABLE = 0, +- PIPE_GATING_CONTROL_ENABLE, +- PIPE_GATING_CONTROL_INIT +-}; +- + enum vline_select { + VLINE0, + VLINE1 + }; + +-struct dce_hwseq_wa { +- bool blnd_crtc_trigger; +- bool DEGVIDCN10_253; +- bool false_optc_underflow; +- bool DEGVIDCN10_254; +- bool DEGVIDCN21; +-}; +- +-struct hwseq_wa_state { +- bool DEGVIDCN10_253_applied; +-}; +- +-struct dce_hwseq { +- struct dc_context *ctx; +- const struct dce_hwseq_registers *regs; +- const struct dce_hwseq_shift *shifts; +- const struct dce_hwseq_mask *masks; +- struct dce_hwseq_wa wa; +- struct hwseq_wa_state wa_state; +-}; +- + struct pipe_ctx; + struct dc_state; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_stream_status; + struct dc_writeback_info; ++#endif + struct dchub_init_data; + struct dc_static_screen_events; + struct resource_pool; +-struct resource_context; +-struct stream_resource; ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct dc_phy_addr_space_config; + struct dc_virtual_addr_space_config; +-struct hubp; ++#endif + struct dpp; ++struct dce_hwseq; + + struct hw_sequencer_funcs { ++ /* Embedded Display Related */ ++ void (*edp_power_control)(struct dc_link *link, bool enable); ++ void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); + +- void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); +- +- void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); +- ++ /* Pipe Programming Related */ + void (*init_hw)(struct dc *dc); +- +- void (*init_pipes)(struct dc *dc, struct dc_state *context); +- +- enum dc_status (*apply_ctx_to_hw)( +- struct dc *dc, struct dc_state *context); +- +- void (*reset_hw_ctx_wrap)( +- struct dc *dc, struct dc_state *context); +- +- void (*apply_ctx_for_surface)( +- struct dc *dc, ++ void (*enable_accelerated_mode)(struct dc *dc, ++ struct dc_state *context); ++ enum dc_status (*apply_ctx_to_hw)(struct dc *dc, ++ struct dc_state *context); ++ void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); ++ void (*apply_ctx_for_surface)(struct dc *dc, + const struct dc_stream_state *stream, +- int num_planes, ++ int num_planes, struct dc_state *context); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ void (*program_front_end_for_ctx)(struct dc *dc, + struct dc_state *context); +- +- void (*program_gamut_remap)( ++#endif ++ void (*update_plane_addr)(const struct dc *dc, + struct pipe_ctx *pipe_ctx); +- +- void (*program_output_csc)(struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- enum dc_color_space colorspace, +- uint16_t *matrix, +- int opp_id); +- +- void (*program_front_end_for_ctx)( +- struct dc *dc, +- struct dc_state *context); +- void (*program_triplebuffer)( +- const struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- bool enableTripleBuffer); +- void (*set_flip_control_gsl)( +- struct pipe_ctx *pipe_ctx, +- bool flip_immediate); +- +- void (*update_plane_addr)( +- const struct dc *dc, +- struct pipe_ctx *pipe_ctx); +- +- void (*plane_atomic_disconnect)( +- struct dc *dc, +- struct pipe_ctx *pipe_ctx); +- +- void (*update_dchub)( +- struct dce_hwseq *hws, +- struct dchub_init_data *dh_data); +- +- int (*init_sys_ctx)( +- struct dce_hwseq *hws, +- struct dc *dc, +- struct dc_phy_addr_space_config *pa_config); +- void (*init_vm_ctx)( +- struct dce_hwseq *hws, +- struct dc *dc, +- struct dc_virtual_addr_space_config *va_config, +- int vmid); +- void (*update_mpcc)( +- struct dc *dc, +- struct pipe_ctx *pipe_ctx); +- +- void (*update_pending_status)( ++ void (*update_dchub)(struct dce_hwseq *hws, ++ struct dchub_init_data *dh_data); ++ void (*wait_for_mpcc_disconnect)(struct dc *dc, ++ struct resource_pool *res_pool, + struct pipe_ctx *pipe_ctx); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ void (*program_triplebuffer)(const struct dc *dc, ++ struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); ++#endif ++ void (*update_pending_status)(struct pipe_ctx *pipe_ctx); ++ ++ /* Pipe Lock Related */ ++ void (*pipe_control_lock_global)(struct dc *dc, ++ struct pipe_ctx *pipe, bool lock); ++ void (*pipe_control_lock)(struct dc *dc, ++ struct pipe_ctx *pipe, bool lock); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, ++ bool flip_immediate); ++#endif + +- bool (*set_input_transfer_func)(struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- const struct dc_plane_state *plane_state); +- +- bool (*set_output_transfer_func)(struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- const struct dc_stream_state *stream); +- +- void (*power_down)(struct dc *dc); +- +- void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context); +- +- void (*enable_timing_synchronization)( +- struct dc *dc, +- int group_index, +- int group_size, +- struct pipe_ctx *grouped_pipes[]); +- +- void (*enable_per_frame_crtc_position_reset)( +- struct dc *dc, +- int group_size, ++ /* Timing Related */ ++ void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, ++ struct crtc_position *position); ++ int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); ++ void (*enable_per_frame_crtc_position_reset)(struct dc *dc, ++ int group_size, struct pipe_ctx *grouped_pipes[]); ++ void (*enable_timing_synchronization)(struct dc *dc, ++ int group_index, int group_size, + struct pipe_ctx *grouped_pipes[]); ++ void (*setup_periodic_interrupt)(struct dc *dc, ++ struct pipe_ctx *pipe_ctx, ++ enum vline_select vline); ++ void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, ++ unsigned int vmin, unsigned int vmax, ++ unsigned int vmid, unsigned int vmid_frame_number); ++ void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, ++ int num_pipes, ++ const struct dc_static_screen_events *events); + +- void (*enable_display_pipe_clock_gating)( +- struct dc_context *ctx, +- bool clock_gating); +- +- bool (*enable_display_power_gating)( +- struct dc *dc, +- uint8_t controller_id, +- struct dc_bios *dcb, +- enum pipe_gating_control power_gating); +- +- void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); +- +- void (*update_info_frame)(struct pipe_ctx *pipe_ctx); +- +- void (*send_immediate_sdp_message)( +- struct pipe_ctx *pipe_ctx, +- const uint8_t *custom_sdp_message, +- unsigned int sdp_message_size); +- ++ /* Stream Related */ + void (*enable_stream)(struct pipe_ctx *pipe_ctx); +- + void (*disable_stream)(struct pipe_ctx *pipe_ctx); +- ++ void (*blank_stream)(struct pipe_ctx *pipe_ctx); + void (*unblank_stream)(struct pipe_ctx *pipe_ctx, + struct dc_link_settings *link_settings); + +- void (*blank_stream)(struct pipe_ctx *pipe_ctx); +- +- void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); +- +- void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); +- +- void (*pipe_control_lock)( +- struct dc *dc, +- struct pipe_ctx *pipe, +- bool lock); ++ /* Bandwidth Related */ ++ void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); ++#endif ++ void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); + +- void (*pipe_control_lock_global)( +- struct dc *dc, +- struct pipe_ctx *pipe, +- bool lock); +- void (*blank_pixel_data)( +- struct dc *dc, ++ /* Infopacket Related */ ++ void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); ++ void (*send_immediate_sdp_message)( + struct pipe_ctx *pipe_ctx, +- bool blank); +- +- void (*prepare_bandwidth)( +- struct dc *dc, +- struct dc_state *context); +- void (*optimize_bandwidth)( +- struct dc *dc, +- struct dc_state *context); +- +- void (*exit_optimized_pwr_state)( +- const struct dc *dc, +- struct dc_state *context); +- void (*optimize_pwr_state)( +- const struct dc *dc, +- struct dc_state *context); +- +- bool (*update_bandwidth)( +- struct dc *dc, +- struct dc_state *context); ++ const uint8_t *custom_sdp_message, ++ unsigned int sdp_message_size); ++ void (*update_info_frame)(struct pipe_ctx *pipe_ctx); ++ void (*set_dmdata_attributes)(struct pipe_ctx *pipe); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); + bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); ++#endif + +- void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, +- unsigned int vmin, unsigned int vmax, +- unsigned int vmid, unsigned int vmid_frame_number); +- +- void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, +- struct crtc_position *position); +- +- void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, +- int num_pipes, const struct dc_static_screen_events *events); +- +- enum dc_status (*enable_stream_timing)( +- struct pipe_ctx *pipe_ctx, +- struct dc_state *context, +- struct dc *dc); +- +- void (*setup_stereo)( +- struct pipe_ctx *pipe_ctx, +- struct dc *dc); +- +- void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); +- +- void (*log_hw_state)(struct dc *dc, +- struct dc_log_buffer_ctx *log_ctx); +- void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask); +- void (*clear_status_bits)(struct dc *dc, unsigned int mask); +- +- void (*wait_for_mpcc_disconnect)(struct dc *dc, +- struct resource_pool *res_pool, +- struct pipe_ctx *pipe_ctx); +- +- void (*edp_power_control)( +- struct dc_link *link, +- bool enable); +- void (*edp_backlight_control)( +- struct dc_link *link, +- bool enable); +- void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); +- ++ /* Cursor Related */ + void (*set_cursor_position)(struct pipe_ctx *pipe); + void (*set_cursor_attribute)(struct pipe_ctx *pipe); + void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); + +- void (*setup_periodic_interrupt)(struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- enum vline_select vline); +- void (*setup_vupdate_interrupt)(struct dc *dc, struct pipe_ctx *pipe_ctx); +- bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); +- +- void (*init_blank)(struct dc *dc, struct timing_generator *tg); +- void (*disable_vga)(struct dce_hwseq *hws); +- void (*bios_golden_init)(struct dc *dc); +- void (*plane_atomic_power_down)(struct dc *dc, +- struct dpp *dpp, +- struct hubp *hubp); +- +- void (*plane_atomic_disable)( +- struct dc *dc, struct pipe_ctx *pipe_ctx); +- +- void (*enable_power_gating_plane)( +- struct dce_hwseq *hws, +- bool enable); +- +- void (*dpp_pg_control)( +- struct dce_hwseq *hws, +- unsigned int dpp_inst, +- bool power_on); +- +- void (*hubp_pg_control)( +- struct dce_hwseq *hws, +- unsigned int hubp_inst, +- bool power_on); +- +- void (*dsc_pg_control)( +- struct dce_hwseq *hws, +- unsigned int dsc_inst, +- bool power_on); +- ++ /* Colour Related */ ++ void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); ++ void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, ++ enum dc_color_space colorspace, ++ uint16_t *matrix, int opp_id); + +- void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); +- void (*program_all_writeback_pipes_in_tree)( ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ /* VM Related */ ++ int (*init_sys_ctx)(struct dce_hwseq *hws, + struct dc *dc, +- const struct dc_stream_state *stream, +- struct dc_state *context); ++ struct dc_phy_addr_space_config *pa_config); ++ void (*init_vm_ctx)(struct dce_hwseq *hws, ++ struct dc *dc, ++ struct dc_virtual_addr_space_config *va_config, ++ int vmid); ++ ++ /* Writeback Related */ + void (*update_writeback)(struct dc *dc, + const struct dc_stream_status *stream_status, + struct dc_writeback_info *wb_info, +@@ -330,48 +173,34 @@ struct hw_sequencer_funcs { + struct dc_state *context); + void (*disable_writeback)(struct dc *dc, + unsigned int dwb_pipe_inst); +- enum dc_status (*set_clock)(struct dc *dc, +- enum dc_clock_type clock_type, +- uint32_t clk_khz, +- uint32_t stepping); ++#endif + +- void (*get_clock)(struct dc *dc, ++ /* Clock Related */ ++ enum dc_status (*set_clock)(struct dc *dc, + enum dc_clock_type clock_type, ++ uint32_t clk_khz, uint32_t stepping); ++ void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, + struct dc_clock_config *clock_cfg); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_1) +- bool (*s0i3_golden_init_wa)(struct dc *dc); +-#endif +- +- void (*get_surface_visual_confirm_color)( +- const struct pipe_ctx *pipe_ctx, +- struct tg_color *color); +- +- void (*get_hdr_visual_confirm_color)( +- struct pipe_ctx *pipe_ctx, +- struct tg_color *color); +- +- void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx); +- +- void (*verify_allow_pstate_change_high)(struct dc *dc); +- +- void (*program_pipe)( +- struct dc *dc, +- struct pipe_ctx *pipe_ctx, ++ void (*optimize_pwr_state)(const struct dc *dc, ++ struct dc_state *context); ++ void (*exit_optimized_pwr_state)(const struct dc *dc, + struct dc_state *context); + +- bool (*wait_for_blank_complete)( +- struct output_pixel_processor *opp); ++ /* Audio Related */ ++ void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); ++ void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); + +- void (*dccg_init)(struct dce_hwseq *hws); ++ /* Stereo 3D Related */ ++ void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); + +- bool (*set_blend_lut)( +- struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); ++ /* HW State Logging Related */ ++ void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); ++ void (*get_hw_state)(struct dc *dc, char *pBuf, ++ unsigned int bufSize, unsigned int mask); ++ void (*clear_status_bits)(struct dc *dc, unsigned int mask); + +- bool (*set_shaper_3dlut)( +- struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); + +- int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); + }; + + void color_space_to_black_color( +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +new file mode 100644 +index 000000000000..8ba06f015975 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +@@ -0,0 +1,156 @@ ++/* ++ * Copyright 2015 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#ifndef __DC_HW_SEQUENCER_PRIVATE_H__ ++#define __DC_HW_SEQUENCER_PRIVATE_H__ ++ ++#include "dc_types.h" ++ ++enum pipe_gating_control { ++ PIPE_GATING_CONTROL_DISABLE = 0, ++ PIPE_GATING_CONTROL_ENABLE, ++ PIPE_GATING_CONTROL_INIT ++}; ++ ++struct dce_hwseq_wa { ++ bool blnd_crtc_trigger; ++ bool DEGVIDCN10_253; ++ bool false_optc_underflow; ++ bool DEGVIDCN10_254; ++ bool DEGVIDCN21; ++}; ++ ++struct hwseq_wa_state { ++ bool DEGVIDCN10_253_applied; ++}; ++ ++struct pipe_ctx; ++struct dc_state; ++struct dc_stream_status; ++struct dc_writeback_info; ++struct dchub_init_data; ++struct dc_static_screen_events; ++struct resource_pool; ++struct resource_context; ++struct stream_resource; ++struct dc_phy_addr_space_config; ++struct dc_virtual_addr_space_config; ++struct hubp; ++struct dpp; ++struct dce_hwseq; ++struct timing_generator; ++struct tg_color; ++struct output_pixel_processor; ++ ++struct hwseq_private_funcs { ++ ++ void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); ++ void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); ++ void (*init_pipes)(struct dc *dc, struct dc_state *context); ++ void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context); ++ void (*update_plane_addr)(const struct dc *dc, ++ struct pipe_ctx *pipe_ctx); ++ void (*plane_atomic_disconnect)(struct dc *dc, ++ struct pipe_ctx *pipe_ctx); ++ void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx); ++ bool (*set_input_transfer_func)(struct dc *dc, ++ struct pipe_ctx *pipe_ctx, ++ const struct dc_plane_state *plane_state); ++ bool (*set_output_transfer_func)(struct dc *dc, ++ struct pipe_ctx *pipe_ctx, ++ const struct dc_stream_state *stream); ++ void (*power_down)(struct dc *dc); ++ void (*enable_display_pipe_clock_gating)(struct dc_context *ctx, ++ bool clock_gating); ++ bool (*enable_display_power_gating)(struct dc *dc, ++ uint8_t controller_id, ++ struct dc_bios *dcb, ++ enum pipe_gating_control power_gating); ++ void (*blank_pixel_data)(struct dc *dc, ++ struct pipe_ctx *pipe_ctx, ++ bool blank); ++ enum dc_status (*enable_stream_timing)( ++ struct pipe_ctx *pipe_ctx, ++ struct dc_state *context, ++ struct dc *dc); ++ void (*edp_backlight_control)(struct dc_link *link, ++ bool enable); ++ void (*setup_vupdate_interrupt)(struct dc *dc, ++ struct pipe_ctx *pipe_ctx); ++ bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); ++ void (*init_blank)(struct dc *dc, struct timing_generator *tg); ++ void (*disable_vga)(struct dce_hwseq *hws); ++ void (*bios_golden_init)(struct dc *dc); ++ void (*plane_atomic_power_down)(struct dc *dc, ++ struct dpp *dpp, ++ struct hubp *hubp); ++ void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx); ++ void (*enable_power_gating_plane)(struct dce_hwseq *hws, ++ bool enable); ++ void (*dpp_pg_control)(struct dce_hwseq *hws, ++ unsigned int dpp_inst, ++ bool power_on); ++ void (*hubp_pg_control)(struct dce_hwseq *hws, ++ unsigned int hubp_inst, ++ bool power_on); ++ void (*dsc_pg_control)(struct dce_hwseq *hws, ++ unsigned int dsc_inst, ++ bool power_on); ++ void (*update_odm)(struct dc *dc, struct dc_state *context, ++ struct pipe_ctx *pipe_ctx); ++ void (*program_all_writeback_pipes_in_tree)(struct dc *dc, ++ const struct dc_stream_state *stream, ++ struct dc_state *context); ++ bool (*s0i3_golden_init_wa)(struct dc *dc); ++ void (*get_surface_visual_confirm_color)( ++ const struct pipe_ctx *pipe_ctx, ++ struct tg_color *color); ++ void (*get_hdr_visual_confirm_color)(struct pipe_ctx *pipe_ctx, ++ struct tg_color *color); ++ void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx); ++ void (*verify_allow_pstate_change_high)(struct dc *dc); ++ void (*program_pipe)(struct dc *dc, ++ struct pipe_ctx *pipe_ctx, ++ struct dc_state *context); ++ bool (*wait_for_blank_complete)(struct output_pixel_processor *opp); ++ void (*dccg_init)(struct dce_hwseq *hws); ++ bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx, ++ const struct dc_plane_state *plane_state); ++ bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx, ++ const struct dc_plane_state *plane_state); ++}; ++ ++struct dce_hwseq { ++ struct dc_context *ctx; ++ const struct dce_hwseq_registers *regs; ++ const struct dce_hwseq_shift *shifts; ++ const struct dce_hwseq_mask *masks; ++ struct dce_hwseq_wa wa; ++ struct hwseq_wa_state wa_state; ++ struct hwseq_private_funcs funcs; ++ ++}; ++ ++#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */ +-- +2.17.1 + |