diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch new file mode 100644 index 00000000..55c78e06 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch @@ -0,0 +1,55 @@ +From 995d14032141d5875eb3578387bce42f2deabcfc Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Fri, 22 Nov 2019 17:56:47 +0800 +Subject: [PATCH 4659/4736] drm/amdgpu: clear ras controller status registers + when interrupt occurs + +To fix issue that ras controller interrupt cannot be triggered anymore after +one time nbif uncorrectable error. And error count is stored in nbif ras object +for query. + +Change-Id: Iba482c169fdff3e9c390072c0289a622a522133c +Signed-off-by: Le Ma <le.ma@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +index 25231d699341..9a3a65a0691c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +@@ -52,6 +52,9 @@ + #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL + #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L + ++static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, ++ void *ras_error_status); ++ + static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) + { + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, +@@ -314,6 +317,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev) + static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) + { + uint32_t bif_doorbell_intr_cntl; ++ struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); + + bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); + if (REG_GET_FIELD(bif_doorbell_intr_cntl, +@@ -324,6 +328,12 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device + RAS_CNTLR_INTERRUPT_CLEAR, 1); + WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); + ++ /* ++ * clear error status after ras_controller_intr according to ++ * hw team and count ue number for query ++ */ ++ nbio_v7_4_query_ras_error_count(adev, &obj->err_data); ++ + DRM_WARN("RAS controller interrupt triggered by NBIF error\n"); + + /* ras_controller_int is dedicated for nbif ras error, +-- +2.17.1 + |