diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch | 5022 |
1 files changed, 5022 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch new file mode 100644 index 00000000..1debddf9 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch @@ -0,0 +1,5022 @@ +From 3ffff051d14b90a48427a1a00b28557d625a6567 Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 6 Nov 2019 14:38:55 -0500 +Subject: [PATCH 4555/4736] drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and + DSC_SUPPORTED + +[Why] + +DCN2 and DSC are stable enough to be build by default. So drop the flags. + +[How] + +Remove them using the unifdef tool. The following commands were executed +in sequence: + +$ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' +$ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' + +In addition: + +* Remove from kconfig, and replace any dependencies with DCN1_0. +* Remove from any makefiles. +* Fix and cleanup NV defninitions in dal_asic_id.h +* Expand DCN1 ifdef to include DCN2 code in the following files: + * clk_mgr/clk_mgr.c: dc_clk_mgr_create() + * core/dc_resources.c: dc_create_resource_pool() + * dce/dce_dmcu.c: dcn20_*lock_phy() + * dce/dce_dmcu.c: dcn20_funcs + * dce/dce_dmcu.c: dcn20_dmcu_create() + * gpio/hw_factory.c: dal_hw_factory_init() + * gpio/hw_translate.c: dal_hw_translate_init() + +Signed-off-by: Leo Li <sunpeng.li@amd.com> +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 -- + drivers/gpu/drm/amd/display/Kconfig | 13 +---- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ----- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 - + .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 - + .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 2 - + drivers/gpu/drm/amd/display/dc/Makefile | 12 ++--- + .../drm/amd/display/dc/bios/bios_parser2.c | 2 - + .../display/dc/bios/command_table_helper2.c | 2 - + .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 -- + .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 2 - + .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 4 +- + drivers/gpu/drm/amd/display/dc/core/dc.c | 48 ------------------- + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 ------- + .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 24 ---------- + .../drm/amd/display/dc/core/dc_link_hwss.c | 6 --- + .../gpu/drm/amd/display/dc/core/dc_resource.c | 8 +--- + .../gpu/drm/amd/display/dc/core/dc_stream.c | 6 --- + .../gpu/drm/amd/display/dc/core/dc_surface.c | 6 --- + drivers/gpu/drm/amd/display/dc/dc.h | 38 --------------- + drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 4 -- + drivers/gpu/drm/amd/display/dc/dc_dsc.h | 2 - + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 20 -------- + drivers/gpu/drm/amd/display/dc/dc_link.h | 4 -- + drivers/gpu/drm/amd/display/dc/dc_stream.h | 16 ------- + drivers/gpu/drm/amd/display/dc/dc_types.h | 6 --- + drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 4 -- + drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 2 - + .../drm/amd/display/dc/dce/dce_clock_source.c | 4 -- + .../drm/amd/display/dc/dce/dce_clock_source.h | 6 --- + drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 14 ++---- + drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 2 - + .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 4 -- + .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 6 --- + .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 8 ---- + .../display/dc/dce110/dce110_hw_sequencer.c | 4 -- + .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 6 --- + .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 4 -- + .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 2 - + .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 2 - + .../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 2 - + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 4 -- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 2 - + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 ------- + .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 4 -- + .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 6 --- + .../amd/display/dc/dcn10/dcn10_link_encoder.h | 10 ---- + .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 2 - + .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 4 -- + .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 4 -- + .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 9 ---- + .../display/dc/dcn10/dcn10_stream_encoder.h | 8 ---- + drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 2 - + .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 - + .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 2 - + .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 - + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 14 ------ + .../amd/display/dc/dcn20/dcn20_link_encoder.c | 6 --- + .../amd/display/dc/dcn20/dcn20_link_encoder.h | 2 - + .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 4 -- + .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 2 - + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 42 ---------------- + .../drm/amd/display/dc/dcn20/dcn20_resource.h | 2 - + .../display/dc/dcn20/dcn20_stream_encoder.c | 6 --- + .../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 - + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 16 ------- + drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 - + drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 --- + drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 +- + .../dc/dml/dcn21/display_mode_vba_21.c | 2 - + .../dc/dml/dcn21/display_rq_dlg_calc_21.c | 2 - + .../amd/display/dc/dml/display_mode_enums.h | 2 - + .../drm/amd/display/dc/dml/display_mode_lib.c | 6 --- + .../drm/amd/display/dc/dml/display_mode_lib.h | 6 --- + .../amd/display/dc/dml/display_mode_structs.h | 2 - + .../drm/amd/display/dc/dml/display_mode_vba.c | 2 - + .../drm/amd/display/dc/dml/display_mode_vba.h | 2 - + drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 - + .../gpu/drm/amd/display/dc/dsc/dscc_types.h | 2 - + .../gpu/drm/amd/display/dc/dsc/qp_tables.h | 2 - + drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 2 - + drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 2 - + .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 2 - + drivers/gpu/drm/amd/display/dc/gpio/Makefile | 2 - + .../display/dc/gpio/dcn20/hw_factory_dcn20.c | 2 - + .../display/dc/gpio/dcn20/hw_factory_dcn20.h | 2 - + .../dc/gpio/dcn20/hw_translate_dcn20.c | 2 - + .../dc/gpio/dcn20/hw_translate_dcn20.h | 2 - + .../display/dc/gpio/dcn21/hw_factory_dcn21.c | 2 - + .../dc/gpio/dcn21/hw_translate_dcn21.c | 2 - + .../gpu/drm/amd/display/dc/gpio/ddc_regs.h | 12 ----- + drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 4 -- + .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 6 +-- + .../drm/amd/display/dc/gpio/hw_translate.c | 6 +-- + .../gpu/drm/amd/display/dc/inc/core_status.h | 2 - + .../gpu/drm/amd/display/dc/inc/core_types.h | 22 --------- + .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 - + .../amd/display/dc/inc/hw/clk_mgr_internal.h | 12 ----- + .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 4 -- + drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 12 ----- + drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h | 2 - + drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 10 ---- + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 -- + .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 10 ---- + .../drm/amd/display/dc/inc/hw/link_encoder.h | 8 ---- + drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 10 ---- + drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 4 -- + .../amd/display/dc/inc/hw/stream_encoder.h | 10 ---- + .../amd/display/dc/inc/hw/timing_generator.h | 8 ---- + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 12 ----- + drivers/gpu/drm/amd/display/dc/inc/resource.h | 4 -- + drivers/gpu/drm/amd/display/dc/irq/Makefile | 2 - + .../dc/virtual/virtual_stream_encoder.c | 8 ---- + .../gpu/drm/amd/display/include/dal_asic_id.h | 2 - + .../gpu/drm/amd/display/include/dal_types.h | 2 - + .../drm/amd/display/include/logger_types.h | 6 --- + .../drm/amd/display/modules/inc/mod_shared.h | 2 - + 117 files changed, 14 insertions(+), 744 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 62d088a4840b..3f587dce39e2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1545,7 +1545,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) + } + + parse_soc_bounding_box: +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + /* + * soc bounding box info is not integrated in disocovery table, + * we always need to parse it from gpu info firmware. +@@ -1556,7 +1555,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; + } +-#endif + break; + } + default: +@@ -2620,8 +2618,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) + case CHIP_VEGA20: + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: +-#endif +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case CHIP_NAVI10: + case CHIP_NAVI14: + case CHIP_NAVI12: +diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig +index 9eae7c67ceb5..19250f316da3 100644 +--- a/drivers/gpu/drm/amd/display/Kconfig ++++ b/drivers/gpu/drm/amd/display/Kconfig +@@ -14,21 +14,11 @@ config DRM_AMD_DC + config DRM_AMD_DC_DCN1_0 + def_bool n + help +- RV family support for display engine +- +-config DRM_AMD_DC_DCN2_0 +- bool "DCN 2.0 family" +- default y +- depends on DRM_AMD_DC && X86 +- depends on DRM_AMD_DC_DCN1_0 +- help +- Choose this option if you want to have +- Navi support for display engine ++ RV and NV family support for display engine + + config DRM_AMD_DC_DCN2_1 + bool "DCN 2.1 family" + depends on DRM_AMD_DC && X86 +- depends on DRM_AMD_DC_DCN2_0 + help + Choose this option if you want to have + Renoir support for display engine +@@ -38,7 +28,6 @@ config DRM_AMD_DC_DSC_SUPPORT + default y + depends on DRM_AMD_DC && X86 + depends on DRM_AMD_DC_DCN1_0 +- depends on DRM_AMD_DC_DCN2_0 + help + Choose this option if you want to have + Dynamic Stream Compression support +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 430008124373..3ec482e79ecf 100755 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -943,9 +943,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) + + init_data.flags.power_down_display_on_boot = true; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + init_data.soc_bounding_box = adev->dm.soc_bounding_box; +-#endif + + /* Display Core create. */ + adev->dm.dc = dc_create(&init_data); +@@ -2741,10 +2739,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + break; + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case CHIP_NAVI10: + case CHIP_NAVI14: +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + case CHIP_RENOIR: + #endif +@@ -2985,7 +2981,6 @@ static int dm_early_init(void *handle) + adev->mode_info.num_dig = 4; + break; + #endif +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case CHIP_NAVI10: + case CHIP_NAVI12: + adev->mode_info.num_crtc = 6; +@@ -2997,7 +2992,6 @@ static int dm_early_init(void *handle) + adev->mode_info.num_hpd = 5; + adev->mode_info.num_dig = 5; + break; +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + case CHIP_RENOIR: + adev->mode_info.num_crtc = 4; +@@ -3297,11 +3291,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, + if (adev->asic_type == CHIP_VEGA10 || + adev->asic_type == CHIP_VEGA12 || + adev->asic_type == CHIP_VEGA20 || +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + adev->asic_type == CHIP_NAVI10 || + adev->asic_type == CHIP_NAVI14 || + adev->asic_type == CHIP_NAVI12 || +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + adev->asic_type == CHIP_RENOIR || + #endif +@@ -4001,10 +3993,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; + int mode_refresh; + int preferred_refresh = 0; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct dsc_dec_dpcd_caps dsc_caps; + uint32_t link_bandwidth_kbps; +-#endif + + struct dc_sink *sink = NULL; + if (aconnector == NULL) { +@@ -4078,7 +4068,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + fill_stream_properties_from_drm_display_mode(stream, + &mode, &aconnector->base, con_state, old_stream); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + stream->timing.flags.DSC = 0; + + if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { +@@ -4097,7 +4086,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + &stream->timing.dsc_cfg)) + stream->timing.flags.DSC = 1; + } +-#endif + + update_stream_scaling_settings(&mode, dm_state, stream); + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +index 1fc810bf02af..e5ef8be7b813 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +@@ -281,7 +281,6 @@ struct amdgpu_display_manager { + + const struct firmware *fw_dmcu; + uint32_t dmcu_fw_version; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + /** + * @soc_bounding_box: + * +@@ -289,7 +288,6 @@ struct amdgpu_display_manager { + * available in FW + */ + const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; +-#endif + }; + + struct amdgpu_dm_connector { +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +index 92ba7ca84d7c..8522e66db4ea 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +@@ -539,7 +539,6 @@ bool dm_helpers_submit_i2c( + + return result; + } +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool dm_helpers_dp_write_dsc_enable( + struct dc_context *ctx, + const struct dc_stream_state *stream, +@@ -550,7 +549,6 @@ bool dm_helpers_dp_write_dsc_enable( + + return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1); + } +-#endif + + bool dm_helpers_is_dp_sink_present(struct dc_link *link) + { +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +index e42b162ee5d3..254123a02aa3 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +@@ -996,7 +996,6 @@ void dm_pp_get_funcs( + funcs->rv_funcs.set_hard_min_fclk_by_freq = + pp_rv_set_hard_min_fclk_by_freq; + break; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + case DCN_VERSION_2_0: + funcs->ctx.ver = PP_SMU_VER_NV; + funcs->nv_funcs.pp_smu.dm = ctx; +@@ -1019,7 +1018,6 @@ void dm_pp_get_funcs( + funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states; + funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support; + break; +-#endif + + #ifdef CONFIG_DRM_AMD_DC_DCN2_1 + case DCN_VERSION_2_1: +diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile +index 90482b158283..38ef29719400 100644 +--- a/drivers/gpu/drm/amd/display/dc/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/Makefile +@@ -25,18 +25,12 @@ + + DC_LIBS = basics bios calcs clk_mgr dce gpio irq virtual + +-ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++ifdef CONFIG_DRM_AMD_DC_DCN1_0 + DC_LIBS += dcn20 +-endif +- +- +-ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + DC_LIBS += dsc +-endif +- +-ifdef CONFIG_DRM_AMD_DC_DCN1_0 + DC_LIBS += dcn10 dml + endif ++ + ifdef CONFIG_DRM_AMD_DC_DCN2_1 + DC_LIBS += dcn21 + endif +@@ -59,7 +53,7 @@ include $(AMD_DC) + DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ + dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o + +-ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++ifdef CONFIG_DRM_AMD_DC_DCN1_0 + DISPLAY_CORE += dc_vm_helper.o + endif + +diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +index 03a5e82a7b2d..c70bfdca5d2f 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +@@ -1415,10 +1415,8 @@ static enum bp_result get_integrated_info_v11( + info->ma_channel_number = info_v11->umachannelnumber; + info->lvds_ss_percentage = + le16_to_cpu(info_v11->lvds_ss_percentage); +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + info->dp_ss_control = + le16_to_cpu(info_v11->reserved1); +-#endif + info->lvds_sspread_rate_in_10hz = + le16_to_cpu(info_v11->lvds_ss_rate_10hz); + info->hdmi_ss_percentage = +diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +index db153ddf0fee..45bb2bd81ba1 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +@@ -62,11 +62,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2( + return true; + #endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case DCN_VERSION_2_0: + *h = dal_cmd_tbl_helper_dce112_get_table2(); + return true; +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + case DCN_VERSION_2_1: + *h = dal_cmd_tbl_helper_dce112_get_table2(); +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index 9b2cb57bf2ba..a4ddd657598f 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -53,13 +53,9 @@ + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + /* Defaults from spreadsheet rev#247. + * RV2 delta: dram_clock_change_latency, max_num_dpp + */ +-#else +-/* Defaults from spreadsheet rev#247 */ +-#endif + const struct dcn_soc_bounding_box dcn10_soc_defaults = { + /* latencies */ + .sr_exit_time = 17, /*us*/ +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +index b864869cc7e3..9f15817a3eed 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +@@ -72,9 +72,7 @@ CLK_MGR_DCN10 = rv1_clk_mgr.o rv1_clk_mgr_vbios_smu.o rv2_clk_mgr.o + AMD_DAL_CLK_MGR_DCN10 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DCN10)) + + AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN10) +-endif + +-ifdef CONFIG_DRM_AMD_DC_DCN2_0 + ############################################################################### + # DCN20 + ############################################################################### +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +index 8af8fab14bcb..3d42bb4355f8 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +@@ -150,13 +150,11 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p + break; + } + break; +-#endif /* Family RV */ + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case FAMILY_NV: + dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + break; +-#endif /* Family NV */ ++#endif /* Family RV and NV*/ + + default: + ASSERT(0); /* Unknown Asic */ +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 81f4499490b9..121465bf223f 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -57,13 +57,9 @@ + #include "dc_link_dp.h" + #include "dc_dmub_srv.h" + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #include "dsc.h" +-#endif + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + #include "vm_helper.h" +-#endif + + #include "dce/dce_i2c.h" + +@@ -575,11 +571,9 @@ static void dc_destruct(struct dc *dc) + dc->dcn_ip = NULL; + + #endif +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + kfree(dc->vm_helper); + dc->vm_helper = NULL; + +-#endif + } + + static bool dc_construct(struct dc *dc, +@@ -596,11 +590,9 @@ static bool dc_construct(struct dc *dc, + enum dce_version dc_version = DCE_VERSION_UNKNOWN; + dc->config = init_params->flags; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + // Allocate memory for the vm_helper + dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL); + +-#endif + memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides)); + + dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL); +@@ -634,9 +626,7 @@ static bool dc_construct(struct dc *dc, + } + + dc->dcn_ip = dcn_ip; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + dc->soc_bounding_box = init_params->soc_bounding_box; +-#endif + #endif + + dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL); +@@ -738,7 +728,6 @@ static bool dc_construct(struct dc *dc, + return false; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + static bool disable_all_writeback_pipes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, +@@ -751,7 +740,6 @@ static bool disable_all_writeback_pipes_for_stream( + + return true; + } +-#endif + + static void disable_dangling_plane(struct dc *dc, struct dc_state *context) + { +@@ -777,16 +765,12 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) + } + if (should_disable && old_stream) { + dc_rem_all_planes_for_stream(dc, old_stream, dangling_context); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context); +-#endif + if (dc->hwss.apply_ctx_for_surface) + dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context); + } +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx) + dc->hwss.program_front_end_for_ctx(dc, dangling_context); +-#endif + } + + current_ctx = dc->current_state; +@@ -1176,10 +1160,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + context->stream_status[i].plane_count, + context); /* use new pipe config in new context */ + } +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx) + dc->hwss.program_front_end_for_ctx(dc, context); +-#endif + + /* Program hardware */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { +@@ -1198,10 +1180,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + } + + /* Program all planes within new context*/ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx) + dc->hwss.program_front_end_for_ctx(dc, context); +-#endif + for (i = 0; i < context->stream_count; i++) { + const struct dc_link *link = context->streams[i]->link; + +@@ -1685,10 +1665,8 @@ static enum surface_update_type check_update_surfaces_for_stream( + if (stream_update->gamut_remap) + su_flags->bits.gamut_remap = 1; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (stream_update->wb_update) + su_flags->bits.wb_update = 1; +-#endif + if (su_flags->raw != 0) + overall_type = UPDATE_TYPE_FULL; + +@@ -1851,7 +1829,6 @@ static void copy_surface_update_to_plane( + sizeof(struct dc_transfer_func_distributed_points)); + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (srf_update->func_shaper && + (surface->in_shaper_func != + srf_update->func_shaper)) +@@ -1874,7 +1851,6 @@ static void copy_surface_update_to_plane( + memcpy(surface->blend_tf, srf_update->blend_tf, + sizeof(*surface->blend_tf)); + +-#endif + if (srf_update->input_csc_color_matrix) + surface->input_csc_color_matrix = + *srf_update->input_csc_color_matrix; +@@ -1949,7 +1925,6 @@ static void copy_stream_update_to_stream(struct dc *dc, + + if (update->dither_option) + stream->dither_option = *update->dither_option; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* update current stream with writeback info */ + if (update->wb_update) { + int i; +@@ -1960,8 +1935,6 @@ static void copy_stream_update_to_stream(struct dc *dc, + stream->writeback_info[i] = + update->wb_update->writeback_info[i]; + } +-#endif +-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) + if (update->dsc_config) { + struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; + uint32_t old_dsc_enabled = stream->timing.flags.DSC; +@@ -1976,7 +1949,6 @@ static void copy_stream_update_to_stream(struct dc *dc, + stream->timing.flags.DSC = old_dsc_enabled; + } + } +-#endif + } + + static void commit_planes_do_stream_update(struct dc *dc, +@@ -2017,31 +1989,25 @@ static void commit_planes_do_stream_update(struct dc *dc, + dc_stream_program_csc_matrix(dc, stream); + + if (stream_update->dither_option) { +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; +-#endif + resource_build_bit_depth_reduction_params(pipe_ctx->stream, + &pipe_ctx->stream->bit_depth_params); + pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + while (odm_pipe) { + odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); + odm_pipe = odm_pipe->next_odm_pipe; + } +-#endif + } + +-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) + if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) { + dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true); + dp_update_dsc_config(pipe_ctx); + dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false); + } +-#endif + /* Full fe update*/ + if (update_type == UPDATE_TYPE_FAST) + continue; +@@ -2128,15 +2094,12 @@ static void commit_planes_for_stream(struct dc *dc, + */ + if (dc->hwss.apply_ctx_for_surface) + dc->hwss.apply_ctx_for_surface(dc, stream, 0, context); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx) + dc->hwss.program_front_end_for_ctx(dc, context); +-#endif + + return; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { + for (i = 0; i < surface_count; i++) { + struct dc_plane_state *plane_state = srf_updates[i].surface; +@@ -2158,7 +2121,6 @@ static void commit_planes_for_stream(struct dc *dc, + } + } + } +-#endif + + // Update Type FULL, Surface updates + for (j = 0; j < dc->res_pool->pipe_count; j++) { +@@ -2179,7 +2141,6 @@ static void commit_planes_for_stream(struct dc *dc, + if (update_type == UPDATE_TYPE_FAST) + continue; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); + + if (dc->hwss.program_triplebuffer != NULL && +@@ -2188,7 +2149,6 @@ static void commit_planes_for_stream(struct dc *dc, + dc->hwss.program_triplebuffer( + dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); + } +-#endif + stream_status = + stream_get_status(context, pipe_ctx->stream); + +@@ -2197,7 +2157,6 @@ static void commit_planes_for_stream(struct dc *dc, + dc, pipe_ctx->stream, stream_status->plane_count, context); + } + } +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) { + dc->hwss.program_front_end_for_ctx(dc, context); + #ifdef CONFIG_DRM_AMD_DC_DCN1_0 +@@ -2216,7 +2175,6 @@ static void commit_planes_for_stream(struct dc *dc, + } + #endif + } +-#endif + + // Update Type FAST, Surface updates + if (update_type == UPDATE_TYPE_FAST) { +@@ -2226,7 +2184,6 @@ static void commit_planes_for_stream(struct dc *dc, + */ + dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (dc->hwss.set_flip_control_gsl) + for (i = 0; i < surface_count; i++) { + struct dc_plane_state *plane_state = srf_updates[i].surface; +@@ -2245,7 +2202,6 @@ static void commit_planes_for_stream(struct dc *dc, + plane_state->flip_immediate); + } + } +-#endif + /* Perform requested Updates */ + for (i = 0; i < surface_count; i++) { + struct dc_plane_state *plane_state = srf_updates[i].surface; +@@ -2258,7 +2214,6 @@ static void commit_planes_for_stream(struct dc *dc, + + if (pipe_ctx->plane_state != plane_state) + continue; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /*program triple buffer after lock based on flip type*/ + if (dc->hwss.program_triplebuffer != NULL && + !dc->debug.disable_tri_buf) { +@@ -2266,7 +2221,6 @@ static void commit_planes_for_stream(struct dc *dc, + dc->hwss.program_triplebuffer( + dc, pipe_ctx, plane_state->triplebuffer_flips); + } +-#endif + if (srf_updates[i].flip_addr) + dc->hwss.update_plane_addr(dc, pipe_ctx); + } +@@ -2432,12 +2386,10 @@ void dc_set_power_state( + + dc->hwss.init_hw(dc); + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + if (dc->hwss.init_sys_ctx != NULL && + dc->vm_pa_config.valid) { + dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config); + } +-#endif + + break; + default: +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +index ec010dc0de8b..f27921e46937 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -1494,9 +1494,7 @@ static enum dc_status enable_link_dp( + struct dc_link *link = stream->link; + struct dc_link_settings link_settings = {0}; + enum dp_panel_mode panel_mode; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool fec_enable; +-#endif + int i; + bool apply_seamless_boot_optimization = false; + +@@ -1571,14 +1569,12 @@ static enum dc_status enable_link_dp( + else + status = DC_FAIL_DP_LINK_TRAINING; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (link->preferred_training_settings.fec_enable != NULL) + fec_enable = *link->preferred_training_settings.fec_enable; + else + fec_enable = true; + + dp_set_fec_enable(link, fec_enable); +-#endif + return status; + } + +@@ -2201,14 +2197,12 @@ static void disable_link(struct dc_link *link, enum signal_type signal) + dp_disable_link_phy(link, signal); + else + dp_disable_link_phy_mst(link, signal); +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + + if (dc_is_dp_sst_signal(signal) || + link->mst_stream_alloc_table.stream_count == 0) { + dp_set_fec_enable(link, false); + dp_set_fec_ready(link, false); + } +-#endif + } else { + if (signal != SIGNAL_TYPE_VIRTUAL) + link->link_enc->funcs->disable_output(link->link_enc, signal); +@@ -3015,23 +3009,19 @@ void core_link_enable_stream( + CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, + COLOR_DEPTH_UNDEFINED); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (pipe_ctx->stream->timing.flags.DSC) { + if (dc_is_dp_signal(pipe_ctx->stream->signal) || + dc_is_virtual_signal(pipe_ctx->stream->signal)) + dp_set_dsc_enable(pipe_ctx, true); + } +-#endif + core_dc->hwss.enable_stream(pipe_ctx); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* Set DPS PPS SDP (AKA "info frames") */ + if (pipe_ctx->stream->timing.flags.DSC) { + if (dc_is_dp_signal(pipe_ctx->stream->signal) || + dc_is_virtual_signal(pipe_ctx->stream->signal)) + dp_set_dsc_pps_sdp(pipe_ctx, true); + } +-#endif + + if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) + dc_link_allocate_mst_payload(pipe_ctx); +@@ -3045,14 +3035,12 @@ void core_link_enable_stream( + update_psp_stream_config(pipe_ctx, false); + #endif + } +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) + if (dc_is_dp_signal(pipe_ctx->stream->signal) || + dc_is_virtual_signal(pipe_ctx->stream->signal)) + dp_set_dsc_enable(pipe_ctx, true); + + } +-#endif + } + + void core_link_disable_stream(struct pipe_ctx *pipe_ctx) +@@ -3101,12 +3089,10 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) + core_dc->hwss.disable_stream(pipe_ctx); + + disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal); +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (pipe_ctx->stream->timing.flags.DSC) { + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + dp_set_dsc_enable(pipe_ctx, false); + } +-#endif + } + + void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) +@@ -3174,13 +3160,11 @@ uint32_t dc_bandwidth_in_kbps_from_timing( + uint32_t bits_per_channel = 0; + uint32_t kbps; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (timing->flags.DSC) { + kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); + kbps = kbps / 160 + ((kbps % 160) ? 1 : 0); + return kbps; + } +-#endif + + switch (timing->display_color_depth) { + case COLOR_DEPTH_666: +@@ -3358,7 +3342,6 @@ uint32_t dc_link_bandwidth_kbps( + link_bw_kbps *= 8; /* 8 bits per byte*/ + link_bw_kbps *= link_setting->lane_count; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { + /* Account for FEC overhead. + * We have to do it based on caps, +@@ -3383,7 +3366,6 @@ uint32_t dc_link_bandwidth_kbps( + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000, + link_bw_kbps, 32); + } +-#endif + + return link_bw_kbps; + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +index a32626864154..272261192e82 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +@@ -4,12 +4,8 @@ + #include "dc_link_dp.h" + #include "dm_helpers.h" + #include "opp.h" +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #include "dsc.h" +-#endif +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "resource.h" +-#endif + + #include "inc/core_types.h" + #include "link_hwss.h" +@@ -1365,9 +1361,7 @@ enum link_training_result dc_link_dp_perform_link_training( + enum link_training_result status = LINK_TRAINING_SUCCESS; + struct link_training_settings lt_settings; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool fec_enable; +-#endif + uint8_t repeater_cnt; + uint8_t repeater_id; + +@@ -1380,14 +1374,12 @@ enum link_training_result dc_link_dp_perform_link_training( + /* 1. set link rate, lane count and spread. */ + dpcd_set_link_settings(link, <_settings); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (link->preferred_training_settings.fec_enable != NULL) + fec_enable = *link->preferred_training_settings.fec_enable; + else + fec_enable = true; + + dp_set_fec_ready(link, fec_enable); +-#endif + + if (!link->is_lttpr_mode_transparent) { + /* Configure lttpr mode */ +@@ -1529,9 +1521,7 @@ enum link_training_result dc_link_dp_sync_lt_attempt( + enum link_training_result lt_status = LINK_TRAINING_SUCCESS; + enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT; + enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool fec_enable = false; +-#endif + + initialize_training_settings( + link, +@@ -1551,11 +1541,9 @@ enum link_training_result dc_link_dp_sync_lt_attempt( + dp_enable_link_phy(link, link->connector_signal, + dp_cs_id, link_settings); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* Set FEC enable */ + fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable; + dp_set_fec_ready(link, fec_enable); +-#endif + + if (lt_overrides->alternate_scrambler_reset) { + if (*lt_overrides->alternate_scrambler_reset) +@@ -1596,9 +1584,7 @@ bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down) + */ + if (link_down == true) { + dp_disable_link_phy(link, link->connector_signal); +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + dp_set_fec_ready(link, false); +-#endif + } + + link->sync_lt_in_progress = false; +@@ -3306,7 +3292,6 @@ static bool retrieve_link_cap(struct dc_link *link) + dp_hw_fw_revision.ieee_fw_rev, + sizeof(dp_hw_fw_revision.ieee_fw_rev)); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + memset(&link->dpcd_caps.dsc_caps, '\0', + sizeof(link->dpcd_caps.dsc_caps)); + memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); +@@ -3328,7 +3313,6 @@ static bool retrieve_link_cap(struct dc_link *link) + link->dpcd_caps.dsc_caps.dsc_ext_caps.raw, + sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw)); + } +-#endif + + /* Connectivity log: detection */ + CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); +@@ -3458,14 +3442,12 @@ static void set_crtc_test_pattern(struct dc_link *link, + stream->timing.display_color_depth; + struct bit_depth_reduction_params params; + struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + int width = pipe_ctx->stream->timing.h_addressable + + pipe_ctx->stream->timing.h_border_left + + pipe_ctx->stream->timing.h_border_right; + int height = pipe_ctx->stream->timing.v_addressable + + pipe_ctx->stream->timing.v_border_bottom + + pipe_ctx->stream->timing.v_border_top; +-#endif + + memset(¶ms, 0, sizeof(params)); + +@@ -3509,7 +3491,6 @@ static void set_crtc_test_pattern(struct dc_link *link, + if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) + pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, + controller_test_pattern, color_depth); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + else if (opp->funcs->opp_set_disp_pattern_generator) { + struct pipe_ctx *odm_pipe; + enum controller_dp_color_space controller_color_space; +@@ -3558,7 +3539,6 @@ static void set_crtc_test_pattern(struct dc_link *link, + width, + height); + } +-#endif + } + break; + case DP_TEST_PATTERN_VIDEO_MODE: +@@ -3571,7 +3551,6 @@ static void set_crtc_test_pattern(struct dc_link *link, + pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, + CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, + color_depth); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + else if (opp->funcs->opp_set_disp_pattern_generator) { + struct pipe_ctx *odm_pipe; + int opp_cnt = 1; +@@ -3600,7 +3579,6 @@ static void set_crtc_test_pattern(struct dc_link *link, + width, + height); + } +-#endif + } + break; + +@@ -3876,7 +3854,6 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) + return DP_PANEL_MODE_DEFAULT; + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + void dp_set_fec_ready(struct dc_link *link, bool ready) + { + /* FEC has to be "set ready" before the link training. +@@ -3939,5 +3916,4 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) + } + } + } +-#endif + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +index 5efbdc1eb173..bb1e8e5b5252 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +@@ -12,12 +12,8 @@ + #include "dc_link_ddc.h" + #include "dm_helpers.h" + #include "dpcd_defs.h" +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #include "dsc.h" +-#endif +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "resource.h" +-#endif + + static uint8_t convert_to_count(uint8_t lttpr_repeater_count) + { +@@ -374,7 +370,6 @@ void dp_retrain_link_dp_test(struct dc_link *link, + } + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #define DC_LOGGER \ + dsc->ctx->logger + static void dsc_optc_config_log(struct display_stream_compressor *dsc, +@@ -572,5 +567,4 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx) + dp_set_dsc_pps_sdp(pipe_ctx, true); + return true; + } +-#endif + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index 2acfaa9a24cd..081275a430ad 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -46,9 +46,7 @@ + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "dcn10/dcn10_resource.h" + #endif +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "dcn20/dcn20_resource.h" +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + #include "dcn21/dcn21_resource.h" + #endif +@@ -108,11 +106,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) + break; + #endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case FAMILY_NV: + dc_version = DCN_VERSION_2_0; + break; +-#endif + default: + dc_version = DCE_VERSION_UNKNOWN; + break; +@@ -164,18 +160,16 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, + case DCN_VERSION_1_01: + res_pool = dcn10_create_resource_pool(init_data, dc); + break; +-#endif + + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case DCN_VERSION_2_0: + res_pool = dcn20_create_resource_pool(init_data, dc); + break; +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + case DCN_VERSION_2_1: + res_pool = dcn21_create_resource_pool(init_data, dc); + break; ++#endif + #endif + + default: +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +index ae7cbb6d7847..59eaa5c172a9 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +@@ -105,7 +105,6 @@ static void dc_stream_construct(struct dc_stream_state *stream, + /* EDID CAP translation for HDMI 2.0 */ + stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); + stream->timing.dsc_cfg.num_slices_h = 0; + stream->timing.dsc_cfg.num_slices_v = 0; +@@ -114,7 +113,6 @@ static void dc_stream_construct(struct dc_stream_state *stream, + stream->timing.dsc_cfg.linebuf_depth = 9; + stream->timing.dsc_cfg.version_minor = 2; + stream->timing.dsc_cfg.ycbcr422_simple = 0; +-#endif + + update_stream_signal(stream, dc_sink_data); + +@@ -364,7 +362,6 @@ bool dc_stream_set_cursor_position( + return true; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool dc_stream_add_writeback(struct dc *dc, + struct dc_stream_state *stream, + struct dc_writeback_info *wb_info) +@@ -477,7 +474,6 @@ bool dc_stream_remove_writeback(struct dc *dc, + + return true; + } +-#endif + + uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) + { +@@ -564,7 +560,6 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, + return ret; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) + { + struct pipe_ctx *pipe = NULL; +@@ -625,7 +620,6 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, + + return true; + } +-#endif + + void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) + { +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +index d534ac166512..5904c459fe8f 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +@@ -48,7 +48,6 @@ static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *pl + plane_state->in_transfer_func->type = TF_TYPE_BYPASS; + plane_state->in_transfer_func->ctx = ctx; + } +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + plane_state->in_shaper_func = dc_create_transfer_func(); + if (plane_state->in_shaper_func != NULL) { + plane_state->in_shaper_func->type = TF_TYPE_BYPASS; +@@ -65,7 +64,6 @@ static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *pl + plane_state->blend_tf->ctx = ctx; + } + +-#endif + } + + static void dc_plane_destruct(struct dc_plane_state *plane_state) +@@ -78,7 +76,6 @@ static void dc_plane_destruct(struct dc_plane_state *plane_state) + plane_state->in_transfer_func); + plane_state->in_transfer_func = NULL; + } +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (plane_state->in_shaper_func != NULL) { + dc_transfer_func_release( + plane_state->in_shaper_func); +@@ -95,7 +92,6 @@ static void dc_plane_destruct(struct dc_plane_state *plane_state) + plane_state->blend_tf = NULL; + } + +-#endif + } + + /******************************************************************************* +@@ -260,7 +256,6 @@ struct dc_transfer_func *dc_create_transfer_func(void) + return NULL; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + static void dc_3dlut_func_free(struct kref *kref) + { + struct dc_3dlut *lut = container_of(kref, struct dc_3dlut, refcount); +@@ -294,6 +289,5 @@ void dc_3dlut_func_retain(struct dc_3dlut *lut) + { + kref_get(&lut->refcount); + } +-#endif + + +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 18fdd61a606b..d710e123b53a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -113,17 +113,13 @@ struct dc_caps { + bool psp_setup_panel_mode; + bool extended_aux_timeout_support; + bool dmcub_support; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + bool hw_3d_lut; +-#endif + struct dc_plane_cap planes[MAX_PLANES]; + }; + + struct dc_bug_wa { +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool no_connect_phy_config; + bool dedcn20_305_wa; +-#endif + bool skip_clock_update; + }; + +@@ -364,10 +360,8 @@ struct dc_debug_options { + bool disable_dfs_bypass; + bool disable_dpp_power_gate; + bool disable_hubp_power_gate; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool disable_dsc_power_gate; + int dsc_min_slice_height_override; +-#endif + bool native422_support; + bool disable_pplib_wm_range; + enum wm_report_mode pplib_wm_report_mode; +@@ -407,9 +401,7 @@ struct dc_debug_options { + bool dmcub_emulation; + bool dmub_command_table; /* for testing only */ + struct dc_bw_validation_profile bw_val_profile; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool disable_fec; +-#endif + #ifdef CONFIG_DRM_AMD_DC_DCN2_1 + bool disable_48mhz_pwrdwn; + #endif +@@ -418,9 +410,7 @@ struct dc_debug_options { + */ + unsigned int force_min_dcfclk_mhz; + bool disable_timing_sync; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool cm_in_bypass; +-#endif + int force_clock_mode;/*every mode change.*/ + + bool nv12_iflip_vm_wa; +@@ -434,7 +424,6 @@ struct dc_debug_data { + uint32_t auxErrorCount; + }; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct dc_phy_addr_space_config { + struct { + uint64_t start_addr; +@@ -464,7 +453,6 @@ struct dc_virtual_addr_space_config { + uint32_t page_table_block_size_in_bytes; + uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid + }; +-#endif + + struct dc_bounding_box_overrides { + int sr_exit_time_ns; +@@ -492,9 +480,7 @@ struct dc { + struct dc_bounding_box_overrides bb_overrides; + struct dc_bug_wa work_arounds; + struct dc_context *ctx; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct dc_phy_addr_space_config vm_pa_config; +-#endif + + uint8_t link_count; + struct dc_link *links[MAX_PIPES * 2]; +@@ -532,10 +518,8 @@ struct dc { + struct dc_debug_data debug_data; + + const char *build_id; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct vm_helper *vm_helper; + const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; +-#endif + }; + + enum frame_buffer_mode { +@@ -572,13 +556,11 @@ struct dc_init_data { + + struct dc_config flags; + uint32_t log_mask; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + /** + * gpu_info FW provided soc bounding box struct or 0 if not + * available in FW + */ + const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; +-#endif + }; + + struct dc_callback_init { +@@ -593,11 +575,9 @@ struct dc *dc_create(const struct dc_init_data *init_params); + void dc_hardware_init(struct dc *dc); + + int dc_get_vmid_use_vector(struct dc *dc); +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); + /* Returns the number of vmids supported */ + int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); +-#endif + void dc_init_callbacks(struct dc *dc, + const struct dc_callback_init *init_params); + void dc_deinit_callbacks(struct dc *dc); +@@ -673,7 +653,6 @@ struct dc_transfer_func { + }; + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + union dc_3dlut_state { + struct { +@@ -697,7 +676,6 @@ struct dc_3dlut { + union dc_3dlut_state state; + struct dc_context *ctx; + }; +-#endif + /* + * This structure is filled in by dc_surface_get_status and contains + * the last requested address and the currently active address so the called +@@ -748,9 +726,7 @@ union surface_update_flags { + struct dc_plane_state { + struct dc_plane_address address; + struct dc_plane_flip_time time; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool triplebuffer_flips; +-#endif + struct scaling_taps scaling_quality; + struct rect src_rect; + struct rect dst_rect; +@@ -773,11 +749,9 @@ struct dc_plane_state { + + enum dc_color_space color_space; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_3dlut *lut3d_func; + struct dc_transfer_func *in_shaper_func; + struct dc_transfer_func *blend_tf; +-#endif + + enum surface_pixel_format format; + enum dc_rotation_angle rotation; +@@ -845,11 +819,9 @@ struct dc_surface_update { + + const struct dc_csc_transform *input_csc_color_matrix; + const struct fixed31_32 *coeff_reduction_factor; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + const struct dc_transfer_func *func_shaper; + const struct dc_3dlut *lut3d_func; + const struct dc_transfer_func *blend_tf; +-#endif + }; + + /* +@@ -870,11 +842,9 @@ void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); + void dc_transfer_func_release(struct dc_transfer_func *dc_tf); + struct dc_transfer_func *dc_create_transfer_func(void); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_3dlut *dc_create_3dlut_func(void); + void dc_3dlut_func_release(struct dc_3dlut *lut); + void dc_3dlut_func_retain(struct dc_3dlut *lut); +-#endif + /* + * This structure holds a surface address. There could be multiple addresses + * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such +@@ -991,10 +961,8 @@ struct dpcd_caps { + bool panel_mode_edp; + bool dpcd_display_control_capable; + bool ext_receiver_cap_field_present; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + union dpcd_fec_capability fec_cap; + struct dpcd_dsc_capabilities dsc_caps; +-#endif + struct dc_lttpr_caps lttpr_caps; + + }; +@@ -1017,14 +985,12 @@ struct dc_container_id { + }; + + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct dc_sink_dsc_caps { + // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), + // 'false' if they are sink's DSC caps + bool is_virtual_dpcd_dsc; + struct dsc_dec_dpcd_caps dsc_dec_caps; + }; +-#endif + + /* + * The sink structure contains EDID and other display device properties +@@ -1039,9 +1005,7 @@ struct dc_sink { + struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; + bool converter_disable_audio; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct dc_sink_dsc_caps sink_dsc_caps; +-#endif + + /* private to DC core */ + struct dc_link *link; +@@ -1102,10 +1066,8 @@ bool dc_is_dmcu_initialized(struct dc *dc); + + enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); + void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); +-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) + /******************************************************************************* + * DSC Interfaces + ******************************************************************************/ + #include "dc_dsc.h" +-#endif + #endif /* DC_INTERFACE_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +index 28234d8fdb2c..dfe4472c9e40 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +@@ -129,9 +129,7 @@ struct dc_link_training_overrides { + bool *alternate_scrambler_reset; + bool *enhanced_framing; + bool *mst_enable; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool *fec_enable; +-#endif + }; + + union dpcd_rev { +@@ -570,7 +568,6 @@ struct dp_audio_test_data { + uint8_t pattern_period[8]; + }; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* FEC capability DPCD register field bits-*/ + union dpcd_fec_capability { + struct { +@@ -695,6 +692,5 @@ struct dpcd_dsc_capabilities { + union dpcd_dsc_ext_capabilities dsc_ext_caps; + }; + +-#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ + + #endif /* DC_DP_TYPES_H */ +diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h +index 0ed2962add5a..a782ae18a1c5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h +@@ -1,4 +1,3 @@ +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #ifndef DC_DSC_H_ + #define DC_DSC_H_ + /* +@@ -69,4 +68,3 @@ bool dc_dsc_compute_config( + const struct dc_crtc_timing *timing, + struct dc_dsc_config *dsc_cfg); + #endif +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +index e0856bb8511f..86043d431d40 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +@@ -167,12 +167,10 @@ enum surface_pixel_format { + /*swaped & float*/ + SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, + /*grow graphics here if necessary */ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, + SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, + SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, + SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, +-#endif + SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, + SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = + SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, +@@ -180,10 +178,8 @@ enum surface_pixel_format { + SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, + SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, + SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, + SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, +-#endif + SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, + SURFACE_PIXEL_FORMAT_INVALID + +@@ -222,12 +218,10 @@ enum tile_split_values { + DC_ROTATED_MICRO_TILING = 0x3, + }; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + enum tripleBuffer_enable { + DC_TRIPLEBUFFER_DISABLE = 0x0, + DC_TRIPLEBUFFER_ENABLE = 0x1, + }; +-#endif + + /* TODO: These values come from hardware spec. We need to readdress this + * if they ever change. +@@ -427,13 +421,11 @@ struct dc_csc_transform { + bool enable_adjustment; + }; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct dc_rgb_fixed { + struct fixed31_32 red; + struct fixed31_32 green; + struct fixed31_32 blue; + }; +-#endif + + struct dc_gamma { + struct kref refcount; +@@ -468,10 +460,8 @@ enum dc_cursor_color_format { + CURSOR_MODE_COLOR_1BIT_AND, + CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA, + CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA, +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED, + CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED +-#endif + }; + + /* +@@ -626,10 +616,8 @@ enum dc_color_depth { + COLOR_DEPTH_121212, + COLOR_DEPTH_141414, + COLOR_DEPTH_161616, +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + COLOR_DEPTH_999, + COLOR_DEPTH_111111, +-#endif + COLOR_DEPTH_COUNT + }; + +@@ -690,9 +678,7 @@ struct dc_crtc_timing_flags { + * rates less than or equal to 340Mcsc */ + uint32_t LTE_340MCSC_SCRAMBLE:1; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + uint32_t DSC : 1; /* Use DSC with this timing */ +-#endif + }; + + enum dc_timing_3d_format { +@@ -717,7 +703,6 @@ enum dc_timing_3d_format { + TIMING_3D_FORMAT_MAX, + }; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct dc_dsc_config { + uint32_t num_slices_h; /* Number of DSC slices - horizontal */ + uint32_t num_slices_v; /* Number of DSC slices - vertical */ +@@ -728,7 +713,6 @@ struct dc_dsc_config { + bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ + int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ + }; +-#endif + struct dc_crtc_timing { + uint32_t h_total; + uint32_t h_border_left; +@@ -755,9 +739,7 @@ struct dc_crtc_timing { + enum scanning_type scan_type; + + struct dc_crtc_timing_flags flags; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct dc_dsc_config dsc_cfg; +-#endif + }; + + #ifndef AMD_EDID_UTILITY +@@ -796,7 +778,6 @@ enum vram_type { + VIDEO_MEMORY_TYPE_GDDR6 = 6, + }; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + enum dwb_cnv_out_bpc { + DWB_CNV_OUT_BPC_8BPC = 0, + DWB_CNV_OUT_BPC_10BPC = 1, +@@ -847,7 +828,6 @@ struct mcif_buf_params { + unsigned int swlock; + }; + +-#endif + + #define MAX_TG_COLOR_VALUE 0x3FF + struct tg_color { +diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h +index 03efdc1a7b03..1ff79f703734 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_link.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h +@@ -29,13 +29,11 @@ + #include "dc_types.h" + #include "grph_object_defs.h" + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + enum dc_link_fec_state { + dc_link_fec_not_ready, + dc_link_fec_ready, + dc_link_fec_enabled + }; +-#endif + struct dc_link_status { + bool link_active; + struct dpcd_caps *dpcd_caps; +@@ -142,9 +140,7 @@ struct dc_link { + + struct link_trace link_trace; + struct gpio *hpd_gpio; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + enum dc_link_fec_state fec_state; +-#endif + }; + + const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); +diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h +index 70274fc43a72..3ea54321b045 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h +@@ -52,7 +52,6 @@ struct freesync_context { + bool dummy; + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + enum hubp_dmdata_mode { + DMDATA_SW_MODE, + DMDATA_HW_MODE +@@ -82,9 +81,7 @@ struct dc_dmdata_attributes { + /* An unbounded array of uint32s, represents software dmdata to be loaded */ + uint32_t *dmdata_sw_data; + }; +-#endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_writeback_info { + bool wb_enabled; + int dwb_pipe_inst; +@@ -96,7 +93,6 @@ struct dc_writeback_update { + unsigned int num_wb_info; + struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; + }; +-#endif + + enum vertical_interrupt_ref_point { + START_V_UPDATE = 0, +@@ -121,9 +117,7 @@ union stream_update_flags { + uint32_t abm_level:1; + uint32_t dpms_off:1; + uint32_t gamut_remap:1; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + uint32_t wb_update:1; +-#endif + } bits; + + uint32_t raw; +@@ -204,11 +198,9 @@ struct dc_stream_state { + + struct crtc_trigger_info triggered_crtc_reset; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* writeback */ + unsigned int num_wb_info; + struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; +-#endif + /* Computed state bits */ + bool mode_changed : 1; + +@@ -227,9 +219,7 @@ struct dc_stream_state { + bool apply_seamless_boot_optimization; + + uint32_t stream_id; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool is_dsc_enabled; +-#endif + union stream_update_flags update_flags; + }; + +@@ -260,12 +250,8 @@ struct dc_stream_update { + + struct dc_csc_transform *output_csc_transform; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_writeback_update *wb_update; +-#endif +-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) + struct dc_dsc_config *dsc_config; +-#endif + }; + + bool dc_is_stream_unchanged( +@@ -355,7 +341,6 @@ bool dc_add_all_planes_for_stream( + int plane_count, + struct dc_state *context); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool dc_stream_add_writeback(struct dc *dc, + struct dc_stream_state *stream, + struct dc_writeback_info *wb_info); +@@ -366,7 +351,6 @@ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) + bool dc_stream_set_dynamic_metadata(struct dc *dc, + struct dc_stream_state *stream, + struct dc_dmdata_attributes *dmdata_attr); +-#endif + + enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); + +diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h +index 45dfed8bcaf7..1363e8907fbf 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h +@@ -468,7 +468,6 @@ enum display_content_type { + DISPLAY_CONTENT_TYPE_GAME = 8 + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* writeback */ + struct dwb_stereo_params { + bool stereo_enabled; /* false: normal mode, true: 3D stereo */ +@@ -499,7 +498,6 @@ struct dc_dwb_params { + enum dwb_subsample_position subsample_position; + struct dc_transfer_func *out_transfer_func; + }; +-#endif + + /* audio*/ + +@@ -607,9 +605,7 @@ enum dc_infoframe_type { + DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, + DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, + DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + DC_DP_INFOFRAME_TYPE_PPS = 0x10, +-#endif + }; + + struct dc_info_packet { +@@ -788,7 +784,6 @@ struct dc_clock_config { + #endif /*AMD_EDID_UTILITY*/ + //AMD EDID UTILITY does not need any of the above structures + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* DSC DPCD capabilities */ + union dsc_slice_caps1 { + struct { +@@ -858,6 +853,5 @@ struct dsc_dec_dpcd_caps { + uint32_t branch_overall_throughput_1_mps; /* In MPs */ + uint32_t branch_max_line_width; + }; +-#endif + + #endif /* DC_TYPES_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +index 7ba7e6f722f6..ba0caaffa24b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +@@ -67,7 +67,6 @@ + SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ + NBIO_SR(BIOS_SCRATCH_2) + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define ABM_DCN20_REG_LIST() \ + ABM_COMMON_REG_LIST_DCE_BASE(), \ + SR(DC_ABM1_HG_SAMPLE_RATE), \ +@@ -81,7 +80,6 @@ + SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ + SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ + NBIO_SR(BIOS_SCRATCH_2) +-#endif + + #define ABM_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix +@@ -163,9 +161,7 @@ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) +-#endif + + #define ABM_REG_FIELD_LIST(type) \ + type ABM1_HG_NUM_OF_BINS_SEL; \ +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +index 2e2e925a506b..382465862f29 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +@@ -30,7 +30,6 @@ + #include "inc/hw/aux_engine.h" + + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + #define AUX_COMMON_REG_LIST0(id)\ + SRI(AUX_CONTROL, DP_AUX, id), \ + SRI(AUX_ARB_CONTROL, DP_AUX, id), \ +@@ -39,7 +38,6 @@ + SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ + SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \ + SRI(AUX_SW_STATUS, DP_AUX, id) +-#endif + + #define AUX_COMMON_REG_LIST(id)\ + SRI(AUX_CONTROL, DP_AUX, id), \ +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +index accae1089b83..24ad0b4dddb6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +@@ -1002,7 +1002,6 @@ static bool get_pixel_clk_frequency_100hz( + return false; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ + struct pixel_rate_range_table_entry { +@@ -1062,7 +1061,6 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = { + .get_pix_clk_dividers = dce112_get_pix_clk_dividers, + .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz + }; +-#endif + + /*****************************************/ + /* Constructor */ +@@ -1433,7 +1431,6 @@ bool dce112_clk_src_construct( + return true; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool dcn20_clk_src_construct( + struct dce110_clk_src *clk_src, + struct dc_context *ctx, +@@ -1449,4 +1446,3 @@ bool dcn20_clk_src_construct( + + return ret; + } +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +index 43c1bf60b83c..5b4a29ee1696 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +@@ -55,7 +55,6 @@ + CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ + CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \ + SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ + SRII(PHASE, DP_DTO, 0),\ +@@ -76,7 +75,6 @@ + SRII(PIXEL_RATE_CNTL, OTG, 3),\ + SRII(PIXEL_RATE_CNTL, OTG, 4),\ + SRII(PIXEL_RATE_CNTL, OTG, 5) +-#endif + + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ +@@ -95,13 +93,11 @@ + SRII(PIXEL_RATE_CNTL, OTG, 3) + #endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ + CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ + CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ + CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ + CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) +-#endif + + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + +@@ -201,7 +197,6 @@ bool dce112_clk_src_construct( + const struct dce110_clk_src_shift *cs_shift, + const struct dce110_clk_src_mask *cs_mask); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool dcn20_clk_src_construct( + struct dce110_clk_src *clk_src, + struct dc_context *ctx, +@@ -210,6 +205,5 @@ bool dcn20_clk_src_construct( + const struct dce110_clk_src_regs *regs, + const struct dce110_clk_src_shift *cs_shift, + const struct dce110_clk_src_mask *cs_mask); +-#endif + + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +index da9a07edcb06..6e23a82afe8b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +@@ -745,9 +745,7 @@ static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) + return true; + } + +-#endif //(CONFIG_DRM_AMD_DC_DCN1_0) + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + static bool dcn20_lock_phy(struct dmcu *dmcu) + { +@@ -795,7 +793,7 @@ static bool dcn20_unlock_phy(struct dmcu *dmcu) + return true; + } + +-#endif //(CONFIG_DRM_AMD_DC_DCN2_0) ++#endif //(CONFIG_DRM_AMD_DC_DCN1_0) + + static const struct dmcu_funcs dce_funcs = { + .dmcu_init = dce_dmcu_init, +@@ -819,9 +817,7 @@ static const struct dmcu_funcs dcn10_funcs = { + .get_psr_wait_loop = dcn10_get_psr_wait_loop, + .is_dmcu_initialized = dcn10_is_dmcu_initialized + }; +-#endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + static const struct dmcu_funcs dcn20_funcs = { + .dmcu_init = dcn10_dmcu_init, + .load_iram = dcn10_dmcu_load_iram, +@@ -834,7 +830,6 @@ static const struct dmcu_funcs dcn20_funcs = { + .lock_phy = dcn20_lock_phy, + .unlock_phy = dcn20_unlock_phy + }; +-#endif + + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + static const struct dmcu_funcs dcn21_funcs = { +@@ -850,6 +845,7 @@ static const struct dmcu_funcs dcn21_funcs = { + .unlock_phy = dcn20_unlock_phy + }; + #endif ++#endif + + static void dce_dmcu_construct( + struct dce_dmcu *dmcu_dce, +@@ -869,7 +865,7 @@ static void dce_dmcu_construct( + dmcu_dce->dmcu_mask = dmcu_mask; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + static void dcn21_dmcu_construct( + struct dce_dmcu *dmcu_dce, + struct dc_context *ctx, +@@ -931,9 +927,7 @@ struct dmcu *dcn10_dmcu_create( + + return &dmcu_dce->base; + } +-#endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dmcu *dcn20_dmcu_create( + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, +@@ -954,7 +948,6 @@ struct dmcu *dcn20_dmcu_create( + + return &dmcu_dce->base; + } +-#endif + + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + struct dmcu *dcn21_dmcu_create( +@@ -978,6 +971,7 @@ struct dmcu *dcn21_dmcu_create( + return &dmcu_dce->base; + } + #endif ++#endif + + void dce_dmcu_destroy(struct dmcu **dmcu) + { +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +index 1a42b2cbb21b..89277899b507 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +@@ -266,13 +266,11 @@ struct dmcu *dcn10_dmcu_create( + const struct dce_dmcu_shift *dmcu_shift, + const struct dce_dmcu_mask *dmcu_mask); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dmcu *dcn20_dmcu_create( + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, + const struct dce_dmcu_shift *dmcu_shift, + const struct dce_dmcu_mask *dmcu_mask); +-#endif + + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + struct dmcu *dcn21_dmcu_create( +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index a0d1c3b811a9..7e3dde764111 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -210,7 +210,6 @@ + SR(DC_IP_REQUEST_CNTL), \ + BL_REG_LIST() + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define HWSEQ_DCN2_REG_LIST()\ + HWSEQ_DCN_REG_LIST(), \ + HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ +@@ -276,7 +275,6 @@ + SR(D6VGA_CONTROL), \ + SR(DC_IP_REQUEST_CNTL), \ + BL_REG_LIST() +-#endif + + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + #define HWSEQ_DCN21_REG_LIST()\ +@@ -577,7 +575,6 @@ struct dce_hwseq_registers { + HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ + HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ + HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ +@@ -637,7 +634,6 @@ struct dce_hwseq_registers { + HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ + HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) +-#endif + + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +index 0495a1b5dd74..f4c1ce4f4e6a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +@@ -293,9 +293,7 @@ static bool setup_engine( + struct dce_i2c_hw *dce_i2c_hw) + { + uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + uint32_t reset_length = 0; +-#endif + /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/ + REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1); + +@@ -319,14 +317,12 @@ static bool setup_engine( + REG_UPDATE_N(SETUP, 2, + FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit, + FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + } else { + reset_length = dce_i2c_hw->send_reset_length; + REG_UPDATE_N(SETUP, 3, + FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit, + FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length, + FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1); +-#endif + } + /* Program HW priority + * set to High - interrupt software I2C at any time +@@ -702,7 +698,6 @@ void dcn1_i2c_hw_construct( + dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void dcn2_i2c_hw_construct( + struct dce_i2c_hw *dce_i2c_hw, + struct dc_context *ctx, +@@ -721,4 +716,3 @@ void dcn2_i2c_hw_construct( + if (ctx->dc->debug.scl_reset_length10) + dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10; + } +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h +index cb0234e5d597..d4b2037f7d74 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h +@@ -177,9 +177,7 @@ struct dce_i2c_shift { + uint8_t DC_I2C_INDEX; + uint8_t DC_I2C_INDEX_WRITE; + uint8_t XTAL_REF_DIV; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH; +-#endif + uint8_t DC_I2C_REG_RW_CNTL_STATUS; + }; + +@@ -220,17 +218,13 @@ struct dce_i2c_mask { + uint32_t DC_I2C_INDEX; + uint32_t DC_I2C_INDEX_WRITE; + uint32_t XTAL_REF_DIV; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH; +-#endif + uint32_t DC_I2C_REG_RW_CNTL_STATUS; + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\ + I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\ + I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh) +-#endif + + struct dce_i2c_registers { + uint32_t SETUP; +@@ -312,7 +306,6 @@ void dcn1_i2c_hw_construct( + const struct dce_i2c_shift *shifts, + const struct dce_i2c_mask *masks); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void dcn2_i2c_hw_construct( + struct dce_i2c_hw *dce_i2c_hw, + struct dc_context *ctx, +@@ -320,7 +313,6 @@ void dcn2_i2c_hw_construct( + const struct dce_i2c_registers *regs, + const struct dce_i2c_shift *shifts, + const struct dce_i2c_mask *masks); +-#endif + + bool dce_i2c_submit_command_hw( + struct resource_pool *pool, +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 050634926263..01fefe19ee92 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1319,9 +1319,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( + struct dc_stream_state *stream = pipe_ctx->stream; + struct drr_params params = {0}; + unsigned int event_triggers = 0; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; +-#endif + + if (dc->hwss.disable_stream_gating) { + dc->hwss.disable_stream_gating(dc, pipe_ctx); +@@ -1387,7 +1385,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( + pipe_ctx->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + while (odm_pipe) { + odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( + odm_pipe->stream_res.opp, +@@ -1401,7 +1398,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( + &stream->clamping); + odm_pipe = odm_pipe->next_odm_pipe; + } +-#endif + + if (!stream->dpms_off) + core_link_enable_stream(context, pipe_ctx); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +index 997e9582edc7..0e682b5aa3eb 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +@@ -290,12 +290,8 @@ void dpp1_cnv_setup ( + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + enum dc_color_space input_color_space, + struct cnv_alpha_2bit_lut *alpha_2bit_lut) +-#else +- enum dc_color_space input_color_space) +-#endif + { + uint32_t pixel_format; + uint32_t alpha_en; +@@ -542,11 +538,9 @@ static const struct dpp_funcs dcn10_dpp_funcs = { + .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, + .dpp_dppclk_control = dpp1_dppclk_control, + .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier, +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + .dpp_program_blnd_lut = NULL, + .dpp_program_shaper_lut = NULL, + .dpp_program_3dlut = NULL +-#endif + }; + + static struct dpp_caps dcn10_dpp_cap = { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +index 1d4a7d640334..2edf566b3a72 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +@@ -1486,12 +1486,8 @@ void dpp1_cnv_setup ( + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + enum dc_color_space input_color_space, + struct cnv_alpha_2bit_lut *alpha_2bit_lut); +-#else +- enum dc_color_space input_color_space); +-#endif + + void dpp1_full_bypass(struct dpp *dpp_base); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +index 6f1a312c6a5a..6b7593dd0c77 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +@@ -736,10 +736,8 @@ void dpp1_full_bypass(struct dpp *dpp_base) + /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */ + if (dpp->tf_mask->CM_BYPASS_EN) + REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + else + REG_SET(CM_CONTROL, 0, CM_BYPASS, 1); +-#endif + + /* Setting degamma bypass for now */ + REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +index d67e0abeee93..fce37c527a0b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +@@ -218,14 +218,12 @@ static void dpp1_dscl_set_lb( + INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ + LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ + } +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + else { + /* DSCL caps: pixel data processed in float format */ + REG_SET_2(LB_DATA_FORMAT, 0, + INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ + LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ + } +-#endif + + REG_SET_2(LB_MEMORY_CTRL, 0, + MEMORY_CONFIG, mem_size_config, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c +index 374cc9acda3b..64b31edc8cf6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c +@@ -109,9 +109,7 @@ const struct dwbc_funcs dcn10_dwbc_funcs = { + .update = NULL, + .set_stereo = NULL, + .set_new_content = NULL, +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + .set_warmup = NULL, +-#endif + .dwb_set_scaler = NULL, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +index 5aeee938605a..31b64733d693 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +@@ -306,7 +306,6 @@ void hubp1_program_pixel_format( + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 12); + break; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 112); +@@ -327,7 +326,6 @@ void hubp1_program_pixel_format( + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 119); + break; +-#endif + default: + BREAK_TO_DEBUGGER(); + break; +@@ -1251,10 +1249,8 @@ static const struct hubp_funcs dcn10_hubp_funcs = { + .hubp_get_underflow_status = hubp1_get_underflow_status, + .hubp_init = hubp1_init, + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + .dmdata_set_attributes = NULL, + .dmdata_load = NULL, +-#endif + }; + + /*****************************************/ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +index e65e76f018e4..780af5b3c16f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +@@ -729,13 +729,11 @@ void hubp1_dcc_control(struct hubp *hubp, + bool enable, + enum hubp_ind_block_size independent_64b_blks); + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + bool hubp1_program_surface_flip_and_addr( + struct hubp *hubp, + const struct dc_plane_address *address, + bool flip_immediate); + +-#endif + bool hubp1_is_flip_pending(struct hubp *hubp); + + void hubp1_cursor_set_attributes( +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index c8bd1c0cdb45..df59bd9185b5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -48,9 +48,7 @@ + #include "clk_mgr.h" + + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #include "dsc.h" +-#endif + + #define DC_LOGGER_INIT(logger) + +@@ -314,7 +312,6 @@ void dcn10_log_hw_state(struct dc *dc, + /* Read shared OTG state registers for all DCNx */ + optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + /* + * For DCN2 and greater, a register on the OPP is used to + * determine if the CRTC is blanked instead of the OTG. So use +@@ -326,9 +323,6 @@ void dcn10_log_hw_state(struct dc *dc, + s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]); + else + s.blank_enabled = tg->funcs->is_blanked(tg); +-#else +- s.blank_enabled = tg->funcs->is_blanked(tg); +-#endif + + //only print if OTG master is enabled + if ((s.otg_enabled & 1) == 0) +@@ -363,7 +357,6 @@ void dcn10_log_hw_state(struct dc *dc, + } + DTN_INFO("\n"); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n"); + for (i = 0; i < pool->res_cap->num_dsc; i++) { + struct display_stream_compressor *dsc = pool->dscs[i]; +@@ -418,7 +411,6 @@ void dcn10_log_hw_state(struct dc *dc, + } + } + DTN_INFO("\n"); +-#endif + + DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n" + "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", +@@ -1272,11 +1264,9 @@ static void dcn10_init_hw(struct dc *dc) + } + + /* Power gate DSCs */ +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + for (i = 0; i < res_pool->res_cap->num_dsc; i++) + if (dc->hwss.dsc_pg_control != NULL) + dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); +-#endif + + /* If taking control over from VBIOS, we may want to optimize our first + * mode set, so we need to skip powering down pipes until we know which +@@ -2188,12 +2178,8 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) + plane_state->format, + EXPANSION_MODE_ZERO, + plane_state->input_csc_color_matrix, +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + plane_state->color_space, + NULL); +-#else +- plane_state->color_space); +-#endif + + //set scale and bias registers + dcn10_build_prescale_params(&bns_params, plane_state); +@@ -2651,11 +2637,9 @@ static void dcn10_apply_ctx_for_surface( + if (num_planes > 0) + program_all_pipe_in_tree(dc, top_pipe_to_program, context); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* Program secondary blending tree and writeback pipes */ + if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree)) + dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context); +-#endif + if (interdependent_update) + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +index 1580f9c6d27d..24b68337d76e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +@@ -51,11 +51,9 @@ static const struct ipp_funcs dcn10_ipp_funcs = { + .ipp_destroy = dcn10_ipp_destroy + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + static const struct ipp_funcs dcn20_ipp_funcs = { + .ipp_destroy = dcn10_ipp_destroy + }; +-#endif + + void dcn10_ipp_construct( + struct dcn10_ipp *ippn10, +@@ -74,7 +72,6 @@ void dcn10_ipp_construct( + ippn10->ipp_mask = ipp_mask; + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void dcn20_ipp_construct( + struct dcn10_ipp *ippn10, + struct dc_context *ctx, +@@ -91,4 +88,3 @@ void dcn20_ipp_construct( + ippn10->ipp_shift = ipp_shift; + ippn10->ipp_mask = ipp_mask; + } +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h +index cfa24459242b..f0e0d07b0311 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h +@@ -49,7 +49,6 @@ + SRI(CURSOR_HOT_SPOT, CURSOR, id), \ + SRI(CURSOR_DST_OFFSET, CURSOR, id) + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define IPP_REG_LIST_DCN20(id) \ + IPP_REG_LIST_DCN(id), \ + SRI(CURSOR_SETTINGS, HUBPREQ, id), \ +@@ -60,7 +59,6 @@ + SRI(CURSOR_POSITION, CURSOR0_, id), \ + SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \ + SRI(CURSOR_DST_OFFSET, CURSOR0_, id) +-#endif + + #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 + #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +@@ -105,7 +103,6 @@ + IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ + IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh) + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define IPP_MASK_SH_LIST_DCN20(mask_sh) \ + IPP_MASK_SH_LIST_DCN(mask_sh), \ + IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ +@@ -124,7 +121,6 @@ + IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ + IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ + IPP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) +-#endif + + #define IPP_DCN10_REG_FIELD_LIST(type) \ + type CNVC_SURFACE_PIXEL_FORMAT; \ +@@ -196,13 +192,11 @@ void dcn10_ipp_construct(struct dcn10_ipp *ippn10, + const struct dcn10_ipp_shift *ipp_shift, + const struct dcn10_ipp_mask *ipp_mask); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void dcn20_ipp_construct(struct dcn10_ipp *ippn10, + struct dc_context *ctx, + int inst, + const struct dcn10_ipp_registers *regs, + const struct dcn10_ipp_shift *ipp_shift, + const struct dcn10_ipp_mask *ipp_mask); +-#endif + + #endif /* _DCN10_IPP_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +index 88fcc395adf5..7493a630f4dc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +@@ -72,9 +72,7 @@ + struct dcn10_link_enc_aux_registers { + uint32_t AUX_CONTROL; + uint32_t AUX_DPHY_RX_CONTROL0; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + uint32_t AUX_DPHY_TX_CONTROL; +-#endif + }; + + struct dcn10_link_enc_hpd_registers { +@@ -106,7 +104,6 @@ struct dcn10_link_enc_registers { + uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; + uint32_t DP_SEC_CNTL1; + uint32_t TMDS_CTL_BITS; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* DCCG */ + uint32_t CLOCK_ENABLE; + /* DIG */ +@@ -136,7 +133,6 @@ struct dcn10_link_enc_registers { + uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3; + uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2; + uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3; +-#endif + }; + + #define LE_SF(reg_name, field_name, post_fix)\ +@@ -242,7 +238,6 @@ struct dcn10_link_enc_registers { + type AUX_LS_READ_EN;\ + type AUX_RX_RECEIVE_WINDOW + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \ + type RDPCS_PHY_DP_TX0_DATA_EN;\ +@@ -423,20 +418,15 @@ struct dcn10_link_enc_registers { + type AUX_TX_PRECHARGE_SYMBOLS; \ + type AUX_MODE_DET_CHECK_DELAY;\ + type DPCS_DBG_CBUS_DIS +-#endif + + struct dcn10_link_enc_shift { + DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t); +-#endif + }; + + struct dcn10_link_enc_mask { + DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t); +-#endif + }; + + struct dcn10_link_encoder { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +index b3f66e1de15d..04f863499cfb 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +@@ -464,12 +464,10 @@ static const struct mpc_funcs dcn10_mpc_funcs = { + .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect, + .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, + .update_blending = mpc1_update_blending, +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + .set_denorm = NULL, + .set_denorm_clamp = NULL, + .set_output_csc = NULL, + .set_output_gamma = NULL, +-#endif + }; + + void dcn10_mpc_construct(struct dcn10_mpc *mpc10, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +index 8249b4429186..f2368be8e06d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +@@ -371,11 +371,9 @@ void opp1_program_oppbuf( + */ + REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* Controls the number of padded pixels at the end of a segment */ + if (REG(OPPBUF_CONTROL1)) + REG_UPDATE(OPPBUF_CONTROL1, OPPBUF_NUM_SEGMENT_PADDED_PIXELS, oppbuf->num_segment_padded_pixels); +-#endif + } + + void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable) +@@ -402,10 +400,8 @@ static const struct opp_funcs dcn10_opp_funcs = { + .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction, + .opp_program_stereo = opp1_program_stereo, + .opp_pipe_clock_control = opp1_pipe_clock_control, +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + .opp_set_disp_pattern_generator = NULL, + .dpg_is_blanked = NULL, +-#endif + .opp_destroy = opp1_destroy + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +index 30c025918568..cd7412dc42d1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +@@ -1502,7 +1502,6 @@ void dcn10_timing_generator_init(struct optc *optc1) + optc1->min_v_sync_width = 1; + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: + * + * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as +@@ -1515,15 +1514,12 @@ void dcn10_timing_generator_init(struct optc *optc1) + * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. + * + */ +-#endif + bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) + { + bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 + && !timing->dsc_cfg.ycbcr422_simple); +-#endif + return two_pix; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +index 4476bc8cdb4d..3afeb1a30f21 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +@@ -165,13 +165,11 @@ struct dcn_optc_registers { + uint32_t OTG_CRC0_WINDOWB_X_CONTROL; + uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; + uint32_t GSL_SOURCE_SELECT; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + uint32_t DWB_SOURCE_SELECT; + uint32_t OTG_DSC_START_POSITION; + uint32_t OPTC_DATA_FORMAT_CONTROL; + uint32_t OPTC_BYTES_PER_PIXEL; + uint32_t OPTC_WIDTH_CONTROL; +-#endif + }; + + #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ +@@ -456,7 +454,6 @@ struct dcn_optc_registers { + type MANUAL_FLOW_CONTROL;\ + type MANUAL_FLOW_CONTROL_SEL; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + + #define TG_REG_FIELD_LIST(type) \ + TG_REG_FIELD_LIST_DCN1_0(type)\ +@@ -479,12 +476,6 @@ struct dcn_optc_registers { + type OPTC_DWB0_SOURCE_SELECT;\ + type OPTC_DWB1_SOURCE_SELECT; + +-#else +- +-#define TG_REG_FIELD_LIST(type) \ +- TG_REG_FIELD_LIST_DCN1_0(type) +- +-#endif + + + struct dcn_optc_shift { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +index 2f00f2389e40..f9b9e221c698 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +@@ -163,14 +163,12 @@ struct dcn10_stream_enc_registers { + uint32_t DP_MSA_TIMING_PARAM3; + uint32_t DP_MSA_TIMING_PARAM4; + uint32_t HDMI_DB_CONTROL; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + uint32_t DP_DSC_CNTL; + uint32_t DP_DSC_BYTES_PER_PIXEL; + uint32_t DME_CONTROL; + uint32_t DP_SEC_METADATA_TRANSMISSION; + uint32_t HDMI_METADATA_PACKET_CONTROL; + uint32_t DP_SEC_FRAMING4; +-#endif + uint32_t DIG_CLOCK_PATTERN; + }; + +@@ -466,7 +464,6 @@ struct dcn10_stream_enc_registers { + type DIG_SOURCE_SELECT;\ + type DIG_CLOCK_PATTERN + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define SE_REG_FIELD_LIST_DCN2_0(type) \ + type DP_DSC_MODE;\ + type DP_DSC_SLICE_WIDTH;\ +@@ -485,20 +482,15 @@ struct dcn10_stream_enc_registers { + type DOLBY_VISION_EN;\ + type DP_PIXEL_COMBINE;\ + type DP_SST_SDP_SPLITTING +-#endif + + struct dcn10_stream_encoder_shift { + SE_REG_FIELD_LIST_DCN1_0(uint8_t); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + SE_REG_FIELD_LIST_DCN2_0(uint8_t); +-#endif + }; + + struct dcn10_stream_encoder_mask { + SE_REG_FIELD_LIST_DCN1_0(uint32_t); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + SE_REG_FIELD_LIST_DCN2_0(uint32_t); +-#endif + }; + + struct dcn10_stream_encoder { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile +index be3a614963c6..89c581196c4c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile +@@ -6,9 +6,7 @@ DCN20 = dcn20_resource.o dcn20_hwseq.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \ + dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \ + dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o + +-ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + DCN20 += dcn20_dsc.o +-endif + + CFLAGS_dcn20_resource.o := -mhard-float -msse + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +index dc9944427d2f..0111545dac75 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +@@ -23,7 +23,6 @@ + * + */ + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #include "reg_helper.h" + #include "dcn20_dsc.h" + #include "dsc/dscc_types.h" +@@ -734,4 +733,3 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const + } + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h +index 4e2fb38390a4..9855a7ed0387 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h +@@ -21,7 +21,6 @@ + * Authors: AMD + * + */ +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #ifndef __DCN20_DSC_H__ + #define __DCN20_DSC_H__ + +@@ -572,4 +571,3 @@ void dsc2_construct(struct dcn20_dsc *dsc, + + #endif + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +index 4c60fa4b89e7..2823be75b071 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +@@ -485,7 +485,6 @@ void hubp2_program_pixel_format( + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 12); + break; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 112); +@@ -506,7 +505,6 @@ void hubp2_program_pixel_format( + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 119); + break; +-#endif + default: + BREAK_TO_DEBUGGER(); + break; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index 92117b6d0012..868099fbe8ba 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -33,9 +33,7 @@ + #include "dcn10/dcn10_hw_sequencer.h" + #include "dcn20_hwseq.h" + #include "dce/dce_hwseq.h" +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #include "dcn20/dcn20_dsc.h" +-#endif + #include "abm.h" + #include "clk_mgr.h" + #include "dmcu.h" +@@ -245,7 +243,6 @@ void dcn20_init_blank( + dcn20_hwss_wait_for_blank_complete(opp); + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + static void dcn20_dsc_pg_control( + struct dce_hwseq *hws, + unsigned int dsc_inst, +@@ -322,7 +319,6 @@ static void dcn20_dsc_pg_control( + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); + } +-#endif + + static void dcn20_dpp_pg_control( + struct dce_hwseq *hws, +@@ -1695,7 +1691,6 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) + + static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) + { +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct dce_hwseq *hws = dc->hwseq; + + if (pipe_ctx->stream_res.dsc) { +@@ -1707,12 +1702,10 @@ static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx + odm_pipe = odm_pipe->next_odm_pipe; + } + } +-#endif + } + + static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) + { +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct dce_hwseq *hws = dc->hwseq; + + if (pipe_ctx->stream_res.dsc) { +@@ -1724,7 +1717,6 @@ static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) + odm_pipe = odm_pipe->next_odm_pipe; + } + } +-#endif + } + + void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) +@@ -1923,11 +1915,9 @@ static void dcn20_reset_back_end_for_pipe( + } + } + } +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + else if (pipe_ctx->stream_res.dsc) { + dp_set_dsc_enable(pipe_ctx, false); + } +-#endif + + /* by upper caller loop, parent pipe: pipe0, will be reset last. + * back end share by all pipes and will be disable only when disable +@@ -2439,11 +2429,7 @@ void dcn20_hw_sequencer_construct(struct dc *dc) + dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane; + dc->hwss.dpp_pg_control = dcn20_dpp_pg_control; + dc->hwss.hubp_pg_control = dcn20_hubp_pg_control; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + dc->hwss.dsc_pg_control = dcn20_dsc_pg_control; +-#else +- dc->hwss.dsc_pg_control = NULL; +-#endif + dc->hwss.disable_vga = dcn20_disable_vga; + + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c +index 0e0306d84cd8..e4ac73035c84 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c +@@ -168,10 +168,8 @@ static struct mpll_cfg dcn2_mpll_cfg[] = { + void enc2_fec_set_enable(struct link_encoder *enc, bool enable) + { + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + DC_LOG_DSC("%s FEC at link encoder inst %d", + enable ? "Enabling" : "Disabling", enc->id.enum_id); +-#endif + REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable); + } + +@@ -192,7 +190,6 @@ bool enc2_fec_is_active(struct link_encoder *enc) + return (active != 0); + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state + * into a dcn_dsc_state struct. + */ +@@ -205,7 +202,6 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) + REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); + REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); + } +-#endif + + static bool update_cfg_data( + struct dcn10_link_encoder *enc10, +@@ -316,9 +312,7 @@ void enc2_hw_init(struct link_encoder *enc) + } + + static const struct link_encoder_funcs dcn20_link_enc_funcs = { +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .read_state = link_enc2_read_state, +-#endif + .validate_output_with_stream = + dcn10_link_encoder_validate_output_with_stream, + .hw_init = enc2_hw_init, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h +index 0c98a0bbbd14..62dfd34c69f1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h +@@ -158,9 +158,7 @@ void enc2_fec_set_ready(struct link_encoder *enc, bool ready); + bool enc2_fec_is_active(struct link_encoder *enc); + void enc2_hw_init(struct link_encoder *enc); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); +-#endif + + void dcn20_link_encoder_enable_dp_output( + struct link_encoder *enc, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c +index 3b613fb93ef8..0e50dc9b611a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c +@@ -167,7 +167,6 @@ void optc2_set_gsl_source_select( + } + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */ + void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc, + int x_position, +@@ -201,7 +200,6 @@ void optc2_set_dsc_config(struct timing_generator *optc, + REG_UPDATE(OPTC_WIDTH_CONTROL, + OPTC_DSC_SLICE_WIDTH, dsc_slice_width); + } +-#endif + + /** + * PTI i think is already done somewhere else for 2ka +@@ -448,9 +446,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = { + .setup_global_swap_lock = NULL, + .get_crc = optc1_get_crc, + .configure_crc = optc1_configure_crc, +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .set_dsc_config = optc2_set_dsc_config, +-#endif + .set_dwb_source = optc2_set_dwb_source, + .set_odm_bypass = optc2_set_odm_bypass, + .set_odm_combine = optc2_set_odm_combine, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h +index 32a58431fd09..9ae22146d2d8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h +@@ -86,12 +86,10 @@ void optc2_set_gsl_source_select(struct timing_generator *optc, + int group_idx, + uint32_t gsl_ready_signal); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + void optc2_set_dsc_config(struct timing_generator *optc, + enum optc_dsc_mode dsc_mode, + uint32_t dsc_bytes_per_pixel, + uint32_t dsc_slice_width); +-#endif + + void optc2_set_odm_bypass(struct timing_generator *optc, + const struct dc_crtc_timing *dc_crtc_timing); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 3119714586dd..9f721d5bea3b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -43,9 +43,7 @@ + #include "dcn10/dcn10_resource.h" + #include "dcn20_opp.h" + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #include "dcn20_dsc.h" +-#endif + + #include "dcn20_link_encoder.h" + #include "dcn20_stream_encoder.h" +@@ -93,11 +91,7 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = { + .hostvm_max_page_table_levels = 4, + .hostvm_cached_page_table_levels = 0, + .pte_group_size_bytes = 2048, +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .num_dsc = 6, +-#else +- .num_dsc = 0, +-#endif + .rob_buffer_size_kbytes = 168, + .det_buffer_size_kbytes = 164, + .dpte_buffer_size_in_pte_reqs_luma = 84, +@@ -742,7 +736,6 @@ static const struct dce110_aux_registers_mask aux_mask = { + }; + + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #define dsc_regsDCN20(id)\ + [id] = {\ + DSC_REG_LIST_DCN20(id)\ +@@ -764,7 +757,6 @@ static const struct dcn20_dsc_shift dsc_shift = { + static const struct dcn20_dsc_mask dsc_mask = { + DSC_REG_LIST_SH_MASK_DCN20(_MASK) + }; +-#endif + + static const struct dccg_registers dccg_regs = { + DCCG_REG_LIST_DCN2() +@@ -788,9 +780,7 @@ static const struct resource_caps res_cap_nv10 = { + .num_dwb = 1, + .num_ddc = 6, + .num_vmid = 16, +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .num_dsc = 6, +-#endif + }; + + static const struct dc_plane_cap plane_cap = { +@@ -1211,7 +1201,6 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src) + *clk_src = NULL; + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + + struct display_stream_compressor *dcn20_dsc_create( + struct dc_context *ctx, uint32_t inst) +@@ -1234,7 +1223,6 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc) + *dsc = NULL; + } + +-#endif + + static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) + { +@@ -1247,12 +1235,10 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) + } + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + if (pool->base.dscs[i] != NULL) + dcn20_dsc_destroy(&pool->base.dscs[i]); + } +-#endif + + if (pool->base.mpc != NULL) { + kfree(TO_DCN20_MPC(pool->base.mpc)); +@@ -1463,7 +1449,6 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state + return status; + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + + static void acquire_dsc(struct resource_context *res_ctx, + const struct resource_pool *pool, +@@ -1497,10 +1482,8 @@ static void release_dsc(struct resource_context *res_ctx, + } + } + +-#endif + + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + static enum dc_status add_dsc_to_stream_resource(struct dc *dc, + struct dc_state *dc_ctx, + struct dc_stream_state *dc_stream) +@@ -1552,7 +1535,6 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, + else + return DC_OK; + } +-#endif + + + enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) +@@ -1564,11 +1546,9 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, + if (result == DC_OK) + result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* Get a DSC if required and available */ + if (result == DC_OK && dc_stream->timing.flags.DSC) + result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream); +-#endif + + if (result == DC_OK) + result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); +@@ -1581,9 +1561,7 @@ enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ + { + enum dc_status result = DC_OK; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); +-#endif + + return result; + } +@@ -1666,9 +1644,7 @@ bool dcn20_split_stream_for_odm( + next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; + next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; + next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + next_odm_pipe->stream_res.dsc = NULL; +-#endif + if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { + next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; + next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; +@@ -1714,14 +1690,12 @@ bool dcn20_split_stream_for_odm( + sd->recout.x = 0; + } + next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (next_odm_pipe->stream->timing.flags.DSC == 1) { + acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc); + ASSERT(next_odm_pipe->stream_res.dsc); + if (next_odm_pipe->stream_res.dsc == NULL) + return false; + } +-#endif + + return true; + } +@@ -1745,9 +1719,7 @@ void dcn20_split_stream_for_mpc( + secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; + secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; + secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + secondary_pipe->stream_res.dsc = NULL; +-#endif + if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { + ASSERT(!secondary_pipe->bottom_pipe); + secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; +@@ -1835,11 +1807,9 @@ int dcn20_populate_dml_pipes_from_context( + pipes[pipe_cnt].pipe.src.dcc = 0; + pipes[pipe_cnt].pipe.src.vm = 0;*/ + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; + /* todo: rotation?*/ + pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; +-#endif + if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { + pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; + /* 1/2 vblank */ +@@ -1927,14 +1897,12 @@ int dcn20_populate_dml_pipes_from_context( + case COLOR_DEPTH_161616: + output_bpc = 16; + break; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + case COLOR_DEPTH_999: + output_bpc = 9; + break; + case COLOR_DEPTH_111111: + output_bpc = 11; + break; +-#endif + default: + output_bpc = 8; + break; +@@ -1962,10 +1930,8 @@ int dcn20_populate_dml_pipes_from_context( + pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) + pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; +-#endif + + /* todo: default max for now, until there is logic reflecting this in dc*/ + pipes[pipe_cnt].dout.output_bpc = 12; +@@ -2187,7 +2153,6 @@ void dcn20_set_mcif_arb_params( + } + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) + { + int i; +@@ -2221,7 +2186,6 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) + } + return true; + } +-#endif + + struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, + struct resource_context *res_ctx, +@@ -2324,10 +2288,8 @@ void dcn20_merge_pipes_for_validate( + odm_pipe->bottom_pipe = NULL; + odm_pipe->prev_odm_pipe = NULL; + odm_pipe->next_odm_pipe = NULL; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (odm_pipe->stream_res.dsc) + release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); +-#endif + /* Clear plane_res and stream_res */ + memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); + memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); +@@ -2547,14 +2509,12 @@ bool dcn20_fast_validate_bw( + ASSERT(0); + } + } +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* Actual dsc count per stream dsc validation*/ + if (!dcn20_validate_dsc(dc, context)) { + context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = + DML_FAIL_DSC_VALIDATION_FAILURE; + goto validate_fail; + } +-#endif + + *vlevel_out = vlevel; + +@@ -3656,7 +3616,6 @@ static bool dcn20_resource_construct( + goto create_fail; + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + pool->base.dscs[i] = dcn20_dsc_create(ctx, i); + if (pool->base.dscs[i] == NULL) { +@@ -3665,7 +3624,6 @@ static bool dcn20_resource_construct( + goto create_fail; + } + } +-#endif + + if (!dcn20_dwbc_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h +index 7187e0f8eb28..840ca66c34e1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h +@@ -127,9 +127,7 @@ int dcn20_validate_apply_pipe_split_flags( + struct dc_state *context, + int vlevel, + bool *split); +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx); +-#endif + void dcn20_split_stream_for_mpc( + struct resource_context *res_ctx, + const struct resource_pool *pool, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +index b909c526b7f9..3549c81b20b7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +@@ -203,7 +203,6 @@ static void enc2_stream_encoder_stop_hdmi_info_packets( + HDMI_GENERIC7_LINE, 0); + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + + /* Update GSP7 SDP 128 byte long */ + static void enc2_update_gsp7_128_info_packet( +@@ -358,7 +357,6 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s) + REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); + } + } +-#endif + + /* Set Dynamic Metadata-configuration. + * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME +@@ -438,10 +436,8 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) + { + bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 + && !timing->dsc_cfg.ycbcr422_simple); +-#endif + return two_pix; + } + +@@ -587,11 +583,9 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { + .dp_get_pixel_format = + enc1_stream_encoder_dp_get_pixel_format, + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .enc_read_state = enc2_read_state, + .dp_set_dsc_config = enc2_dp_set_dsc_config, + .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, +-#endif + .set_dynamic_metadata = enc2_set_dynamic_metadata, + .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, + }; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +index e8a504ca5890..e45683ac871a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +@@ -323,9 +323,7 @@ void dcn21_link_encoder_disable_output( + + + static const struct link_encoder_funcs dcn21_link_enc_funcs = { +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .read_state = link_enc2_read_state, +-#endif + .validate_output_with_stream = + dcn10_link_encoder_validate_output_with_stream, + .hw_init = enc2_hw_init, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index 9ec73b513488..f68f643a82af 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -88,11 +88,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = { + .gpuvm_max_page_table_levels = 1, + .hostvm_max_page_table_levels = 4, + .hostvm_cached_page_table_levels = 2, +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .num_dsc = 3, +-#else +- .num_dsc = 0, +-#endif + .rob_buffer_size_kbytes = 168, + .det_buffer_size_kbytes = 164, + .dpte_buffer_size_in_pte_reqs_luma = 44, +@@ -538,7 +534,6 @@ static const struct dcn20_vmid_mask vmid_masks = { + DCN20_VMID_MASK_SH_LIST(_MASK) + }; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #define dsc_regsDCN20(id)\ + [id] = {\ + DSC_REG_LIST_DCN20(id)\ +@@ -560,7 +555,6 @@ static const struct dcn20_dsc_shift dsc_shift = { + static const struct dcn20_dsc_mask dsc_mask = { + DSC_REG_LIST_SH_MASK_DCN20(_MASK) + }; +-#endif + + #define ipp_regs(id)\ + [id] = {\ +@@ -757,9 +751,7 @@ static const struct resource_caps res_cap_rn = { + .num_dwb = 1, + .num_ddc = 5, + .num_vmid = 1, +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .num_dsc = 3, +-#endif + }; + + #ifdef DIAGS_BUILD +@@ -784,9 +776,7 @@ static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { + .num_pll = 4, + .num_dwb = 1, + .num_ddc = 4, +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .num_dsc = 2, +-#endif + }; + #endif + +@@ -865,12 +855,10 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) + } + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + if (pool->base.dscs[i] != NULL) + dcn20_dsc_destroy(&pool->base.dscs[i]); + } +-#endif + + if (pool->base.mpc != NULL) { + kfree(TO_DCN20_MPC(pool->base.mpc)); +@@ -1299,7 +1287,6 @@ static void read_dce_straps( + + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + + struct display_stream_compressor *dcn21_dsc_create( + struct dc_context *ctx, uint32_t inst) +@@ -1315,7 +1302,6 @@ struct display_stream_compressor *dcn21_dsc_create( + dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); + return &dsc->base; + } +-#endif + + static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) + { +@@ -1875,7 +1861,6 @@ static bool dcn21_resource_construct( + goto create_fail; + } + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + pool->base.dscs[i] = dcn21_dsc_create(ctx, i); + if (pool->base.dscs[i] == NULL) { +@@ -1884,7 +1869,6 @@ static bool dcn21_resource_construct( + goto create_fail; + } + } +-#endif + + if (!dcn20_dwbc_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); +diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h +index 94b75e942607..8bde1d688f2e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h +@@ -118,13 +118,11 @@ bool dm_helpers_submit_i2c( + const struct dc_link *link, + struct i2c_command *cmd); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool dm_helpers_dp_write_dsc_enable( + struct dc_context *ctx, + const struct dc_stream_state *stream, + bool enable + ); +-#endif + bool dm_helpers_is_dp_sink_present( + struct dc_link *link); + +diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +index 95f3193da951..04d54283c94f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +@@ -41,9 +41,7 @@ enum pp_smu_ver { + */ + PP_SMU_UNSUPPORTED, + PP_SMU_VER_RV, +-#ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0 + PP_SMU_VER_NV, +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + PP_SMU_VER_RN, + #endif +@@ -137,7 +135,6 @@ struct pp_smu_funcs_rv { + void (*set_pme_wa_enable)(struct pp_smu *pp); + }; + +-#ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0 + /* Used by pp_smu_funcs_nv.set_voltage_by_freq + * + */ +@@ -241,7 +238,6 @@ struct pp_smu_funcs_nv { + enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp, + BOOLEAN pstate_handshake_supported); + }; +-#endif + + #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8 + #define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8 +@@ -285,9 +281,7 @@ struct pp_smu_funcs { + struct pp_smu ctx; + union { + struct pp_smu_funcs_rv rv_funcs; +-#ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0 + struct pp_smu_funcs_nv nv_funcs; +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + struct pp_smu_funcs_rn rn_funcs; + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile +index 9cc2fe56ed64..e3d6546a08c2 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile +@@ -43,7 +43,7 @@ endif + + CFLAGS_display_mode_lib.o := $(dml_ccflags) + +-ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++ifdef CONFIG_DRM_AMD_DC_DCN1_0 + CFLAGS_display_mode_vba.o := $(dml_ccflags) + CFLAGS_display_mode_vba_20.o := $(dml_ccflags) + CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags) +@@ -64,7 +64,7 @@ CFLAGS_dml_common_defs.o := $(dml_ccflags) + DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \ + dml_common_defs.o + +-ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++ifdef CONFIG_DRM_AMD_DC_DCN1_0 + DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o + DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o + endif +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +index ba77957aefe3..945291d5ad98 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +@@ -23,7 +23,6 @@ + * + */ + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + + #include "../display_mode_lib.h" + #include "../dml_inline_defs.h" +@@ -6126,4 +6125,3 @@ static double CalculateExtraLatency( + return CalculateExtraLatency; + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c +index a1f207cbb966..a4b103eb4b02 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c +@@ -23,7 +23,6 @@ + * + */ + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + + #include "../display_mode_lib.h" + #include "../display_mode_vba.h" +@@ -1820,4 +1819,3 @@ static void calculate_ttu_cursor( + } + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +index 1c97083b8d0b..55d4cb23a073 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +@@ -135,9 +135,7 @@ enum dm_validation_status { + DML_FAIL_DIO_SUPPORT, + DML_FAIL_NOT_ENOUGH_DSC, + DML_FAIL_DSC_CLK_REQUIRED, +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + DML_FAIL_DSC_VALIDATION_FAILURE, +-#endif + DML_FAIL_URGENT_LATENCY, + DML_FAIL_REORDERING_BUFFER, + DML_FAIL_DISPCLK_DPPCLK, +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c +index 704efefdcba8..9c6016e57d2b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c +@@ -25,18 +25,15 @@ + + #include "display_mode_lib.h" + #include "dc_features.h" +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "dcn20/display_mode_vba_20.h" + #include "dcn20/display_rq_dlg_calc_20.h" + #include "dcn20/display_mode_vba_20v2.h" + #include "dcn20/display_rq_dlg_calc_20v2.h" +-#endif + #ifdef CONFIG_DRM_AMD_DC_DCN2_1 + #include "dcn21/display_mode_vba_21.h" + #include "dcn21/display_rq_dlg_calc_21.h" + #endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + const struct dml_funcs dml20_funcs = { + .validate = dml20_ModeSupportAndSystemConfigurationFull, + .recalculate = dml20_recalculate, +@@ -50,7 +47,6 @@ const struct dml_funcs dml20v2_funcs = { + .rq_dlg_get_dlg_reg = dml20v2_rq_dlg_get_dlg_reg, + .rq_dlg_get_rq_reg = dml20v2_rq_dlg_get_rq_reg + }; +-#endif + + #ifdef CONFIG_DRM_AMD_DC_DCN2_1 + const struct dml_funcs dml21_funcs = { +@@ -70,14 +66,12 @@ void dml_init_instance(struct display_mode_lib *lib, + lib->ip = *ip_params; + lib->project = project; + switch (project) { +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + case DML_PROJECT_NAVI10: + lib->funcs = dml20_funcs; + break; + case DML_PROJECT_NAVI10v2: + lib->funcs = dml20v2_funcs; + break; +-#endif + #ifdef CONFIG_DRM_AMD_DC_DCN2_1 + case DML_PROJECT_DCN21: + lib->funcs = dml21_funcs; +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h +index d8c59aa356b6..212188be1ec1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h +@@ -27,17 +27,13 @@ + + + #include "dml_common_defs.h" +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + #include "display_mode_vba.h" +-#endif + + enum dml_project { + DML_PROJECT_UNDEFINED, + DML_PROJECT_RAVEN1, +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + DML_PROJECT_NAVI10, + DML_PROJECT_NAVI10v2, +-#endif + #ifdef CONFIG_DRM_AMD_DC_DCN2_1 + DML_PROJECT_DCN21, + #endif +@@ -70,9 +66,7 @@ struct display_mode_lib { + struct _vcs_dpi_ip_params_st ip; + struct _vcs_dpi_soc_bounding_box_st soc; + enum dml_project project; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct vba_vars_st vba; +-#endif + struct dal_logger *logger; + struct dml_funcs funcs; + }; +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +index 19356180cbb6..516396d53d01 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +@@ -146,7 +146,6 @@ struct _vcs_dpi_ip_params_st { + unsigned int writeback_interface_buffer_size_kbytes; + unsigned int writeback_line_buffer_buffer_size; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + unsigned int writeback_10bpc420_supported; + double writeback_max_hscl_ratio; + double writeback_max_vscl_ratio; +@@ -156,7 +155,6 @@ struct _vcs_dpi_ip_params_st { + unsigned int writeback_max_vscl_taps; + unsigned int writeback_line_buffer_luma_buffer_size; + unsigned int writeback_line_buffer_chroma_buffer_size; +-#endif + + unsigned int max_page_table_levels; + unsigned int max_num_dpp; +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +index da5e9d2fd6b6..b1c2b79e42b6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +@@ -23,7 +23,6 @@ + * + */ + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + + #include "display_mode_lib.h" + #include "display_mode_vba.h" +@@ -862,4 +861,3 @@ double CalculateWriteBackDISPCLK( + return CalculateWriteBackDISPCLK; + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +index 6d8b5c61de68..3eb657ed5714 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +@@ -23,7 +23,6 @@ + * + */ + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + + #ifndef __DML2_DISPLAY_MODE_VBA_H__ + #define __DML2_DISPLAY_MODE_VBA_H__ +@@ -872,4 +871,3 @@ double CalculateWriteBackDISPCLK( + unsigned int WritebackChromaLineBufferWidth); + + #endif /* _DML2_DISPLAY_MODE_VBA_H_ */ +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +index f76a72a96631..ec86ba73a039 100644 +--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c ++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +@@ -22,7 +22,6 @@ + * Author: AMD + */ + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #include "dc_hw_types.h" + #include "dsc.h" + #include <drm/drm_dp_helper.h> +@@ -907,4 +906,3 @@ bool dc_dsc_compute_config( + timing, dsc_min_slice_height_override, dsc_cfg); + return is_dsc_possible; + } +-#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ +diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h b/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h +index 020ad8f685ea..9f70e87b3ecb 100644 +--- a/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h +@@ -1,4 +1,3 @@ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + /* + * Copyright 2017 Advanced Micro Devices, Inc. +@@ -51,4 +50,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_par + + #endif + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h b/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h +index f66d006eac5d..e5fac9f4181d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h ++++ b/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h +@@ -1,4 +1,3 @@ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + /* + * Copyright 2017 Advanced Micro Devices, Inc. +@@ -703,4 +702,3 @@ const qp_table qp_table_422_8bpc_max = { + { 16, { 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 4} } + }; + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +index 76c4b12d6824..03ae15946c6d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c ++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +@@ -1,4 +1,3 @@ +-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) + + /* + * Copyright 2017 Advanced Micro Devices, Inc. +@@ -252,4 +251,3 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_com + rc->rc_buf_thresh[13] = 8064; + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h +index f1d6e793bc61..b6b1f09c2009 100644 +--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h ++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h +@@ -1,4 +1,3 @@ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + /* + * Copyright 2017 Advanced Micro Devices, Inc. +@@ -82,4 +81,3 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_com + + #endif + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +index 73172fd0b529..1f6e63b71456 100644 +--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c ++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +@@ -1,4 +1,3 @@ +-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) + /* + * Copyright 2012-17 Advanced Micro Devices, Inc. + * +@@ -144,4 +143,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_par + return ret; + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile +index b3062275711e..7791cd29fc18 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile +@@ -67,12 +67,10 @@ GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o + AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10)) + + AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN10) +-endif + + ############################################################################### + # DCN 2 + ############################################################################### +-ifdef CONFIG_DRM_AMD_DC_DCN2_0 + GPIO_DCN20 = hw_translate_dcn20.o hw_factory_dcn20.o + + AMD_DAL_GPIO_DCN20 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn20/,$(GPIO_DCN20)) +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c +index 2664cb22dfe7..83f798cb8b21 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c +@@ -22,7 +22,6 @@ + * Authors: AMD + * + */ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "dm_services.h" + #include "include/gpio_types.h" + #include "../hw_factory.h" +@@ -258,4 +257,3 @@ void dal_hw_factory_dcn20_init(struct hw_factory *factory) + factory->funcs = &funcs; + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h +index 43a4ce7aa3bf..0fd9b315bd7a 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h +@@ -22,7 +22,6 @@ + * Authors: AMD + * + */ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #ifndef __DAL_HW_FACTORY_DCN20_H__ + #define __DAL_HW_FACTORY_DCN20_H__ + +@@ -30,4 +29,3 @@ + void dal_hw_factory_dcn20_init(struct hw_factory *factory); + + #endif /* __DAL_HW_FACTORY_DCN20_H__ */ +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c +index 915e896e0e91..52ba62b3b5e4 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c +@@ -26,7 +26,6 @@ + /* + * Pre-requisites: headers required by header of this unit + */ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "hw_translate_dcn20.h" + + #include "dm_services.h" +@@ -379,4 +378,3 @@ void dal_hw_translate_dcn20_init(struct hw_translate *tr) + tr->funcs = &funcs; + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h +index 01f52c7bed86..5f7a35530e26 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h +@@ -22,7 +22,6 @@ + * Authors: AMD + * + */ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #ifndef __DAL_HW_TRANSLATE_DCN20_H__ + #define __DAL_HW_TRANSLATE_DCN20_H__ + +@@ -32,4 +31,3 @@ struct hw_translate; + void dal_hw_translate_dcn20_init(struct hw_translate *tr); + + #endif /* __DAL_HW_TRANSLATE_DCN20_H__ */ +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c +index 8572678f8d4f..907c5911eb9e 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c +@@ -22,7 +22,6 @@ + * Authors: AMD + * + */ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "dm_services.h" + #include "include/gpio_types.h" + #include "../hw_factory.h" +@@ -239,4 +238,3 @@ void dal_hw_factory_dcn21_init(struct hw_factory *factory) + factory->funcs = &funcs; + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c +index fbb58fb8c318..291966efe63d 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c +@@ -26,7 +26,6 @@ + /* + * Pre-requisites: headers required by header of this unit + */ +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "hw_translate_dcn21.h" + + #include "dm_services.h" +@@ -382,4 +381,3 @@ void dal_hw_translate_dcn21_init(struct hw_translate *tr) + tr->funcs = &funcs; + } + +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h +index f91e85b04956..308a543178a5 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h ++++ b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h +@@ -48,13 +48,11 @@ + DDC_GPIO_REG_LIST(cd,id),\ + .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define DDC_REG_LIST_DCN2(cd, id) \ + DDC_GPIO_REG_LIST(cd, id),\ + .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\ + .phy_aux_cntl = REG(PHY_AUX_CNTL), \ + .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) +-#endif + + #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\ + .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ +@@ -90,13 +88,11 @@ + DDC_GPIO_I2C_REG_LIST(cd),\ + .ddc_setup = 0 + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define DDC_I2C_REG_LIST_DCN2(cd) \ + DDC_GPIO_I2C_REG_LIST(cd),\ + .ddc_setup = 0,\ + .phy_aux_cntl = REG(PHY_AUX_CNTL), \ + .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) +-#endif + #define DDC_MASK_SH_LIST_COMMON(mask_sh) \ + SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ + SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\ +@@ -110,22 +106,18 @@ + SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\ + SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh) + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \ + {DDC_MASK_SH_LIST_COMMON(mask_sh),\ + 0,\ + 0,\ + (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\ + (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)} +-#endif + + struct ddc_registers { + struct gpio_registers gpio; + uint32_t ddc_setup; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + uint32_t phy_aux_cntl; + uint32_t dc_gpio_aux_ctrl_5; +-#endif + }; + + struct ddc_sh_mask { +@@ -140,11 +132,9 @@ struct ddc_sh_mask { + /* i2cpad_mask */ + uint32_t DC_GPIO_SDA_PD_DIS; + uint32_t DC_GPIO_SCL_PD_DIS; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + //phy_aux_cntl + uint32_t AUX_PAD_RXSEL; + uint32_t DDC_PAD_I2CMODE; +-#endif + }; + + +@@ -180,7 +170,6 @@ struct ddc_sh_mask { + {\ + DDC_I2C_REG_LIST(SCL)\ + } +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define ddc_data_regs_dcn2(id) \ + {\ + DDC_REG_LIST_DCN2(DATA, id)\ +@@ -200,7 +189,6 @@ struct ddc_sh_mask { + {\ + DDC_REG_LIST_DCN2(SCL)\ + } +-#endif + + + #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +index 95d1c44a1d47..847da5a76b70 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +@@ -147,7 +147,6 @@ static enum gpio_result set_config( + AUX_PAD1_MODE, 0); + } + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { + REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1); + } +@@ -155,7 +154,6 @@ static enum gpio_result set_config( + if (ddc->regs->phy_aux_cntl != 0) { + REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1); + } +-#endif + return GPIO_RESULT_OK; + case GPIO_DDC_CONFIG_TYPE_MODE_AUX: + /* set the AUX pad mode */ +@@ -163,12 +161,10 @@ static enum gpio_result set_config( + REG_SET(gpio.MASK_reg, regval, + AUX_PAD1_MODE, 1); + } +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { + REG_UPDATE(dc_gpio_aux_ctrl_5, + DDC_PAD_I2CMODE, 0); + } +-#endif + + return GPIO_RESULT_OK; + case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT: +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +index cb5857c8c7e9..18b9fab15676 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +@@ -46,9 +46,7 @@ + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "dcn10/hw_factory_dcn10.h" + #endif +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "dcn20/hw_factory_dcn20.h" +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + #include "dcn21/hw_factory_dcn21.h" + #endif +@@ -93,17 +91,15 @@ bool dal_hw_factory_init( + case DCN_VERSION_1_01: + dal_hw_factory_dcn10_init(factory); + return true; +-#endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case DCN_VERSION_2_0: + dal_hw_factory_dcn20_init(factory); + return true; +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + case DCN_VERSION_2_1: + dal_hw_factory_dcn21_init(factory); + return true; ++#endif + #endif + + default: +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +index f2046f55d6a8..8e10bff4c074 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +@@ -46,9 +46,7 @@ + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "dcn10/hw_translate_dcn10.h" + #endif +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "dcn20/hw_translate_dcn20.h" +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + #include "dcn21/hw_translate_dcn21.h" + #endif +@@ -90,17 +88,15 @@ bool dal_hw_translate_init( + case DCN_VERSION_1_01: + dal_hw_translate_dcn10_init(translate); + return true; +-#endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case DCN_VERSION_2_0: + dal_hw_translate_dcn20_init(translate); + return true; +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + case DCN_VERSION_2_1: + dal_hw_translate_dcn21_init(translate); + return true; ++#endif + #endif + + default: +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h +index fd39e2abe2ed..4ead89dd7c41 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h +@@ -43,10 +43,8 @@ enum dc_status { + DC_FAIL_BANDWIDTH_VALIDATE = 13, /* BW and Watermark validation */ + DC_FAIL_SCALING = 14, + DC_FAIL_DP_LINK_TRAINING = 15, +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + DC_FAIL_DSC_VALIDATE = 16, + DC_NO_DSC_RESOURCE = 17, +-#endif + DC_FAIL_UNSUPPORTED_1 = 18, + DC_FAIL_CLK_EXCEED_MAX = 21, + DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index 67efc8094ae7..d7018e894bc2 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -36,10 +36,8 @@ + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "mpc.h" + #endif +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #include "dwb.h" + #include "mcif_wb.h" +-#endif + + #define MAX_CLOCK_SOURCES 7 + +@@ -135,7 +133,6 @@ struct resource_funcs { + struct resource_context *res_ctx, + const struct resource_pool *pool, + struct dc_stream_state *stream); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void (*populate_dml_writeback_from_context)( + struct dc *dc, + struct resource_context *res_ctx, +@@ -146,7 +143,6 @@ struct resource_funcs { + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt); +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + void (*update_bw_bounding_box)( + struct dc *dc, +@@ -180,7 +176,6 @@ struct resource_pool { + struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; + bool i2c_hw_buffer_in_use; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dwbc *dwbc[MAX_DWB_PIPES]; + struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; + struct { +@@ -188,11 +183,8 @@ struct resource_pool { + unsigned int gsl_1:1; + unsigned int gsl_2:1; + } gsl_groups; +-#endif + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct display_stream_compressor *dscs[MAX_PIPES]; +-#endif + + unsigned int pipe_count; + unsigned int underlay_pipe_index; +@@ -206,9 +198,7 @@ struct resource_pool { + unsigned int timing_generator_count; + unsigned int mpcc_count; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + unsigned int writeback_pipe_count; +-#endif + /* + * reserved clock source for DP + */ +@@ -240,9 +230,7 @@ struct dcn_fe_bandwidth { + + struct stream_resource { + struct output_pixel_processor *opp; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct display_stream_compressor *dsc; +-#endif + struct timing_generator *tg; + struct stream_encoder *stream_enc; + struct audio *audio; +@@ -251,12 +239,10 @@ struct stream_resource { + struct encoder_info_frame encoder_info_frame; + + struct abm *abm; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* There are only (num_pipes+1)/2 groups. 0 means unassigned, + * otherwise it's using group number 'gsl_group-1' + */ + uint8_t gsl_group; +-#endif + }; + + struct plane_resource { +@@ -315,10 +301,8 @@ struct pipe_ctx { + struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; + #endif + union pipe_update_flags update_flags; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct dwbc *dwbc; + struct mcif_wb *mcif_wb; +-#endif + }; + + struct resource_context { +@@ -327,9 +311,7 @@ struct resource_context { + bool is_audio_acquired[MAX_PIPES]; + uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; + uint8_t dp_clock_source_ref_count; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + bool is_dsc_acquired[MAX_PIPES]; +-#endif + }; + + struct dce_bw_output { +@@ -349,18 +331,14 @@ struct dce_bw_output { + int blackout_recovery_time_us; + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dcn_bw_writeback { + struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; + }; +-#endif + + struct dcn_bw_output { + struct dc_clocks clk; + struct dcn_watermark_set watermarks; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dcn_bw_writeback bw_writeback; +-#endif + }; + + union bw_output { +diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +index 1e6ff6eb5bfc..4879cf54d8f1 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +@@ -75,13 +75,11 @@ void dp_enable_mst_on_sink(struct dc_link *link, bool enable); + enum dp_panel_mode dp_get_panel_mode(struct dc_link *link); + void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode); + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + void dp_set_fec_ready(struct dc_link *link, bool ready); + void dp_set_fec_enable(struct dc_link *link, bool enable); + bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable); + bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable); + void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable); + bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx); +-#endif + + #endif /* __DC_LINK_DP_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +index a17a77192690..862952c0286a 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +@@ -96,12 +96,10 @@ enum dentist_divider_range { + .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \ + .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67 + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + #define CLK_REG_LIST_NV10() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \ + CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) +-#endif + + #define CLK_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix +@@ -120,7 +118,6 @@ enum dentist_divider_range { + CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\ + CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh), + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\ +@@ -130,7 +127,6 @@ enum dentist_divider_range { + CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ + CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\ + CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh) +-#endif + + #define CLK_REG_FIELD_LIST(type) \ + type DPREFCLK_SRC_SEL; \ +@@ -143,30 +139,24 @@ enum dentist_divider_range { + ****************** Clock Manager Private Structures *********************************** + *************************************************************************************** + */ +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + #define CLK20_REG_FIELD_LIST(type) \ + type DENTIST_DPPCLK_WDIVIDER; \ + type DENTIST_DPPCLK_CHG_DONE; \ + type FbMult_int; \ + type FbMult_frac; +-#endif + + #define VBIOS_SMU_REG_FIELD_LIST(type) \ + type CONTENT; + + struct clk_mgr_shift { + CLK_REG_FIELD_LIST(uint8_t) +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + CLK20_REG_FIELD_LIST(uint8_t) +-#endif + VBIOS_SMU_REG_FIELD_LIST(uint32_t) + }; + + struct clk_mgr_mask { + CLK_REG_FIELD_LIST(uint32_t) +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + CLK20_REG_FIELD_LIST(uint32_t) +-#endif + VBIOS_SMU_REG_FIELD_LIST(uint32_t) + }; + +@@ -174,10 +164,8 @@ struct clk_mgr_registers { + uint32_t DPREFCLK_CNTL; + uint32_t DENTIST_DISPCLK_CNTL; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + uint32_t CLK3_CLK2_DFS_CNTL; + uint32_t CLK3_CLK_PLL_REQ; +-#endif + + uint32_t MP1_SMN_C2PMSG_67; + uint32_t MP1_SMN_C2PMSG_83; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +index c81a17aeaa25..c0dc1d0f5cae 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +@@ -52,7 +52,6 @@ struct dcn_hubbub_wm { + struct dcn_hubbub_wm_set sets[4]; + }; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + enum dcn_hubbub_page_table_depth { + DCN_PAGE_TABLE_DEPTH_1_LEVEL, + DCN_PAGE_TABLE_DEPTH_2_LEVEL, +@@ -101,13 +100,11 @@ struct hubbub_addr_config { + } default_addrs; + }; + +-#endif + struct hubbub_funcs { + void (*update_dchub)( + struct hubbub *hubbub, + struct dchub_init_data *dh_data); + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + int (*init_dchub_sys_ctx)( + struct hubbub *hubbub, + struct dcn_hubbub_phys_addr_config *pa_config); +@@ -116,7 +113,6 @@ struct hubbub_funcs { + struct dcn_hubbub_virt_addr_config *va_config, + int vmid); + +-#endif + bool (*get_dcc_compression_cap)(struct hubbub *hubbub, + const struct dc_dcc_surface_param *input, + struct dc_surface_dcc_cap *output); +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +index 474c7194a9f8..125e42dbd3c5 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +@@ -36,14 +36,10 @@ struct dpp { + struct dpp_caps *caps; + struct pwl_params regamma_params; + struct pwl_params degamma_params; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dpp_cursor_attributes cur_attr; +-#endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct pwl_params shaper_params; + bool cm_bypass_mode; +-#endif + }; + + struct dpp_input_csc_matrix { +@@ -56,7 +52,6 @@ struct dpp_grph_csc_adjustment { + enum graphics_gamut_adjust_type gamut_adjust_type; + }; + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct cnv_color_keyer_params { + int color_keyer_en; + int color_keyer_mode; +@@ -82,7 +77,6 @@ struct cnv_alpha_2bit_lut { + int lut2; + int lut3; + }; +-#endif + + struct dcn_dpp_state { + uint32_t is_enabled; +@@ -190,12 +184,8 @@ struct dpp_funcs { + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + enum dc_color_space input_color_space, + struct cnv_alpha_2bit_lut *alpha_2bit_lut); +-#else +- enum dc_color_space input_color_space); +-#endif + + void (*dpp_full_bypass)(struct dpp *dpp_base); + +@@ -224,7 +214,6 @@ struct dpp_funcs { + bool dppclk_div, + bool enable); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool (*dpp_program_blnd_lut)( + struct dpp *dpp, + const struct pwl_params *params); +@@ -237,7 +226,6 @@ struct dpp_funcs { + void (*dpp_cnv_set_alpha_keyer)( + struct dpp *dpp_base, + struct cnv_color_keyer_params *color_keyer); +-#endif + }; + + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h +index c6ff3d78b435..c59740084ebc 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h +@@ -22,7 +22,6 @@ + * Authors: AMD + * + */ +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #ifndef __DAL_DSC_H__ + #define __DAL_DSC_H__ + +@@ -98,4 +97,3 @@ struct dsc_funcs { + }; + + #endif +-#endif +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h +index ff1a07b35c85..aed67754e81b 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h +@@ -51,11 +51,7 @@ enum dwb_source { + dwb_src_otg3, /* for DCN1.x/DCN2.x */ + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* DCN1.x, DCN2.x support 2 pipes */ +-#else +-/* DCN1.x supports 2 pipes */ +-#endif + enum dwb_pipe { + dwb_pipe0 = 0, + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) +@@ -64,7 +60,6 @@ enum dwb_pipe { + dwb_pipe_max_num, + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + enum dwb_frame_capture_enable { + DWB_FRAME_CAPTURE_DISABLE = 0, + DWB_FRAME_CAPTURE_ENABLE = 1, +@@ -77,9 +72,7 @@ enum wbscl_coef_filter_type_sel { + WBSCL_COEF_CHROMA_HORZ_FILTER = 3 + }; + +-#endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dwb_warmup_params { + bool warmup_en; /* false: normal mode, true: enable pattern generator */ + bool warmup_mode; /* false: 420, true: 444 */ +@@ -88,7 +81,6 @@ struct dwb_warmup_params { + int warmup_width; /* Pattern width (pixels) */ + int warmup_height; /* Pattern height (lines) */ + }; +-#endif + + struct dwb_caps { + enum dce_version hw_version; /* DCN engine version. */ +@@ -150,13 +142,11 @@ struct dwbc_funcs { + struct dwbc *dwbc, + bool is_new_content); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + void (*set_warmup)( + struct dwbc *dwbc, + struct dwb_warmup_params *warmup_params); + +-#endif + + bool (*get_dwb_status)( + struct dwbc *dwbc); +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +index 9def990d40a6..9793da0f3c7e 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +@@ -38,9 +38,7 @@ enum cursor_pitch { + }; + + enum cursor_lines_per_chunk { +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + CURSOR_LINE_PER_CHUNK_1 = 0, /* new for DCN2 */ +-#endif + CURSOR_LINE_PER_CHUNK_2 = 1, + CURSOR_LINE_PER_CHUNK_4, + CURSOR_LINE_PER_CHUNK_8, +@@ -139,7 +137,6 @@ struct hubp_funcs { + unsigned int (*hubp_get_underflow_status)(struct hubp *hubp); + void (*hubp_init)(struct hubp *hubp); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void (*dmdata_set_attributes)( + struct hubp *hubp, + const struct dc_dmdata_attributes *attr); +@@ -159,7 +156,6 @@ struct hubp_funcs { + void (*hubp_set_flip_control_surface_gsl)( + struct hubp *hubp, + bool enable); +-#endif + + void (*validate_dml_output)( + struct hubp *hubp, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +index 91fda51e5370..75d419081e76 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +@@ -36,9 +36,7 @@ + + #define MAX_AUDIOS 7 + #define MAX_PIPES 6 +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define MAX_DWB_PIPES 1 +-#endif + + struct gamma_curve { + uint32_t offset; +@@ -81,7 +79,6 @@ struct pwl_result_data { + uint32_t delta_blue_reg; + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_rgb { + uint32_t red; + uint32_t green; +@@ -110,7 +107,6 @@ struct tetrahedral_params { + bool use_12bits; + + }; +-#endif + + /* arr_curve_points - regamma regions/segments specification + * arr_points - beginning and end point specified separately (only one on DCE) +@@ -195,13 +191,11 @@ enum opp_regamma { + OPP_REGAMMA_USER + }; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + enum optc_dsc_mode { + OPTC_DSC_DISABLED = 0, + OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */ + OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */ + }; +-#endif + + struct dc_bias_and_scale { + uint16_t scale_red; +@@ -224,12 +218,8 @@ enum test_pattern_mode { + TEST_PATTERN_MODE_VERTICALBARS, + TEST_PATTERN_MODE_HORIZONTALBARS, + TEST_PATTERN_MODE_SINGLERAMP_RGB, +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + TEST_PATTERN_MODE_DUALRAMP_RGB, + TEST_PATTERN_MODE_XR_BIAS_RGB +-#else +- TEST_PATTERN_MODE_DUALRAMP_RGB +-#endif + }; + + enum test_pattern_color_format { +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +index af57751ed8a1..fb748f082c56 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +@@ -113,12 +113,9 @@ struct link_encoder { + struct encoder_feature_support features; + enum transmitter transmitter; + enum hpd_source_id hpd_source; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + bool usbc_combo_phy; +-#endif + }; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct link_enc_state { + + uint32_t dphy_fec_en; +@@ -127,13 +124,10 @@ struct link_enc_state { + uint32_t dp_link_training_complete; + + }; +-#endif + + struct link_encoder_funcs { +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + void (*read_state)( + struct link_encoder *enc, struct link_enc_state *s); +-#endif + bool (*validate_output_with_stream)( + struct link_encoder *enc, const struct dc_stream_state *stream); + void (*hw_init)(struct link_encoder *enc); +@@ -175,7 +169,6 @@ struct link_encoder_funcs { + unsigned int (*get_dig_frontend)(struct link_encoder *enc); + void (*destroy)(struct link_encoder **enc); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void (*fec_set_enable)(struct link_encoder *enc, + bool enable); + +@@ -183,7 +176,6 @@ struct link_encoder_funcs { + bool ready); + + bool (*fec_is_active)(struct link_encoder *enc); +-#endif + bool (*is_in_alt_mode) (struct link_encoder *enc); + + void (*get_max_link_cap)(struct link_encoder *enc, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +index 58826be81395..094afc4c8173 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +@@ -31,9 +31,7 @@ + #define MAX_MPCC 6 + #define MAX_OPP 6 + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define MAX_DWB 1 +-#endif + + enum mpc_output_csc_mode { + MPC_OUTPUT_CSC_DISABLE = 0, +@@ -66,14 +64,12 @@ struct mpcc_blnd_cfg { + int global_alpha; + bool overlap_only; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* MPCC top/bottom gain settings */ + int bottom_gain_mode; + int background_color_bpc; + int top_gain; + int bottom_inside_gain; + int bottom_outside_gain; +-#endif + }; + + struct mpcc_sm_cfg { +@@ -90,7 +86,6 @@ struct mpcc_sm_cfg { + int force_next_field_polarity; + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct mpc_denorm_clamp { + int clamp_max_r_cr; + int clamp_min_r_cr; +@@ -99,7 +94,6 @@ struct mpc_denorm_clamp { + int clamp_max_b_cb; + int clamp_min_b_cb; + }; +-#endif + + /* + * MPCC connection and blending configuration for a single MPCC instance. +@@ -126,10 +120,8 @@ struct mpc { + struct dc_context *ctx; + + struct mpcc mpcc_array[MAX_MPCC]; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct pwl_params blender_params; + bool cm_bypass_mode; +-#endif + }; + + struct mpcc_state { +@@ -230,7 +222,6 @@ struct mpc_funcs { + struct mpc *mpc, + struct mpc_tree *tree); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void (*set_denorm)(struct mpc *mpc, + int opp_id, + enum dc_color_depth output_depth); +@@ -258,7 +249,6 @@ struct mpc_funcs { + struct mpc *mpc, + int mpcc_id, + bool power_on); +-#endif + + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +index b01ff30145fd..7575564b2265 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +@@ -263,9 +263,7 @@ struct oppbuf_params { + enum oppbuf_display_segmentation mso_segmentation; + uint32_t mso_overlap_pixel_num; + uint32_t pixel_repetition; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + uint32_t num_segment_padded_pixels; +-#endif + }; + + struct opp_funcs { +@@ -305,7 +303,6 @@ struct opp_funcs { + struct output_pixel_processor *opp, + bool enable); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void (*opp_set_disp_pattern_generator)( + struct output_pixel_processor *opp, + enum controller_dp_test_pattern test_pattern, +@@ -325,7 +322,6 @@ struct opp_funcs { + void (*opp_program_left_edge_extra_pixel)( + struct output_pixel_processor *opp, + bool count); +-#endif + + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +index c0b93d51ca8d..351b387ad606 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +@@ -65,13 +65,11 @@ struct audio_clock_info { + uint32_t cts_48khz; + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + enum dynamic_metadata_mode { + dmdata_dp, + dmdata_hdmi, + dmdata_dolby_vision + }; +-#endif + + struct encoder_info_frame { + /* auxiliary video information */ +@@ -90,9 +88,7 @@ struct encoder_info_frame { + struct encoder_unblank_param { + struct dc_link_settings link_settings; + struct dc_crtc_timing timing; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + int opp_cnt; +-#endif + }; + + struct encoder_set_dp_phy_pattern_param { +@@ -109,7 +105,6 @@ struct stream_encoder { + enum engine_id id; + }; + +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct enc_state { + uint32_t dsc_mode; // DISABLED 0; 1 or 2 indicate enabled state. + uint32_t dsc_slice_width; +@@ -119,7 +114,6 @@ struct enc_state { + uint32_t sec_gsp_pps_enable; + uint32_t sec_stream_enable; + }; +-#endif + + struct stream_encoder_funcs { + void (*dp_set_stream_attribute)( +@@ -220,8 +214,6 @@ struct stream_encoder_funcs { + enum dc_pixel_encoding *encoding, + enum dc_color_depth *depth); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s); + + void (*dp_set_dsc_config)( +@@ -233,7 +225,6 @@ struct stream_encoder_funcs { + void (*dp_set_dsc_pps_info_packet)(struct stream_encoder *enc, + bool enable, + uint8_t *dsc_packed_pps); +-#endif + + void (*set_dynamic_metadata)(struct stream_encoder *enc, + bool enable, +@@ -243,7 +234,6 @@ struct stream_encoder_funcs { + void (*dp_set_odm_combine)( + struct stream_encoder *enc, + bool odm_combine); +-#endif + }; + + #endif /* STREAM_ENCODER_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +index 27c73caf74ee..2d3efd71fa51 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +@@ -195,10 +195,8 @@ struct timing_generator_funcs { + void (*lock)(struct timing_generator *tg); + void (*lock_doublebuffer_disable)(struct timing_generator *tg); + void (*lock_doublebuffer_enable)(struct timing_generator *tg); +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void(*triplebuffer_unlock)(struct timing_generator *tg); + void(*triplebuffer_lock)(struct timing_generator *tg); +-#endif + void (*enable_reset_trigger)(struct timing_generator *tg, + int source_tg_inst); + void (*enable_crtc_reset)(struct timing_generator *tg, +@@ -235,7 +233,6 @@ struct timing_generator_funcs { + bool (*is_optc_underflow_occurred)(struct timing_generator *tg); + void (*clear_optc_underflow)(struct timing_generator *tg); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void (*set_dwb_source)(struct timing_generator *optc, + uint32_t dwb_pipe_inst); + +@@ -243,7 +240,6 @@ struct timing_generator_funcs { + uint32_t *num_of_input_segments, + uint32_t *seg0_src_sel, + uint32_t *seg1_src_sel); +-#endif + + /** + * Configure CRCs for the given timing generator. Return false if TG is +@@ -267,13 +263,10 @@ struct timing_generator_funcs { + void (*set_vtg_params)(struct timing_generator *optc, + const struct dc_crtc_timing *dc_crtc_timing); + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + void (*set_dsc_config)(struct timing_generator *optc, + enum optc_dsc_mode dsc_mode, + uint32_t dsc_bytes_per_pixel, + uint32_t dsc_slice_width); +-#endif + void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); + void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, + struct dc_crtc_timing *timing); +@@ -281,7 +274,6 @@ struct timing_generator_funcs { + void (*set_gsl_source_select)(struct timing_generator *optc, + int group_idx, + uint32_t gsl_ready_signal); +-#endif + }; + + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +index d39c1e11def5..23e3a541b7c9 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +@@ -66,19 +66,15 @@ struct dce_hwseq { + + struct pipe_ctx; + struct dc_state; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_stream_status; + struct dc_writeback_info; +-#endif + struct dchub_init_data; + struct dc_static_screen_events; + struct resource_pool; + struct resource_context; + struct stream_resource; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct dc_phy_addr_space_config; + struct dc_virtual_addr_space_config; +-#endif + struct hubp; + struct dpp; + +@@ -113,7 +109,6 @@ struct hw_sequencer_funcs { + uint16_t *matrix, + int opp_id); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void (*program_front_end_for_ctx)( + struct dc *dc, + struct dc_state *context); +@@ -124,7 +119,6 @@ struct hw_sequencer_funcs { + void (*set_flip_control_gsl)( + struct pipe_ctx *pipe_ctx, + bool flip_immediate); +-#endif + + void (*update_plane_addr)( + const struct dc *dc, +@@ -138,7 +132,6 @@ struct hw_sequencer_funcs { + struct dce_hwseq *hws, + struct dchub_init_data *dh_data); + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + int (*init_sys_ctx)( + struct dce_hwseq *hws, + struct dc *dc, +@@ -148,7 +141,6 @@ struct hw_sequencer_funcs { + struct dc *dc, + struct dc_virtual_addr_space_config *va_config, + int vmid); +-#endif + void (*update_mpcc)( + struct dc *dc, + struct pipe_ctx *pipe_ctx); +@@ -239,13 +231,11 @@ struct hw_sequencer_funcs { + const struct dc *dc, + struct dc_state *context); + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool (*update_bandwidth)( + struct dc *dc, + struct dc_state *context); + void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); + bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); +-#endif + + void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, + unsigned int vmin, unsigned int vmax, +@@ -323,7 +313,6 @@ struct hw_sequencer_funcs { + bool power_on); + + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); + void (*program_all_writeback_pipes_in_tree)( + struct dc *dc, +@@ -339,7 +328,6 @@ struct hw_sequencer_funcs { + struct dc_state *context); + void (*disable_writeback)(struct dc *dc, + unsigned int dwb_pipe_inst); +-#endif + enum dc_status (*set_clock)(struct dc *dc, + enum dc_clock_type clock_type, + uint32_t clk_khz, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h +index bef224bf803e..7a85abc53d05 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h +@@ -46,12 +46,8 @@ struct resource_caps { + int num_pll; + int num_dwb; + int num_ddc; +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + int num_vmid; +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + int num_dsc; +-#endif +-#endif + }; + + struct resource_straps { +diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile +index ea75420fc876..75db39691616 100644 +--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile +@@ -66,11 +66,9 @@ IRQ_DCN1 = irq_service_dcn10.o + AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1)) + + AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN1) +-endif + ############################################################################### + # DCN 20 + ############################################################################### +-ifdef CONFIG_DRM_AMD_DC_DCN2_0 + IRQ_DCN2 = irq_service_dcn20.o + + AMD_DAL_IRQ_DCN2 = $(addprefix $(AMDDALPATH)/dc/irq/dcn20/,$(IRQ_DCN2)) +diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +index b37db73478eb..2d7c298cf5d2 100644 +--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +@@ -80,22 +80,14 @@ static void virtual_stream_encoder_reset_hdmi_stream_attribute( + struct stream_encoder *enc) + {} + +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + static void virtual_enc_dp_set_odm_combine( + struct stream_encoder *enc, + bool odm_combine) + {} +-#endif +-#endif + + static const struct stream_encoder_funcs virtual_str_enc_funcs = { +-#ifdef CONFIG_DRM_AMD_DC_DCN2_0 +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + .dp_set_odm_combine = + virtual_enc_dp_set_odm_combine, +-#endif +-#endif + .dp_set_stream_attribute = + virtual_stream_encoder_dp_set_stream_attribute, + .hdmi_set_stream_attribute = +diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h +index 68e8f6378d40..d51fe99349ed 100644 +--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h ++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h +@@ -149,7 +149,6 @@ + + #define FAMILY_RV 142 /* DCN 1*/ + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + #define FAMILY_NV 143 /* DCN 2*/ + +@@ -163,7 +162,6 @@ enum { + #define ASICREV_IS_NAVI10_P(eChipRev) (eChipRev < NV_NAVI12_P_A0) + #define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0)) + #define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + #define RENOIR_A0 0x91 + #define DEVICE_ID_RENOIR_1636 0x1636 // Renoir +diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h +index fcc42372b6cf..2db5d4f60ac3 100644 +--- a/drivers/gpu/drm/amd/display/include/dal_types.h ++++ b/drivers/gpu/drm/amd/display/include/dal_types.h +@@ -46,9 +46,7 @@ enum dce_version { + DCE_VERSION_MAX, + DCN_VERSION_1_0, + DCN_VERSION_1_01, +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + DCN_VERSION_2_0, +-#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + DCN_VERSION_2_1, + #endif +diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h +index 2b219cdb13ad..89a709267019 100644 +--- a/drivers/gpu/drm/amd/display/include/logger_types.h ++++ b/drivers/gpu/drm/amd/display/include/logger_types.h +@@ -66,12 +66,8 @@ + #define DC_LOG_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__) + #define DC_LOG_ALL_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__) + #define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__) +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #define DC_LOG_DSC(...) DRM_DEBUG_KMS(__VA_ARGS__) +-#endif +-#if defined(CONFIG_DRM_AMD_DC_DCN3_0) || defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define DC_LOG_DWB(...) DRM_DEBUG_KMS(__VA_ARGS__) +-#endif + + struct dal_logger; + +@@ -116,9 +112,7 @@ enum dc_log_type { + LOG_PERF_TRACE, + LOG_DISPLAYSTATS, + LOG_HDMI_RETIMER_REDRIVER, +-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + LOG_DSC, +-#endif + LOG_DWB, + LOG_GAMMA_DEBUG, + LOG_MAX_HW_POINTS, +diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h +index b45f7d65e76a..fe2117904329 100644 +--- a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h ++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h +@@ -45,7 +45,6 @@ enum vrr_packet_type { + PACKET_TYPE_VTEM + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + union lut3d_control_flags { + unsigned int raw; + struct { +@@ -104,6 +103,5 @@ struct lut3d_settings { + enum lut3d_control_gamut_map map2; + enum lut3d_control_rotation_mode rotation2; + }; +-#endif + + #endif /* MOD_SHARED_H_ */ +-- +2.17.1 + |