diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch | 795 |
1 files changed, 795 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch new file mode 100644 index 00000000..4903443e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch @@ -0,0 +1,795 @@ +From 83f4f8104261c5f2877e3b21909ed8a9d49a59c3 Mon Sep 17 00:00:00 2001 +From: Jaehyun Chung <jaehyun.chung@amd.com> +Date: Thu, 31 Oct 2019 15:53:24 -0400 +Subject: [PATCH 4495/4736] drm/amd/display: DML Validation Dump/Check with + Logging + +[Why] +Need validation that we are programming the expected values (rq, ttu, dlg) +from DML. This debug feature will output logs if we are programming +incorrect values and may help differentiate DAL issues from HW issues. + +[How] +Dump relevant registers for each pipe with active stream. Compare current +reg values with the converted DML output. Log mismatches when found. + +Change-Id: I42f3f19de1f0330ddb2c0c877aa32cd7798205b0 +Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> +Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> +Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 18 +- + drivers/gpu/drm/amd/display/dc/dc.h | 1 + + .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 310 ++++++++++++++++ + .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 345 ++++++++++++++++++ + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 7 + + 5 files changed, 680 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 66ddc2443e1e..81f4499490b9 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -2198,8 +2198,24 @@ static void commit_planes_for_stream(struct dc *dc, + } + } + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) +- if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) ++ if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) { + dc->hwss.program_front_end_for_ctx(dc, context); ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 ++ if (dc->debug.validate_dml_output) { ++ for (i = 0; i < dc->res_pool->pipe_count; i++) { ++ struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i]; ++ if (cur_pipe.stream == NULL) ++ continue; ++ ++ cur_pipe.plane_res.hubp->funcs->validate_dml_output( ++ cur_pipe.plane_res.hubp, dc->ctx, ++ &context->res_ctx.pipe_ctx[i].rq_regs, ++ &context->res_ctx.pipe_ctx[i].dlg_regs, ++ &context->res_ctx.pipe_ctx[i].ttu_regs); ++ } ++ } ++#endif ++ } + #endif + + // Update Type FAST, Surface updates +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 8af7014b1588..bc422728dd54 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -424,6 +424,7 @@ struct dc_debug_options { + + bool nv12_iflip_vm_wa; + bool disable_dram_clock_change_vactive_support; ++ bool validate_dml_output; + }; + + struct dc_debug_data { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +index 391f0629b955..4c60fa4b89e7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +@@ -30,6 +30,8 @@ + #include "reg_helper.h" + #include "basics/conversion.h" + ++#define DC_LOGGER_INIT(logger) ++ + #define REG(reg)\ + hubp2->hubp_regs->reg + +@@ -1246,6 +1248,313 @@ void hubp2_read_state(struct hubp *hubp) + + } + ++void hubp2_validate_dml_output(struct hubp *hubp, ++ struct dc_context *ctx, ++ struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, ++ struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, ++ struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) ++{ ++ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); ++ struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; ++ struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; ++ struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; ++ DC_LOGGER_INIT(ctx->logger); ++ ++ /* Requestor Regs */ ++ REG_GET(HUBPRET_CONTROL, ++ DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); ++ REG_GET_4(DCN_EXPANSION_MODE, ++ DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, ++ PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, ++ MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, ++ CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); ++ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, ++ CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, ++ MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, ++ META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, ++ MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, ++ DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, ++ MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, ++ SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, ++ PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); ++ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, ++ CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, ++ MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, ++ META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, ++ MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, ++ DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, ++ MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size, ++ SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, ++ PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); ++ ++ if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) ++ DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", ++ dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); ++ if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) ++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", ++ dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); ++ if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) ++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", ++ dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); ++ if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) ++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", ++ dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); ++ if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) ++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", ++ dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); ++ ++ if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); ++ if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); ++ if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); ++ if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); ++ if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); ++ if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); ++ if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); ++ if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); ++ ++ if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); ++ if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); ++ if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); ++ if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); ++ if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); ++ if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size); ++ if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); ++ if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); ++ ++ /* DLG - Per hubp */ ++ REG_GET_2(BLANK_OFFSET_0, ++ REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, ++ DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); ++ REG_GET(BLANK_OFFSET_1, ++ MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); ++ REG_GET(DST_DIMENSIONS, ++ REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); ++ REG_GET_2(DST_AFTER_SCALER, ++ REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, ++ DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); ++ REG_GET(REF_FREQ_TO_PIX_FREQ, ++ REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); ++ ++ if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) ++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); ++ if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) ++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); ++ if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) ++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", ++ dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); ++ if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) ++ DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); ++ if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) ++ DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); ++ if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) ++ DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); ++ if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) ++ DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", ++ dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); ++ ++ /* DLG - Per luma/chroma */ ++ REG_GET(VBLANK_PARAMETERS_1, ++ REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); ++ if (REG(NOM_PARAMETERS_0)) ++ REG_GET(NOM_PARAMETERS_0, ++ DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); ++ if (REG(NOM_PARAMETERS_1)) ++ REG_GET(NOM_PARAMETERS_1, ++ REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); ++ REG_GET(NOM_PARAMETERS_4, ++ DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); ++ REG_GET(NOM_PARAMETERS_5, ++ REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); ++ REG_GET_2(PER_LINE_DELIVERY, ++ REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, ++ REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); ++ REG_GET_2(PER_LINE_DELIVERY_PRE, ++ REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, ++ REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); ++ REG_GET(VBLANK_PARAMETERS_2, ++ REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); ++ if (REG(NOM_PARAMETERS_2)) ++ REG_GET(NOM_PARAMETERS_2, ++ DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); ++ if (REG(NOM_PARAMETERS_3)) ++ REG_GET(NOM_PARAMETERS_3, ++ REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); ++ REG_GET(NOM_PARAMETERS_6, ++ DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); ++ REG_GET(NOM_PARAMETERS_7, ++ REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); ++ REG_GET(VBLANK_PARAMETERS_3, ++ REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); ++ REG_GET(VBLANK_PARAMETERS_4, ++ REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); ++ ++ if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); ++ if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); ++ if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); ++ if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); ++ if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); ++ if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) ++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); ++ if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) ++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); ++ if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); ++ if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); ++ if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); ++ if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); ++ if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); ++ if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) ++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); ++ if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) ++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); ++ if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); ++ if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); ++ ++ /* TTU - per hubp */ ++ REG_GET_2(DCN_TTU_QOS_WM, ++ QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, ++ QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); ++ ++ if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) ++ DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); ++ if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) ++ DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); ++ ++ /* TTU - per luma/chroma */ ++ /* Assumed surf0 is luma and 1 is chroma */ ++ REG_GET_3(DCN_SURF0_TTU_CNTL0, ++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, ++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, ++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); ++ REG_GET_3(DCN_SURF1_TTU_CNTL0, ++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, ++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, ++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); ++ REG_GET_3(DCN_CUR0_TTU_CNTL0, ++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, ++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, ++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); ++ REG_GET(FLIP_PARAMETERS_1, ++ REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); ++ REG_GET(DCN_CUR0_TTU_CNTL1, ++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); ++ REG_GET(DCN_CUR1_TTU_CNTL1, ++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); ++ REG_GET(DCN_SURF0_TTU_CNTL1, ++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); ++ REG_GET(DCN_SURF1_TTU_CNTL1, ++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); ++ ++ if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); ++ if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); ++ if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); ++ if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); ++ if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); ++ if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); ++ if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); ++ if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); ++ if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); ++ if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) ++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); ++ if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); ++ if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); ++ if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); ++ if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); ++} ++ + static struct hubp_funcs dcn20_hubp_funcs = { + .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, + .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, +@@ -1269,6 +1578,7 @@ static struct hubp_funcs dcn20_hubp_funcs = { + .hubp_clear_underflow = hubp2_clear_underflow, + .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, + .hubp_init = hubp1_init, ++ .validate_dml_output = hubp2_validate_dml_output, + }; + + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c +index 32e8b589aeb5..0be1c917b242 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c +@@ -29,6 +29,8 @@ + #include "dm_services.h" + #include "reg_helper.h" + ++#define DC_LOGGER_INIT(logger) ++ + #define REG(reg)\ + hubp21->hubp_regs->reg + +@@ -254,6 +256,348 @@ void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, + SYSTEM_ACCESS_MODE, 0x3); + } + ++void hubp21_validate_dml_output(struct hubp *hubp, ++ struct dc_context *ctx, ++ struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, ++ struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, ++ struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) ++{ ++ struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); ++ struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; ++ struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; ++ struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; ++ DC_LOGGER_INIT(ctx->logger); ++ ++ /* Requester - Per hubp */ ++ REG_GET(HUBPRET_CONTROL, ++ DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); ++ REG_GET_4(DCN_EXPANSION_MODE, ++ DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, ++ PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, ++ MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, ++ CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); ++ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, ++ CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, ++ MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, ++ META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, ++ MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, ++ DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, ++ VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, ++ SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, ++ PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); ++ REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, ++ CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, ++ MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, ++ META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, ++ MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, ++ DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, ++ SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, ++ PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); ++ ++ if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) ++ DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", ++ dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); ++ if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) ++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", ++ dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); ++ if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) ++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", ++ dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); ++ if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) ++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", ++ dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); ++ if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) ++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", ++ dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); ++ ++ if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); ++ if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); ++ if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); ++ if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); ++ if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); ++ if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); ++ if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); ++ if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); ++ ++ if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); ++ if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); ++ if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); ++ if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); ++ if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); ++ if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); ++ if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) ++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", ++ dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); ++ ++ ++ /* DLG - Per hubp */ ++ REG_GET_2(BLANK_OFFSET_0, ++ REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, ++ DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); ++ REG_GET(BLANK_OFFSET_1, ++ MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); ++ REG_GET(DST_DIMENSIONS, ++ REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); ++ REG_GET_2(DST_AFTER_SCALER, ++ REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, ++ DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); ++ REG_GET(REF_FREQ_TO_PIX_FREQ, ++ REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); ++ ++ if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) ++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); ++ if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) ++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); ++ if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) ++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", ++ dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); ++ if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) ++ DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); ++ if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) ++ DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); ++ if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) ++ DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); ++ if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) ++ DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", ++ dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); ++ ++ /* DLG - Per luma/chroma */ ++ REG_GET(VBLANK_PARAMETERS_1, ++ REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); ++ if (REG(NOM_PARAMETERS_0)) ++ REG_GET(NOM_PARAMETERS_0, ++ DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); ++ if (REG(NOM_PARAMETERS_1)) ++ REG_GET(NOM_PARAMETERS_1, ++ REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); ++ REG_GET(NOM_PARAMETERS_4, ++ DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); ++ REG_GET(NOM_PARAMETERS_5, ++ REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); ++ REG_GET_2(PER_LINE_DELIVERY, ++ REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, ++ REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); ++ REG_GET_2(PER_LINE_DELIVERY_PRE, ++ REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, ++ REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); ++ REG_GET(VBLANK_PARAMETERS_2, ++ REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); ++ if (REG(NOM_PARAMETERS_2)) ++ REG_GET(NOM_PARAMETERS_2, ++ DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); ++ if (REG(NOM_PARAMETERS_3)) ++ REG_GET(NOM_PARAMETERS_3, ++ REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); ++ REG_GET(NOM_PARAMETERS_6, ++ DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); ++ REG_GET(NOM_PARAMETERS_7, ++ REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); ++ REG_GET(VBLANK_PARAMETERS_3, ++ REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); ++ REG_GET(VBLANK_PARAMETERS_4, ++ REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); ++ ++ if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); ++ if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); ++ if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); ++ if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); ++ if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); ++ if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) ++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); ++ if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) ++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); ++ if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); ++ if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); ++ if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); ++ if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); ++ if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) ++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); ++ if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) ++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); ++ if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) ++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); ++ if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); ++ if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); ++ ++ /* TTU - per hubp */ ++ REG_GET_2(DCN_TTU_QOS_WM, ++ QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, ++ QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); ++ ++ if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) ++ DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); ++ if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) ++ DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); ++ ++ /* TTU - per luma/chroma */ ++ /* Assumed surf0 is luma and 1 is chroma */ ++ REG_GET_3(DCN_SURF0_TTU_CNTL0, ++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, ++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, ++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); ++ REG_GET_3(DCN_SURF1_TTU_CNTL0, ++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, ++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, ++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); ++ REG_GET_3(DCN_CUR0_TTU_CNTL0, ++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, ++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, ++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); ++ REG_GET(FLIP_PARAMETERS_1, ++ REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); ++ REG_GET(DCN_CUR0_TTU_CNTL1, ++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); ++ REG_GET(DCN_CUR1_TTU_CNTL1, ++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); ++ REG_GET(DCN_SURF0_TTU_CNTL1, ++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); ++ REG_GET(DCN_SURF1_TTU_CNTL1, ++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); ++ ++ if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); ++ if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); ++ if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); ++ if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); ++ if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); ++ if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); ++ if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); ++ if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); ++ if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); ++ if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) ++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); ++ if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); ++ if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) ++ DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); ++ if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); ++ if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) ++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", ++ dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); ++ ++ /* Host VM deadline regs */ ++ REG_GET(VBLANK_PARAMETERS_5, ++ REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); ++ REG_GET(VBLANK_PARAMETERS_6, ++ REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); ++ REG_GET(FLIP_PARAMETERS_3, ++ REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); ++ REG_GET(FLIP_PARAMETERS_4, ++ REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); ++ REG_GET(FLIP_PARAMETERS_5, ++ REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); ++ REG_GET(FLIP_PARAMETERS_6, ++ REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); ++ REG_GET(FLIP_PARAMETERS_2, ++ REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); ++ ++ if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); ++ if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) ++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); ++ if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) ++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); ++ if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) ++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); ++ if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) ++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); ++ if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) ++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); ++ if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) ++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", ++ dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); ++} ++ + void hubp21_init(struct hubp *hubp) + { + // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta +@@ -286,6 +630,7 @@ static struct hubp_funcs dcn21_hubp_funcs = { + .hubp_clear_underflow = hubp1_clear_underflow, + .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, + .hubp_init = hubp21_init, ++ .validate_dml_output = hubp21_validate_dml_output, + }; + + bool hubp21_construct( +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +index 809b62b51a43..9def990d40a6 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +@@ -161,6 +161,13 @@ struct hubp_funcs { + bool enable); + #endif + ++ void (*validate_dml_output)( ++ struct hubp *hubp, ++ struct dc_context *ctx, ++ struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, ++ struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, ++ struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr); ++ + }; + + #endif +-- +2.17.1 + |