diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch | 177 |
1 files changed, 177 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch new file mode 100644 index 00000000..1d3c19c2 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch @@ -0,0 +1,177 @@ +From fd3e1f0031707e8ae09a39c90519d483c1e1ffce Mon Sep 17 00:00:00 2001 +From: Leo Liu <leo.liu@amd.com> +Date: Mon, 11 Nov 2019 15:09:25 -0500 +Subject: [PATCH 4452/4736] drm/amdgpu: add PG and CG for JPEG2.0 + +And enable them for Navi1x and Renoir + +Signed-off-by: Leo Liu <leo.liu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 62 +++++++++++++++----------- + drivers/gpu/drm/amd/amdgpu/nv.c | 8 +++- + drivers/gpu/drm/amd/amdgpu/soc15.c | 2 + + 3 files changed, 45 insertions(+), 27 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +index 4143ef6905b8..3869730b2331 100644 +--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +@@ -227,16 +227,18 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev) + uint32_t data; + int r = 0; + +- data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; +- WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); +- +- SOC15_WAIT_ON_RREG(JPEG, 0, +- mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, +- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); +- +- if (r) { +- DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); +- return r; ++ if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { ++ data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; ++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); ++ ++ SOC15_WAIT_ON_RREG(JPEG, 0, ++ mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, ++ UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); ++ ++ if (r) { ++ DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); ++ return r; ++ } + } + + /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */ +@@ -248,24 +250,26 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev) + + static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev) + { +- uint32_t data; +- int r = 0; ++ if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { ++ uint32_t data; ++ int r = 0; + +- data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)); +- data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; +- data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; +- WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); ++ data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)); ++ data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; ++ data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; ++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); + +- data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; +- WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); ++ data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; ++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); + +- SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, +- (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), +- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); ++ SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, ++ (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), ++ UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); + +- if (r) { +- DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); +- return r; ++ if (r) { ++ DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); ++ return r; ++ } + } + + return 0; +@@ -276,7 +280,10 @@ static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device* adev) + uint32_t data; + + data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); +- data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; ++ if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) ++ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; ++ else ++ data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + + data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; + data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; +@@ -296,7 +303,10 @@ static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device* adev) + uint32_t data; + + data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); +- data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; ++ if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) ++ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; ++ else ++ data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + + data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; + data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; +diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c +index be761785b2a8..0b8aedfe1b67 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nv.c ++++ b/drivers/gpu/drm/amd/amdgpu/nv.c +@@ -642,10 +642,12 @@ static int nv_common_early_init(void *handle) + AMD_CG_SUPPORT_ATHUB_MGCG | + AMD_CG_SUPPORT_ATHUB_LS | + AMD_CG_SUPPORT_VCN_MGCG | ++ AMD_CG_SUPPORT_JPEG_MGCG | + AMD_CG_SUPPORT_BIF_MGCG | + AMD_CG_SUPPORT_BIF_LS; + adev->pg_flags = AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG | ++ AMD_PG_SUPPORT_JPEG | + AMD_PG_SUPPORT_ATHUB; + adev->external_rev_id = adev->rev_id + 0x1; + break; +@@ -662,9 +664,11 @@ static int nv_common_early_init(void *handle) + AMD_CG_SUPPORT_ATHUB_MGCG | + AMD_CG_SUPPORT_ATHUB_LS | + AMD_CG_SUPPORT_VCN_MGCG | ++ AMD_CG_SUPPORT_JPEG_MGCG | + AMD_CG_SUPPORT_BIF_MGCG | + AMD_CG_SUPPORT_BIF_LS; + adev->pg_flags = AMD_PG_SUPPORT_VCN | ++ AMD_PG_SUPPORT_JPEG | + AMD_PG_SUPPORT_VCN_DPG; + adev->external_rev_id = adev->rev_id + 20; + break; +@@ -683,9 +687,11 @@ static int nv_common_early_init(void *handle) + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_ATHUB_MGCG | + AMD_CG_SUPPORT_ATHUB_LS | +- AMD_CG_SUPPORT_VCN_MGCG; ++ AMD_CG_SUPPORT_VCN_MGCG | ++ AMD_CG_SUPPORT_JPEG_MGCG; + adev->pg_flags = AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG | ++ AMD_PG_SUPPORT_JPEG | + AMD_PG_SUPPORT_ATHUB; + adev->external_rev_id = adev->rev_id + 0xa; + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 836a34c10db2..233d3850789e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -1231,12 +1231,14 @@ static int soc15_common_early_init(void *handle) + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_ROM_MGCG | + AMD_CG_SUPPORT_VCN_MGCG | ++ AMD_CG_SUPPORT_JPEG_MGCG | + AMD_CG_SUPPORT_IH_CG | + AMD_CG_SUPPORT_ATHUB_LS | + AMD_CG_SUPPORT_ATHUB_MGCG | + AMD_CG_SUPPORT_DF_MGCG; + adev->pg_flags = AMD_PG_SUPPORT_SDMA | + AMD_PG_SUPPORT_VCN | ++ AMD_PG_SUPPORT_JPEG | + AMD_PG_SUPPORT_VCN_DPG; + adev->external_rev_id = adev->rev_id + 0x91; + break; +-- +2.17.1 + |