diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch new file mode 100644 index 00000000..d01a6942 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch @@ -0,0 +1,130 @@ +From 502b21ae7fe7e687739a5a14b15e738565a061ce Mon Sep 17 00:00:00 2001 +From: Kenneth Feng <kenneth.feng@amd.com> +Date: Fri, 8 Nov 2019 13:20:30 +0800 +Subject: [PATCH 4404/4736] drm/amd/powerplay: dynamically disable ds and ulv + for compute + +This is to improve the performance in the compute mode +for vega10. For example, the original performance for a rocm +bandwidth test: 2G internal GPU copy, is about 99GB/s. +With the idle power features disabled dynamically, the porformance +is promoted to about 215GB/s. + +Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> +Reviewed-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 8 +++ + .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 55 +++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 + + 3 files changed, 65 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +index 031447675203..7932eb163a00 100644 +--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c ++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +@@ -969,6 +969,14 @@ static int pp_dpm_switch_power_profile(void *handle, + workload = hwmgr->workload_setting[index]; + } + ++ if (type == PP_SMC_POWER_PROFILE_COMPUTE && ++ hwmgr->hwmgr_func->disable_power_features_for_compute_performance) { ++ if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) { ++ mutex_unlock(&hwmgr->smu_lock); ++ return -EINVAL; ++ } ++ } ++ + if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0); + mutex_unlock(&hwmgr->smu_lock); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index f62e320ed43d..8d933cb7e451 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -5262,6 +5262,59 @@ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_ + return 0; + } + ++static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable) ++{ ++ struct vega10_hwmgr *data = hwmgr->backend; ++ uint32_t feature_mask = 0; ++ ++ if (disable) { ++ feature_mask |= data->smu_features[GNLD_ULV].enabled ? ++ data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; ++ feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ? ++ data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; ++ feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ? ++ data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; ++ feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ? ++ data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; ++ feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ? ++ data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; ++ } else { ++ feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ? ++ data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; ++ feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ? ++ data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; ++ feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ? ++ data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; ++ feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ? ++ data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; ++ feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ? ++ data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; ++ } ++ ++ if (feature_mask) ++ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, ++ !disable, feature_mask), ++ "enable/disable power features for compute performance Failed!", ++ return -EINVAL); ++ ++ if (disable) { ++ data->smu_features[GNLD_ULV].enabled = false; ++ data->smu_features[GNLD_DS_GFXCLK].enabled = false; ++ data->smu_features[GNLD_DS_SOCCLK].enabled = false; ++ data->smu_features[GNLD_DS_LCLK].enabled = false; ++ data->smu_features[GNLD_DS_DCEFCLK].enabled = false; ++ } else { ++ data->smu_features[GNLD_ULV].enabled = true; ++ data->smu_features[GNLD_DS_GFXCLK].enabled = true; ++ data->smu_features[GNLD_DS_SOCCLK].enabled = true; ++ data->smu_features[GNLD_DS_LCLK].enabled = true; ++ data->smu_features[GNLD_DS_DCEFCLK].enabled = true; ++ } ++ ++ return 0; ++ ++} ++ + static const struct pp_hwmgr_func vega10_hwmgr_funcs = { + .backend_init = vega10_hwmgr_backend_init, + .backend_fini = vega10_hwmgr_backend_fini, +@@ -5328,6 +5381,8 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = { + .get_ppfeature_status = vega10_get_ppfeature_status, + .set_ppfeature_status = vega10_set_ppfeature_status, + .set_mp1_state = vega10_set_mp1_state, ++ .disable_power_features_for_compute_performance = ++ vega10_disable_power_features_for_compute_performance, + }; + + int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 40403bc76f1b..af977675fd33 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -357,6 +357,8 @@ struct pp_hwmgr_func { + int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire); + int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state); + int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate); ++ int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr, ++ bool disable); + }; + + struct pp_table_func { +-- +2.17.1 + |