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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch92
1 files changed, 92 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch
new file mode 100644
index 00000000..972ba138
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch
@@ -0,0 +1,92 @@
+From ba021ad1542c7c7c4e1739eb4b51d2288e729c43 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Wed, 25 Sep 2019 09:46:38 -0400
+Subject: [PATCH 4229/4736] drm/amd/display: add odm visual confirm
+
+[why]
+Hard to determine if pipe combine is done with MPC or ODM
+
+[how]
+Add new visual confirm type, this will mark each MPCC tree
+with a different color
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 1 +
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 25 +++++++++++++++++++
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 4 ++-
+ 3 files changed, 29 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 5967106826ca..b7e7181bad78 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -229,6 +229,7 @@ enum visual_confirm {
+ VISUAL_CONFIRM_DISABLE = 0,
+ VISUAL_CONFIRM_SURFACE = 1,
+ VISUAL_CONFIRM_HDR = 2,
++ VISUAL_CONFIRM_MPCTREE = 4,
+ };
+
+ enum dcc_option {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 6229a8ca0013..e237ec39d193 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1996,6 +1996,28 @@ static void dcn20_reset_hw_ctx_wrap(
+ }
+ }
+
++void dcn20_get_mpctree_visual_confirm_color(
++ struct pipe_ctx *pipe_ctx,
++ struct tg_color *color)
++{
++ const struct tg_color pipe_colors[6] = {
++ {MAX_TG_COLOR_VALUE, 0, 0}, // red
++ {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
++ {0, MAX_TG_COLOR_VALUE, 0}, // blue
++ {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
++ {0, 0, MAX_TG_COLOR_VALUE}, // green
++ {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
++ };
++
++ struct pipe_ctx *top_pipe = pipe_ctx;
++
++ while (top_pipe->top_pipe) {
++ top_pipe = top_pipe->top_pipe;
++ }
++
++ *color = pipe_colors[top_pipe->pipe_idx];
++}
++
+ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+@@ -2013,6 +2035,9 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+ dcn10_get_surface_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
++ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
++ dcn20_get_mpctree_visual_confirm_color(
++ pipe_ctx, &blnd_cfg.black_color);
+ }
+
+ if (per_pixel_alpha)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index 9dbc2effa4ea..3098f1049ed7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -109,5 +109,7 @@ bool dcn20_set_blend_lut(
+ struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+ bool dcn20_set_shaper_3dlut(
+ struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+-
++void dcn20_get_mpctree_visual_confirm_color(
++ struct pipe_ctx *pipe_ctx,
++ struct tg_color *color);
+ #endif /* __DC_HWSS_DCN20_H__ */
+--
+2.17.1
+