diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch new file mode 100644 index 00000000..4b56b5b0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch @@ -0,0 +1,63 @@ +From 77b8a13374bac1feff732bbbce9233abd5f65aef Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 2 Oct 2019 11:50:15 -0400 +Subject: [PATCH 4171/4736] drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + .../drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h +index be4249adb356..eddf83ec1c39 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h +@@ -9859,6 +9859,8 @@ + #define mmDP0_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP0_DP_MSA_MISC 0x210e + #define mmDP0_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f ++#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP0_DP_VID_TIMING 0x2110 + #define mmDP0_DP_VID_TIMING_BASE_IDX 2 + #define mmDP0_DP_VID_N 0x2111 +@@ -10187,6 +10189,8 @@ + #define mmDP1_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP1_DP_MSA_MISC 0x220e + #define mmDP1_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f ++#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP1_DP_VID_TIMING 0x2210 + #define mmDP1_DP_VID_TIMING_BASE_IDX 2 + #define mmDP1_DP_VID_N 0x2211 +@@ -10515,6 +10519,8 @@ + #define mmDP2_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP2_DP_MSA_MISC 0x230e + #define mmDP2_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f ++#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP2_DP_VID_TIMING 0x2310 + #define mmDP2_DP_VID_TIMING_BASE_IDX 2 + #define mmDP2_DP_VID_N 0x2311 +@@ -10843,6 +10849,8 @@ + #define mmDP3_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP3_DP_MSA_MISC 0x240e + #define mmDP3_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f ++#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP3_DP_VID_TIMING 0x2410 + #define mmDP3_DP_VID_TIMING_BASE_IDX 2 + #define mmDP3_DP_VID_N 0x2411 +@@ -11171,6 +11179,8 @@ + #define mmDP4_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP4_DP_MSA_MISC 0x250e + #define mmDP4_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f ++#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP4_DP_VID_TIMING 0x2510 + #define mmDP4_DP_VID_TIMING_BASE_IDX 2 + #define mmDP4_DP_VID_N 0x2511 +-- +2.17.1 + |