diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch new file mode 100644 index 00000000..3640ee54 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch @@ -0,0 +1,44 @@ +From ebcfe185bdd35b9616c29db859721ca3123c7933 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 4 Oct 2019 15:14:18 -0500 +Subject: [PATCH 4152/4736] drm/amdgpu: add new SMU 7.0.1 registers for BACO +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h +index dbc2e723f659..71169daa701a 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h +@@ -49,6 +49,7 @@ + #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 + #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 + #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 ++#define ixCG_SPLL_STATUS 0xC050015C + #define ixSPLL_CNTL_MODE 0xc0500160 + #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 + #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h +index 6af9f0217b34..61a9a84e0c3a 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h +@@ -194,6 +194,8 @@ + #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 ++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 ++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 + #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +-- +2.17.1 + |