diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch new file mode 100644 index 00000000..8804632e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch @@ -0,0 +1,144 @@ +From 38ff634117407a29df3b641470f954694492b934 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Thu, 10 Oct 2019 11:34:51 +0800 +Subject: [PATCH 4110/4736] drm/amd/powerplay: enable df cstate control on + powerplay routine + +Currently this is only supported on Vega20 with 40.50 and later +SMC firmware. + +Change-Id: I4f2f7936a3bc6e1a32d590bc76ebfc9a5a53f9cb +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> +--- + .../gpu/drm/amd/include/kgd_pp_interface.h | 6 ++++++ + drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++++++++++++++++++ + .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 19 +++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 + + .../gpu/drm/amd/powerplay/inc/vega20_ppsmc.h | 3 ++- + 5 files changed, 46 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h +index 27cf0afaa0b4..5902f80d1fce 100644 +--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h ++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h +@@ -179,6 +179,11 @@ enum pp_mp1_state { + PP_MP1_STATE_RESET, + }; + ++enum pp_df_cstate { ++ DF_CSTATE_DISALLOW = 0, ++ DF_CSTATE_ALLOW, ++}; ++ + #define PP_GROUP_MASK 0xF0000000 + #define PP_GROUP_SHIFT 28 + +@@ -312,6 +317,7 @@ struct amd_pm_funcs { + int (*get_ppfeature_status)(void *handle, char *buf); + int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); + int (*asic_reset_mode_2)(void *handle); ++ int (*set_df_cstate)(void *handle, enum pp_df_cstate state); + }; + + #endif +diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +index fa8ad7db2b3a..83196b79edd5 100644 +--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c ++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +@@ -1548,6 +1548,23 @@ static int pp_smu_i2c_bus_access(void *handle, bool acquire) + return ret; + } + ++static int pp_set_df_cstate(void *handle, enum pp_df_cstate state) ++{ ++ struct pp_hwmgr *hwmgr = handle; ++ ++ if (!hwmgr) ++ return -EINVAL; ++ ++ if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate) ++ return 0; ++ ++ mutex_lock(&hwmgr->smu_lock); ++ hwmgr->hwmgr_func->set_df_cstate(hwmgr, state); ++ mutex_unlock(&hwmgr->smu_lock); ++ ++ return 0; ++} ++ + static const struct amd_pm_funcs pp_dpm_funcs = { + .load_firmware = pp_dpm_load_fw, + .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, +@@ -1606,4 +1623,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = { + .set_ppfeature_status = pp_set_ppfeature_status, + .asic_reset_mode_2 = pp_asic_reset_mode_2, + .smu_i2c_bus_access = pp_smu_i2c_bus_access, ++ .set_df_cstate = pp_set_df_cstate, + }; +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index f5915308e643..6629c475fe5d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -4155,6 +4155,24 @@ static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire) + return res; + } + ++static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr, ++ enum pp_df_cstate state) ++{ ++ int ret; ++ ++ /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */ ++ if (hwmgr->smu_version < 0x283200) { ++ pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n"); ++ return -EINVAL; ++ } ++ ++ ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state); ++ if (ret) ++ pr_err("SetDfCstate failed!\n"); ++ ++ return ret; ++} ++ + static const struct pp_hwmgr_func vega20_hwmgr_funcs = { + /* init/fini related */ + .backend_init = vega20_hwmgr_backend_init, +@@ -4223,6 +4241,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = { + .set_asic_baco_state = vega20_baco_set_state, + .set_mp1_state = vega20_set_mp1_state, + .smu_i2c_bus_access = vega20_smu_i2c_bus_access, ++ .set_df_cstate = vega20_set_df_cstate, + }; + + int vega20_hwmgr_init(struct pp_hwmgr *hwmgr) +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 7bf9a14bfa0b..bd8c922dfd3e 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -355,6 +355,7 @@ struct pp_hwmgr_func { + int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state); + int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode); + int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire); ++ int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state); + }; + + struct pp_table_func { +diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h +index a0883038f3c3..0c66f0fe1aaf 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h +@@ -120,7 +120,8 @@ + #define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x5D + #define PPSMC_MSG_GetAVFSVoltageByDpm 0x5F + #define PPSMC_MSG_BacoWorkAroundFlushVDCI 0x60 +-#define PPSMC_Message_Count 0x61 ++#define PPSMC_MSG_DFCstateControl 0x63 ++#define PPSMC_Message_Count 0x64 + + typedef uint32_t PPSMC_Result; + typedef uint32_t PPSMC_Msg; +-- +2.17.1 + |